UPD75P3018AGK-BE9 NEC, UPD75P3018AGK-BE9 Datasheet
UPD75P3018AGK-BE9
Available stocks
Related parts for UPD75P3018AGK-BE9
UPD75P3018AGK-BE9 Summary of contents
Page 1
... Mask-option pull-up resistors are not provided in this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U11917EJ2V0DS00 (2nd edition) ...
Page 2
... On-chip pull-up resistor connection can be specified by using software Also used for segment pins 13 V breakdown voltage 40 • Segment number selection : 24/28/32 segments (can be changed to CMOS output port in unit of 4; max. 8) • ...
Page 3
... PIN FUNCTIONS .............................................................................................................................. 3.1 Port Pins ................................................................................................................................................... 3.2 Non-port Pins ........................................................................................................................................... 3.3 Pin Input/Output Circuits ......................................................................................................................... 10 3.4 Recommended Connection for Unused Pins ........................................................................................ 12 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ....................................... 13 4.1 Difference between Mk I Mode and Mk II Mode ..................................................................................... 13 4.2 Setting of Stack Bank Selection Register (SBS) ................................................................................... 14 5. DIFFERENCES BETWEEN PD75P3018A AND 6 ...
Page 4
... S26/BP2 15 S27/BP3 16 S28/BP4 17 S29/BP5 18 S30/BP6 19 20 S31/BP7 Note Connect the V directly to V during normal operation PIN IDENTIFICATIONS BIAS : LCD Power Supply Bias Control BP0-BP7 : Bit Port 0-7 BUZ : Buzzer Clock COM0-COM3 ...
Page 5
BLOCK DIAGRAM TIMER/EVENT PTO1/P21 COUNTER #1 PROGRAM TI1/TI2/ INTT1 COUNTER P12/INT2 TIMER/EVENT COUNTER PTO2/P22/PCL #2 INTT2 TOUT0 BASIC INTERVAL TIMER/ WATCHDOG TIMER INTBT TI0/P13 TIMER/EVENT COUNTER PTO0/P20 #0 PROGRAM MEMORY INTT0 TOUT0 32768 x 8 BITS WATCH BUZ/P23 TIMER ...
Page 6
... P10/INT0 can select noise elimination circuit. This is a 4-bit I/O port (PORT2). These are 4-bit pins for which an internal pull-up resistor connection can be specified by software. This is a programmable 4-bit I/O port (PORT3). Input and output in single-bit units can be specified. When set for 4-bit units, an internal pull-up resistor connection can be specified by software ...
Page 7
... BP0 to BP7. The output level varies depending on the external circuit LC1 for BP0 to BP7 and V . LC1 Example: As shown below, BP0 to BP7 are mutually connected via the PD75P3018A, so the output levels of BP0 to BP7 are determined by the sizes LC1 R ...
Page 8
... DD Vss — — Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input. 2. The V pin does not operate correctly during normal operation unless connected to the Function External event pulse input to timer/event counter Timer/event counter output Clock output Optional frequency output (for buzzer or system clock trimming) ...
Page 9
Non-port Pins (2/2) Pin Name I/O Alternate Function S0-S23 Output — S24-S31 Output BP0-BP7 COM0-COM3 Output — — — LC0- LC2 BIAS Output — Note 2 LCDCL I/O P30/MD0 Note 2 SYNC I/O P31/MD1 Notes 1. The ...
Page 10
Pin Input/Output Circuits The input/output circuits for the PD75P3018A’s pins are shown in abbreviated form below. TYPE P-ch IN N-ch CMOS standard input buffer TYPE B IN Schmitt trigger input with hysteresis characteristics. TYPE B-C V ...
Page 11
TYPE F-B P.U.R. enable Output V DD disable (P) P-ch Data Output N-ch disable Output disable (N) P.U.R. : Pull-Up Resistor TYPE G-A V LC0 V LC1 P-ch N-ch SEG N-ch data V LC2 N-ch TYPE G-B V LC0 V ...
Page 12
... Recommended Connection for Unused Pins Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0, P11/INT1 P12/TI1/TI2/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PTO2/PCL P23/BUZ P30/LCDCL/MD0 P31/SYNC/MD1 P32/MD2, P33/MD3 P40/D0-P43/D3 P50/D4-P53/D7 P60/KR0-P63/KR3 P70/KR4-P73/KR7 S0-S23 S24/BP0-S31/BP7 COM0-COM3 V -V LC0 LC2 BIAS XT1 Note Note XT2 Note When subsystem clock is not used, specify SOS ...
Page 13
SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE Setting a stack bank selection (SBS) register for the PD75P3018A enables the program memory to be switched between Mk I mode and Mk II mode. This function is applicable ...
Page 14
Setting of Stack Bank Selection Register (SBS) Use the stack bank selection register to switch between Mk I mode and Mk II mode. Figure 4-1 shows the format for doing this. The stack bank selection register is set using ...
Page 15
DIFFERENCES BETWEEN PD75P3018A AND The PD75P3018A replaces the internal mask ROM in the PD753012A, 753016A, and 753017A with a one-time PROM and features expanded ROM capacity. The PD75P3018A’ mode supports the Mk I mode in the PD753012A, ...
Page 16
MEMORY CONFIGURATION 6.1 Program Counter (PC) ... 15 bits This is a 15-bit binary counter that stores program memory address data. Bit 15 is valid during Mk II mode. But PC14 is fixed at zero during Mk I mode, ...
Page 17
Figure 6-2. Program Memory Map (Mk I mode 0000H MBE RBE Internal reset start address (high-order 6 bits) Internal reset start address (low-order 8 bits) 0002H MBE RBE INTBT/INT4 start address (high-order 6 bits) INTBT/INT4 start address ...
Page 18
Figure 6-3. Program Memory Map (Mk II mode 0000H MBE RBE Internal reset start address (high-order 6 bits) Internal reset start address (low-order 8 bits) 0002H MBE RBE INTBT/INT4 start address (high-order 6 bits) INTBT/INT4 start address ...
Page 19
Data Memory (RAM) ... 1024 4 bits Figure 6-4 shows the data memory configuration. Data memory consists of a data area and a peripheral hardware area. The data area consists of 1024 4-bit static RAM. General-purpose register area Display ...
Page 20
INSTRUCTION SET (1) Representation and coding formats for operands In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s operand representations (for further description, see the RA75X Assembler Package User’s Manual Language ...
Page 21
Operation legend register; 4-bit accumulator register register register register register register register XA : Register ...
Page 22
Description of symbols used in addressing area MB = MBE • MBS *1 MBS = 0- MBE = (000H-07FH (F80H-FFFH) MBE = ...
Page 23
Description of machine cycles S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as shown below. • No skip ..................................................................... • Skipped instruction is 1-byte or 2-byte ...
Page 24
Instruction Mnemonic Operand Group Transfer MOV A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL– A, @rpa1 XA, @HL @HL, A @HL mem XA, mem mem, A mem reg ...
Page 25
Instruction Mnemonic Operand Group Bit transfer MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY Arithmetic ADDS A, #n4 XA, #n8 A, @HL XA, rp’ rp’1, XA ADDC A, @HL XA, rp’ rp’1, XA SUBS A, ...
Page 26
Instruction Mnemonic Operand Group Comparison SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp’ Carry flag SET1 CY manipulation CLR1 CY SKT CY NOT1 CY Memory bit SET1 mem.bit manipulation fmem.bit pmem.@L @H+mem.bit CLR1 mem.bit fmem.bit ...
Page 27
Instruction Mnemonic Operand Group Branch BR Note 1 addr addr1 !addr $addr $addr1 PCDE PCXA BCDE BCXA Note 1 BRA !addr BRCB Note 1 !caddr Notes 1. Shaded areas indicate support for Mk II mode only. Other areas indicate support ...
Page 28
Instruction Mnemonic Operand Group Subroutine CALLA Note !addr1 stack control CALL Note !addr CALLF Note !faddr RET Note RETS Note Note RETI Note Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode ...
Page 29
Instruction Mnemonic Operand Group Subroutine PUSH rp stack control BS POP rp BS Interrupt EI control IEXXX DI IEXXX I/O IN Note 1 A, PORTn XA, PORTn Note 1 OUT PORTn, A PORTn, XA CPU control HALT STOP NOP Special ...
Page 30
... D4/P50 to D7/P53 (high-order 4 bits Caution Pins not used for program memory write/verify should be connected to V 8.1 Operation Modes for Program Memory Write/Verify When + applied to the V pin and +12 the V DD mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below. ...
Page 31
Program Memory Write Procedure Program memory can be written at high speed using the following procedure. (1) Pull unused pins to Vss through resistors. Set the X1 pin low. (2) Supply the V and V pins. ...
Page 32
Program Memory Read Procedure The PD75P3018A can read program memory contents using the following procedure. (1) Pull unused pins to Vss through resistors. Set the X1 pin low. (2) Supply the V and V pins. DD ...
Page 33
... One-time PROM Screening Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends that after the required data is written and the PROM is stored under the temperature and time conditions shown below, the PROM should be verified via a screening. ...
Page 34
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings ( Parameter Symbol Supply voltage V DD PROM supply voltage V PP Input voltage V Other than ports 4 and Ports 4 and 5 (During N-ch open ...
Page 35
Main System Clock Oscillator Characteristics (T Resonator Recommended Circuit Ceramic Oscillation frequency resonator ( Oscillation C1 C2 stabilization time V DD Crystal Oscillation frequency resonator ( Oscillation C1 C2 stabilization time V DD External X1 input ...
Page 36
Subsystem Clock Oscillator Characteristics (T Resonator Recommended Circuit Crystal Oscillation frequency resonator (f XT1 XT2 R Oscillation C3 C4 stabilization time V DD External XT1 input frequency clock (f XT1 XT2 XT1 input high-/ low-level width (t Notes 1. The ...
Page 37
DC Characteristics (T = – Parameter Symbol Low-level output I Per pin OL current Total of all pins High-level input V Ports 2, 3 IH1 voltage V Ports RESET IH2 V ...
Page 38
DC Characteristics (T = – Parameter Symbol LCD drive voltage V VAC0 = 0 T LCD T VAC0 = 1 VAC current Note 1 I VAC0 = 2.0 V 10% VAC DD ...
Page 39
... RSL Notes 1. The cycle time (minimum instruc- tion execution time) of the CPU clock ( ) is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (SCC), and processor clock control register (PCC). The figure on the right shows the supply voltage V vs ...
Page 40
Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK ... internal clock output): (T Parameter Symbol SCK cycle time 2.7 to 5.5 V KCY1 DD SCK high-/low-level width 2.7 to 5.5 ...
Page 41
SBI mode (SCK ... internal clock output (master)): (T Parameter Symbol SCK cycle time 2.7 to 5.5 V KCY3 DD SCK high-/low-level width 2.7 to 5.5 V KL3 KH3 DD SB0, 1 ...
Page 42
AC Timing Test Points (except X1 and XT1 inputs Clock Timing X1 input XT1 input TI0, TI1, TI2 Timing TI0, TI1, TI2 42 (MIN (MAX (MIN (MAX.) V ...
Page 43
Serial Transfer Timing 3-wire Serial I/O Mode SCK SI SO 2-wire Serial I/O Mode SCK SB0 KCY1 KL1,2 KH1 SIK1,2 KSI1,2 Input data t KSO1,2 Output data t KCY1 KL1,2 KH1,2 ...
Page 44
Serial Transfer Timing Bus Release Signal Transfer SCK t t KSB SBL SB0, 1 Command Signal Transfer SCK t KSB SB0, 1 Interrupt Input Timing INT0 KR0-7 RESET Input Timing RESET 44 t KCY3 ...
Page 45
Data retention characteristics of data memory in STOP mode and at low supply voltage (T Parameter Symbol Data retention power V DDDR supply voltage Release signal setup time t SREL Oscillation stabilization t Released by RESET WAIT wait time Note ...
Page 46
... Note 2 t HAD MD3 hold time (from MD0 ) t M3HR MD3 Data output float delay time t DFR Notes 1. Symbol of corresponding PD27C256A 2. The internal address signal is incremented the 4th rise of the X1 input, and is not connected to a pin 6.0 0. 12.5 0 Conditions MIN. 0. – ...
Page 47
Program Memory Write Timing t VPS VDS D0/P40-D3/P43 Data Input D4/P50-D7/P53 MD0/P30 t PW MD1/P31 PCR ...
Page 48
PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
Page 49
PLASTIC QFP (14x14 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
Page 50
PIN PLASTIC TQFP (FINE PITCH) (12x12 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
Page 51
PLASTIC TQFP (FINE PITCH) (12x12 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
Page 52
... Solder the PD75P3018A under the following recommended conditions. For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and conditions other than those recommended, consult NEC. Table 11-1. Soldering Conditions of Surface Mount Type (1/2) (1) PD75P3018AGC-3B9: 80-pin plastic QFP (14 ...
Page 53
... VPS Package peak temperature: 215 C, Reflow time: 40 seconds or below (200 C or higher), Number of reflow processes: 2 max., Exposure limit: 7 days (After that, prebaking is necessary at 125 C for 10 hours) Partial heating Pin temperature: 300 C or below, Time: 3 seconds or below (per side of device) Note The number of days for storage after the dry pack has been opened. The storage conditions are 25 C, 65% RH max. ...
Page 54
... Data memory 000H-3FFH (1024 CPU 75X Standard Instruction When main system 0.95, 1.91, or 15.3 s execution time clock is selected (at 4.19 MHz operation) When subsystem 122 s (at 32.768 kHz operation) clock is selected Pin connection P40 to P43 P50 to P53 44 P12/INT2 47 P21 48 P22/PCL P30 to P33 ...
Page 55
Parameter Clock output (PCL) , 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation) BUZ output (BUZ) 2 kHz (Main system clock: at 4.19 MHz operation) Serial interface 3 modes are available • 3-wire serial I/O mode ... ...
Page 56
APPENDIX B. DEVELOPMENT TOOLS The following development tools have been provided for system development using the PD75P3018A. In the 75XL Series, the relocatable assembler common to series is used in combination with the device file of each type. RA75X relocatable ...
Page 57
... PG-1500 This is a PROM programmer that can program single-chip microcontroller with PROM in stand alone mode or under control of host machine when connected with supplied accessory board and optional programmer adapter. It can also program typical PROMs in capacities ranging from 256 bits. ...
Page 58
... TGK-080SDW Note 2 It includes a 80-pin conversion adapter (TGK-080SDW) to facilitate connections with target system. Software IE control program This program can control the IE-75000-R or IE-75001 host machine when connected to the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface. Host machine PC-9800 Series IBM PC/AT or compatible Notes 1 ...
Page 59
OS for IBM PCs The following operating systems for the IBM PC are supported. PC DOS MS-DOS IBM DOS Caution Ver. 5.0 or later includes a task swapping function, but this software is not able to use that function. OS ...
Page 60
... Document Name SEMICONDUCTOR SELECTION GUIDE Products & Package (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices Electrostatic Discharge (ESD) Guide to Microcontroller-Related Products by Third Parties Caution The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents ...
Page 61
Data Sheet U11917EJ2V0DS00 PD75P3018A 61 ...
Page 62
... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
Page 63
... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • ...
Page 64
... The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. ...