MC68306FC16 Motorola, MC68306FC16 Datasheet

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... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. " ...

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... Ordering Information and Mechanical Data 68K FAX-IT – Documentation Comments FAX 512-891-8593—Documentation Comments Only The Motorola High-End Technical Publications Department provides a fax number for you to submit any questions or comments about this document or how to order other documents. We welcome your suggestions for improving our documentation. Please do not fax technical questions ...

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UNITED STATES ALABAMA, Huntsville ARIZONA, Tempe CALIFORNIA, Agoura Hills CALIFORNIA, Los Angeles CALIFORNIA, Irvine CALIFORNIA, Rosevllle CALIFORNIA, San Diego CALIFORNIA, Sunnyvale COLORADO , Colorado Springs COLORADO , Denver CONNECTICUT, Wallingford FLORIDA , Maitland FLORIDA , Pompano Beach/ Fort Lauderdale FLORIDA ...

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... DRAM Multiplexed Address Bus (DRAMA14 –DRAMA0) ..................................... 2-6 2.1.10 Processor Function Codes (FC2–FC0).............................................................. 2-6 2.1.11 Halt (HALT) ........................................................................................................ 2-7 2.1.12 Read/Write (R/W) ............................................................................................... 2-7 2.1.13 Upper And Lower Data Strobes (UDS , LDS ) ..................................................... 2-7 2.1.14 Upper Byte Write (UW ) ...................................................................................... 2-8 2.1.15 Lower Byte Write (LW )....................................................................................... 2-8 2.1.16 Output Enable (OE) ........................................................................................... 2-8 2.1.17 Reset (RESET ) .................................................................................................. 2-8 2.2 Chip Select Signals................................................................................................. 2-9 MOTOROLA Title Section 1 Introduction Section 2 Signal Descriptions MC68306 USER'S MANUAL Page Number v ...

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... Test Clock (TCK) ................................................................................................. 2-12 2.7.2 Test Mode Select (TMS)...................................................................................... 2-12 2.7.3 Test Data In (TDI) ................................................................................................ 2-12 2.7.4 Test Data Out (TDO) ........................................................................................... 2-12 2.7.5 Test Reset (TRST) .............................................................................................. 2-12 3.1 Data Transfer Operations ....................................................................................... 3-1 3.1.1 Read Cycle .......................................................................................................... 3-1 3.1.2 Write Cycle .......................................................................................................... 3-4 3.1.3 Read-Modify-Write Cycle..................................................................................... 3-7 3.1.4 CPU Space Cycle ................................................................................................ 3-11 vi Title Section 3 68000 Bus Operation Description MC68306 USER'S MANUAL Page Number MOTOROLA ...

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... Exception Vectors ................................................................................................ 4-14 4.6 Processing of Specific Exceptions .......................................................................... 4-16 4.6.1 Reset Exception................................................................................................... 4-17 4.6.2 Interrupt Exceptions ............................................................................................. 4-17 4.6.3 Uninitialized Interrupt Exception .......................................................................... 4-18 4.6.4 Spurious Interrupt Exception................................................................................ 4-18 4.6.5 Instruction Traps .................................................................................................. 4-18 4.6.6 Illegal and Unimplemented Instructions ............................................................... 4-18 4.6.7 Privilege Violations............................................................................................... 4-19 4.6.8 Tracing ................................................................................................................. 4-19 4.6.9 Bus Error .............................................................................................................. 4-20 4.6.10 Address Error ..................................................................................................... 4-21 4.6.11 Multiple Exceptions ............................................................................................ 4-21 MOTOROLA Title Section 4 EC000 Core Processor MC68306 USER'S MANUAL Page Number vii ...

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... Channel A Receiver Serial Data Input (RxDA) .................................................... 6-5 6.2.5 Channel B Transmitter Serial Data Output (TxDB).............................................. 6-5 6.2.6 Channel B Receiver Serial Data Input (RxDB) .................................................... 6-6 6.2.7 Channel A Request-To-Send (RTSA/OP0) ......................................................... 6-6 6.2.7.1 RTSA ................................................................................................................ 6-6 6.2.7.2 OP0 .................................................................................................................. 6-6 6.2.8 Channel B Request-To-Send (RTSB/OP1) ......................................................... 6-6 viii Title Section 5 System Operation Section 6 Serial Module MC68306 USER'S MANUAL Page Number MOTOROLA ...

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... Input Port Change Register (DUIPCR) ............................................................. 6-29 6.4.1.9 Auxiliary Control Register (DUACR) ................................................................ 6-30 6.4.1.10 Interrupt Status Register (DUISR) .................................................................. 6-31 6.4.1.11 Interrupt MASK Register (DUIMR).................................................................. 6-33 6.4.1.12 Count Register Current MSB of Counter (DUCUR) ........................................ 6-33 6.4.1.13 Count Register Current LSB of Counter (DUCLR) ......................................... 6-33 6.4.1.14 Counter/Timer Upper Preload Register (CTUR) ............................................. 6-34 MOTOROLA Title MC68306 USER'S MANUAL Page Number ix ...

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... AC Electrical Specifications—Bus Arbitration ......................................................... 8-10 8.10 Bus Operation—DRAM Accesses AC Timing Specifications ............................... 8-12 8.11Serial Module Electrical Characteristics ................................................................ 8-15 8.12 Serial Module AC Electrical Characteristics—Clock Timing ................................. 8-16 8.13 AC Electrical Characteristics—Port Timing .......................................................... 8-16 8.14 AC Electrical Characteristics—Interrupt Reset ..................................................... 8-16 x Title Section 7 IEEE 1149.1 Test Access Port Section 8 Electrical Specifications MC68306 USER'S MANUAL Page Number MOTOROLA ...

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... TABLE OF CONTENTS (Continued) Paragraph Number 8.14 AC Electrical Characteristics—Interrupt Reset ..................................................... 8-16 8.15 AC Electrical Characteristics—Transmitter Timing ............................................... 8-17 8.16 AC Electrical Characteristics—Receiver Timing ................................................... 8-18 8.17 IEEE 1149.1 Electrical Characteristics ................................................................. 8-19 Ordering Information and Mechanical Data 9.1 Standard Ordering Information ............................................................................... 9-1 9.2 Pin Assignments ..................................................................................................... 9-2 MOTOROLA Title Section 9 MC68306 USER'S MANUAL Page Number xi ...

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... Figure 3-26. Halt Operation Timing Diagram............................................................ 3-28 Figure 3-27. Reset Operation Timing Diagram......................................................... 3-29 Figure 3-28 Fully Asynchronous Read Cycle ........................................................... 3-32 Figure 3-29. Fully Asynchronous Write Cycle........................................................... 3-32 Figure 3-30. Pseudo-Asynchronous Read Cycle ..................................................... 3-33 Figure 3-31. Pseudo-Asynchronous Write Cycle...................................................... 3-34 Figure 3-32. Synchronous Read Cycle..................................................................... 3-36 Figure 3-33. Synchronous Write Cycle ..................................................................... 3-37 xii Title MC68306 USER'S MANUAL Page Number MOTOROLA ...

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... Figure 8-5. Chip Select and Interrupt Acknowledge Timing Diagram ....................... 8-9 Figure 8-6. Bus Arbitration Timing Diagram ............................................................. 8-10 Figure 8-7. Bus Arbitration Timing Diagram ............................................................. 8-11 Figure 8-8. DRAM Timing – 0-Wait Read, No Refresh ............................................. 8-13 Figure 8-9. DRAM Timing – 1-Wait Write, No Refresh ............................................. 8-14 Figure 8-10. DRAM Timing – 0- and 1-Wait Refresh ................................................ 8-14 MOTOROLA Title MC68306 USER'S MANUAL Page Number xiii ...

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... Figure 8-12. Clock Timing......................................................................................... 8-16 Figure 8-13. Port Timing ........................................................................................... 8-16 Figure 8-14. Interrupt Reset Timing .......................................................................... 8-17 Figure 8-15. Transmit Timing ................................................................................... 8-17 Figure 8-16. Receive Timing .................................................................................... 8-18 Figure 8-17. Test Clock Input Timing Diagram ......................................................... 8-19 Figure 8-18. Boundary Scan Timing Diagram .......................................................... 8-20 Figure 8-19. Test Access Port Timing Diagram ........................................................ 8-20 xiv Title MC68306 USER'S MANUAL Page Number MOTOROLA ...

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... Table 6-3. CMx Control Bits...................................................................................... 6-21 Table 6-4. SBx Control Bits ...................................................................................... 6-22 Table 6-5. RCSx Control Bits.................................................................................... 6-25 Table 6-6. TCSx Control Bits .................................................................................... 6-26 Table 6-7. MISCx Control Bits .................................................................................. 6-27 Table 6-8. TCx Control Bits ...................................................................................... 6-28 Table 6-9. RCx Control Bits ...................................................................................... 6-28 Table 6-10. Counter/Timer Mode and Source Select Bits ........................................ 6-30 MOTOROLA LIST OF TABLES Title MC68306 USER'S MANUAL Page Number xv ...

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... LIST OF TABLES (Continued) Table Number Table 7-1. Boundary Scan Control Bits .................................................................... 7-4 Table 7-2. Boundary Scan Bit Definitions ................................................................. 7-5 Table 7-3. Instructions .............................................................................................. 7-10 xvi Title MC68306 USER'S MANUAL Page Number MOTOROLA ...

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... Figure 1-1 shows a simplified block diagram of the MC68306. 8 Figure 1-1. MC68306 Simplified Block Diagram MOTOROLA 8 DRAM PORT A CONTROLLER EC000 ...

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... The integrated chip selects allow peripherals and data in memory to reside anywhere in the 4-Gbyte linear address space. A supervisor operating mode protects system-level resources from the more restricted user mode, allowing a true virtual environment to be developed. Many addressing modes complement 1-2 MC68306 USER'S MANUAL MOTOROLA ...

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... A and B, a periodic interrupt generator variable duty cycle square-wave generator. 1.2.2 DRAM Controller DRAM is used in many systems since it is the least expensive form of high-speed storage available. However, considerable design effort is often spent designing the interface MOTOROLA MC68306 USER'S MANUAL 1- 3 ...

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... For maximum flexibility, interrupts can be vectored to the correct service routine by the interrupting device. 1.2.6 Clock To save on system costs, the MC68306 has an on-board oscillator that can be driven with a 16.67-MHz crystal. A bus clock output is provided by a CLKOUT pin. Alternatively, an 1-4 MC68306 USER'S MANUAL MOTOROLA ...

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... IEEE 1149.1 Test To aid in system diagnostics, the MC68306 includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1 standard for boundary scan testability, often referred to as JTAG (Joint Test Action Group). MOTOROLA MC68306 USER'S MANUAL 1- 5 ...

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... The term assert or assertion is used to indicate that a signal is active or true, independent of whether that level is represented by a high or low voltage. The term negate or negation is used to indicate that a signal is inactive or false. MOTOROLA NOTE MC68306 USER'S MANUAL 2- 1 ...

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... PROCESSOR TWO- 16-BIT CHANNEL TIMER/ SERIAL COUNTER I/O PORT A FLOW CONTROL MC68306 USER'S MANUAL A19–A16 A15/DRAMA14–A1/DRAMA0 D15–D0 FC2–FC0 RESET BERR HALT AS UDS LDS R DTACK BR BG BGACK X2 X1/CLK RxDA TxDA RxDB TxDB RTSB/OP1 RTSA/OP0 CTSB/IP1 CTSA/IP0 MOTOROLA ...

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... Table 2-2. Chip Select Signal Summary Signal Name Chip Select Chip Select 4–7/Address Port 23 – 20 Table 2-3. DRAM Controller Signal Summary Signal Name Column Address Strobe Row Address Strobe DRAM Write Signal MOTOROLA Table 2-1. Bus Signal Summary Input/ Mnemonic Output A23–A1 Output Output AS I/O ...

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... Input/ Mnemonic Output EXTAL Input XTAL Output CLKOUT Output AMODE Input MC68306 USER'S MANUAL Three-State During Pullup Required Bus Arbitration — (2) — (2) — (2) — (2) — (2) — — (2) — (2) — (2) — (2) — (2) Three-State During Pullup Required Bus Arbitration — — No — MOTOROLA ...

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... This 23-bit, unidirectional, three-state bus is capable of addressing 16 Mbytes of data. This bus provides the address for bus operation during all cycles except interrupt acknowledge cycles. During interrupt acknowledge cycles, address lines A1, A2, and A3 provide the level number of the interrupt being acknowledged, and address lines A23–A4 MOTOROLA Input/ Mnemonic Output ...

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... Address strobe is inactive, which indicates that the microprocessor is not using the bus. 3. Data transfer acknowledge is inactive, which indicates that neither memory nor peripherals are using the bus. 4. Bus grant acknowledge is inactive, which indicates that no other device is claiming bus mastership. 2 BGACK ) MC68306 USER'S MANUAL MOTOROLA ...

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... External assertion of this bi-directional signal causes the processor to stop bus activity at the completion of the bus cycle for which the input met set-up time requirements (i.e., current or next cycle). This operation places all control signals in the inactive state. For MOTOROLA DTACK ) FC1 FC0 ...

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... Valid Data Bits Valid Data Bits 7–0* 7–0 Valid Data Bits Valid Data Bits 15–8 15– MC68306 USER'S MANUAL ) High High High Low High High Low High High Low High High High Low Low High High Low High Low High MOTOROLA ...

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... These three-state signals provide row address strobe timing for external DRAM. Each RAS controls a separate bank of DRAM. 2.3.3 DRAM Write Signal ( This signal provides write control for external DRAM. 2.4 INTERRUPT CONTROL AND PARALLEL PORT SIGNALS The following signals are used for interrupt control on the MC68306. MOTOROLA CAS1 CAS0 – ...

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... A23–A20 is selected and when set to one, CS7–CS4 is selected. The mode selection is static: AMODE is latched at the end of any system reset. 2.6 SERIAL MODULE SIGNALS The following paragraphs describe the signals used by the serial module on the MC68306. 2-10 IACK7 IACK1 – ) MC68306 USER'S MANUAL MOTOROLA ...

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... A change-of-state detector is also associated with this input. RTSB 2.6.8 This output can be used as a general-purpose output or the channel B active low request- to-send (RTSB) output. When used for this function automatically negated and reasserted by either the receiver or transmitter. MOTOROLA MC68306 USER'S MANUAL 2- 11 ...

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... Test Data Out (TDO) This output is used for serial test instructions and test data for on-chip test logic defined by the IEEE 1149.1 standard. TRST 2.7.5 Test Reset ( This input is the master reset for on-chip test logic defined by the IEEE 1149.1 standard. 2-12 ) MC68306 USER'S MANUAL MOTOROLA ...

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... A0 bit to determine which byte to read and issues the appropriate data strobe. When A0 is zero, the upper data strobe is issued; when A0 is one, the lower data strobe is issued. When the data is received, the processor internally positions the byte appropriately. MOTOROLA NOTE MC68306 USER'S MANUAL ...

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... DECODE ADDRESS 2) PLACE DATA ON D7–D0 OR D15–D8 (BASED ON UDS OR LDS) 3) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) 1) REMOVE DATA FROM D7–D0 OR D15–D8 2) NEGATE DTACK MC68306 USER'S MANUAL SLAVE OUTPUT THE DATA TERMINATE THE CYCLE SLAVE OUTPUT THE DATA TERMINATE THE CYCLE MOTOROLA ...

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... CLK FC2–FC0 A31– UDS LDS R/W DTACK D15–D8 D7–D0 READ *Internal Signal Only Figure 3-4. Word and Byte Read Cycle Timing Diagram MOTOROLA WRITE WRITE MC68306 USER'S MANUAL WAIT STATE READ READ 3- 3 ...

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... If the instruction specifies a word or long-word operation, the processor issues both UDS and LDS and writes both bytes. A long-word write is accomplished by two consecutive word writes. When the instruction specifies a byte operation, the processor uses the internal A0 bit to determine which byte to write and issues the appropriate data 3-4 MC68306 USER'S MANUAL MOTOROLA ...

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... TERMINATE OUTPUT TRANSFER 1) NEGATE UDS AND LDS 2) NEGATE AS 3) REMOVE DATA FROM D15–D0 4) SET R/W TO READ START NEXT CYCLE Figure 3-5. Word Write Cycle Flowchart MOTOROLA 1) DECODE ADDRESS 2) LATCH DATA ON D15–D0 3) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) 1) NEGATE DTACK MC68306 USER'S MANUAL ...

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... Figure 3-7. Word and Byte Write Cycle Timing Diagram 3-6 1) DECODE ADDRESS 2) LATCH DATA ON D7–D0 IF LDS IS ASSERTED. LATCH DATA ON D15–D8 IF UDS IS ASSERTED 3) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) 1) NEGATE DTACK ODD BYTE WRITE MC68306 USER'S MANUAL SLAVE INPUT THE DATA TERMINATE THE CYCLE EVEN BYTE WRITE MOTOROLA ...

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... The address strobe ( AS) remains asserted throughout the entire cycle, making the cycle indivisible. The test and set (TAS) instruction uses this cycle to provide a signaling capability without deadlock between processors in a multiprocessing environment. The TAS instruction (the only instruction MOTOROLA MC68306 USER'S MANUAL 3- 7 ...

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... ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) 1) REMOVE DATA FROM D7–D0 OR D15–D8 2) NEGATE DTACK 1) STORE DATA ON D7–D0 OR D15–D8 2) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) 1) NEGATE DTACK MC68306 USER'S MANUAL SLAVE OUTPUT THE DATA TERMINATE THE CYCLE INPUT THE DATA TERMINATE THE CYCLE MOTOROLA ...

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... UDS /LDS . The device negates DTACK at this time. STATES 8–11 The bus signals are unaltered during S8–S11, during which the arithmetic logic unit makes appropriate modifications to the data. MOTOROLA S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 INDIVISIBLE CYCLE MC68306 USER'S MANUAL 3- 9 ...

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... During S6, no bus signals are altered.. STATE 7 During S7, no bus signals are altered. STATE 8 During S8, no bus signals are altered. STATE 9 AS and /LDS are negated. The cycle terminates without the write portion. Case W2: BERR only on write. 3-10 MC68306 USER'S MANUAL MOTOROLA ...

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... A3–A1 and drives all other address lines high. The interrupt acknowledge cycle reads a vector number when the device places a vector number on the data bus. The timing diagram for an interrupt acknowledge cycle is shown in Figure 3-11. MOTOROLA MC68306 USER'S MANUAL ...

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... Figure 3-12. This technique allows processing of bus requests during data transfer cycles. 3- IACK CYCLE STACK (VECTOR NUMBER PCL ACQUISITION) (SSP) MC68306 USER'S MANUAL STACK AND VECTOR FETCH MOTOROLA ...

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... TO BE NEGATED REMAINS ASSERTED AFTER BGACK ASSERTED, RE-ASSERT BG. REARBITRATE OR RESUME PROCESSOR OPERATION Figure 3-12. Three-Wire Bus Arbitration Cycle Flowchart MOTOROLA 1) ASSERT BUS REQUEST (BR) ACKNOWLEDGE BUS MASTERSHIP 1) EXTERNAL ARBITRATION DETER- MINES NEXT BUS MASTER 2) NEXT BUS MASTER WAITS FOR CURRENT CYCLE TO COMPLETE ...

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... Figure 3-13. Two-Wire Bus Arbitration Cycle Flowchart 3-14 1) ASSERT BUS REQUEST (BR) 1) EXTERNAL ARBITRATION DETER- MINES NEXT BUS MASTER 2) NEXT BUS MASTER WAITS FOR CURRENT CYCLE TO COMPLETE 1) NEGATE BUS REQUEST (BR) MC68306 USER'S MANUAL REQUESTING DEVICE REQUEST THE BUS OPERATE AS BUS MASTER RELEASE BUS MASTERSHIP MOTOROLA ...

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... Figure 3-14. Three-Wire Bus Arbitration Timing Diagram CLK FC2–FC0 A19– R/W DTACK D7– PROCESSOR DMA DEVICE Figure 3-15. Two-Wire Bus Arbitration Timing Diagram MOTOROLA DMA DEVICE PROCESSOR PROCESSOR MC68306 USER'S MANUAL DMA DEVICE DMA DEVICE 3- 15 ...

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... DTACK might not be included in this function; general-purpose devices would be connected using AS only.) When BGACK is asserted, the asserting device is bus master until it negates BGACK . BGACK should not be negated until after the bus cycle(s) is complete. A device relinquishes control of the bus by negating BGACK . 3-16 MC68306 USER'S MANUAL MOTOROLA ...

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... A timing diagram of the bus arbitration sequence during a processor bus cycle is shown in Figure 3-18. The bus arbitration timing while the bus is inactive (e.g., the processor is performing internal operations for a multiply instruction) is shown in Figure 3-19. MOTOROLA CLK 47 MC68306 USER'S MANUAL ...

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... STATE STATE 3 R (b) 2-Wire Bus Arbitration MC68306 USER'S MANUAL STATE 4 Notes: 1. State machine will not change if the bus S1. Refer to BUS ARBITRATION CONTROL. 5.2.3. 2. The address bus will be placed in the high-impedance state asserted and AS is negated. MOTOROLA ...

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... AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 3-18. Three-Wire Bus Arbitration Timing Diagram—Processor Active MOTOROLA BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BGACK NEGATED INTERNAL BGACK SAMPLED BGACK NEGATED ALTERNATE BUS MASTER MC68306 USER'S MANUAL ...

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... BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A31–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 3-19. Three-Wire Bus Arbitration Timing Diagram—Bus Inactive 3-20 BUS ALTERNATE BUS MASTER INACTIVE MC68306 USER'S MANUAL PROCESSOR MOTOROLA ...

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... A31–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 3-20. Three-Wire Bus Arbitration Timing Diagram—Special Case MOTOROLA BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BGACK NEGATED INTERNAL BGACK SAMPLED BGACK NEGATED S4 S6 ALTERNATE BUS MASTER MC68306 USER'S MANUAL ...

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... LDS R/W DTACK D15–D0 PROCESSOR Figure 3-21. Two-Wire Bus Arbitration Timing Diagram—Processor Active 3-22 BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BR NEGATED INTERNAL BR SAMPLED BR NEGATED ALTERNATE BUS MASTER MC68306 USER'S MANUAL PROCESSOR MOTOROLA ...

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... BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A31–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 3-22. Two-Wire Bus Arbitration Timing Diagram—Bus Inactive MOTOROLA BUS ALTERNATE BUS MASTER INACTIVE MC68306 USER'S MANUAL PROCESSOR 3- 23 ...

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... For the write portion of a read-modify-write cycle, the current bus cycle is terminated in S19 (DTACK and BERR together) or S21 3-24 BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BR NEGATED INTERNAL BR SAMPLED BR NEGATED S4 S6 ALTERNATE BUS MASTER MC68306 USER'S MANUAL PROCESSOR MOTOROLA ...

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... The processor resumes execution at the address in the vector, which is the first instruction in the bus error handler routine. 3.4.2 Retrying the Bus Cycle The assertion of the bus error signal during a bus cycle in which HALT is also asserted by an external device initiates a retry operation. Figure 3- timing diagram of the retry operation. MOTOROLA ...

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... While the processor is halted, bus arbitration is performed as usual. Should a bus error occur while HALT is asserted, the processor performs the retry operation previously described RESET instruction is executed while HALT is asserted, the CPU will be reset. 3- CLOCK PERIOD HALT NOTE NOTE MC68306 USER'S MANUAL RETRY MOTOROLA ...

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... The reset operation is described in the following paragraph. 3.5 RESET OPERATION RESET is asserted externally for the initial processor reset. Subsequently, the signal can be asserted either externally or internally (executing a RESET instruction). MOTOROLA S6 HALT MC68306 USER'S MANUAL S0 ...

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... DTACK, BERR , and HALT are asserted and negated on the rising edge of the processor clock. 3-28 T 100 MILLISECONDS CLOCKS Bus State Unknown: All Control Signals Inactive. Data Bus in Read Mode: DTACK BERR , , AND MC68306 USER'S MANUAL HALT Ñ Read and Write MOTOROLA ...

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... A — Signal asserted in this bus state NA — Signal not asserted in this bus state X — Don't care S — Signal asserted in preceding bus state and remains asserted in this state NOTE: All operations are subject to relevant setup and hold times. MOTOROLA DTACK BERR HALT , ...

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... Illegal sequence; usually traps to vector number 0. • • Reruns the bus cycle. • • May lengthen next cycle. • or • • If next cycle is started, it will be terminated as a bus • or none error. MC68306 USER'S MANUAL Results—Next Cycle MOTOROLA ...

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... With the system clock frequency known, the slave device can be designed to decode the address bus before recognizing an address strobe. Parameter #11 (refer to AC Electrical Specifications—Read and Write Cycles) specifies the minimum time before address strobe during which the address is valid. MOTOROLA MC68306 USER'S MANUAL 3- 31 ...

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... If DTACK remains asserted past the time specified by parameter #28, the processor may recognize it as being asserted early in the next bus cycle and may terminate that cycle prematurely. Figure 3-31 shows the important timing specifications for a pseudo-asynchronous write cycle. 3- MC68306 USER'S MANUAL 28 29 MOTOROLA ...

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... Also, the R/W signal is driven high; parameter #18 defines the delay from the same rising edge to the transition of R/W . The minimum value for parameter #18 applies to a read cycle preceded by a write cycle; this value is the maximum hold time for a low on R/W beyond the initiation of the read cycle. MOTOROLA 11 20A 22 55 ...

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... The hold time for data relative to the negation and /LDS is specified by parameter #29. For a write cycle, only AS and UDS /LDS , are negated; timing parameter #12 also applies. 3-34 MC68306 USER'S MANUAL MOTOROLA ...

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... Figure 3-32 shows a synchronous read cycle and the important timing parameters that apply. The timing for a synchronous read cycle, including relevant timing parameters, is shown in Figure 3-33. S0 CLOCK 6 ADDR AS UDS/LDS 18 R/W DTACK DATA Figure 3-32. Synchronous Read Cycle MOTOROLA MC68306 USER'S MANUAL ...

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... If DTACK is asserted with the required setup time before the falling edge of S4, no wait states are incurred, and the bus cycle runs at its maximum speed of four clock periods. 3- MC68306 USER'S MANUAL MOTOROLA ...

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... Only an external reset can restart a halted processor. Note that when the processor executes a STOP instruction special type of normal processing state, one without bus cycles. The processor stops, but it does not halt. MOTOROLA MC68306 USER'S MANUAL 4- 1 ...

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... ADDRESS REGISTERS A7/USP USER STACK POINTER PROGRAM COUNTER PC CONDITION CODE REGISTER CCR USER PROGRAMMING MODEL 0 SSP SUPERVISOR STACK POINTER (CCR) SR STATUS REGISTER (CCR IS ALSO SHOWN IN THE USER PROGRAMMING MODEL) SUPERVISOR PROGRAMMING MODEL Figure 4-1. Programmer's Model MC68306 USER'S MANUAL EC1 MOTOROLA ...

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... Table 4-1 lists the data formats for the processor. Refer to M68000PM/AD, M68000 Family Programmer’s Reference Manual, for details on data format organization in registers and memory. Table 4-1. Processor Data Formats Operand Data Format Bit Binary-Coded Decimal (BCD) Byte Integer Word Integer Long-Word Integer MOTOROLA SYSTEM BYTE ...

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... Register Indirect with Offset Indexed Register Indirect with Offset Immediate Data Addressing Immediate Quick Immediate Implied Addressing Implied Register 4-4 Syntax EA=Dn EA=An EA=(Next Word) EA=(Next Two Words) EA=(PC)+d 16 EA=(PC)+d 8 EA=(An) EA=(An), An ¨ An+N An ¨ An–N, EA=(An) EA=(An)+d 16 EA=(An)+(Xn)+d 8 DATA=Next Word(s) Inherent Data EA=SR, USP, SSP, PC, VBR, SFC, DFC MC68306 USER'S MANUAL MOTOROLA ...

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... Any Address or Data Register Rx, Ry Any source and destination registers, respectively. Xn Index Register—An, Dn, or suppressed. MOTOROLA Table 4-3. Notation Conventions Single and Double Operand Operations Other Operations Offset Word ˘ (SSP); SSP – 2 ˘ SSP; PC ˘ (SSP); SSP – 4 ˘ SSP; SR ...

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... A scale factor ( for no-word, word, long-word, or quad-word scaling, respectively). SIZE The index register’s size (W for word, L for long word). {offset:width} Bit field selection. CCR Condition Code Register (lower byte of status register) PC Program Counter SR Status Register 4-6 Data Format And Type Subfields and Qualifiers Register Names MC68306 USER'S MANUAL MOTOROLA ...

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... Table 4-3. Notation Conventions (Concluded) * General Case. C Carry Bit in CCR cc Condition Codes from CCR FC Function Code N Negative Bit in CCR U Undefined, Reserved for Motorola Use. V Overflow Bit in CCR X Extend Bit in CCR Z Zero Bit in CCR — Not Affected or Applicable. SP Active Stack Pointer SSP Supervisor Stack Pointer ...

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... ANDI #<data>,<ea> ANDI #<data>,CCR ANDI #<data>,SR SR ˘ SR ASd Dx,Dy 1 ASd #<data>,Dy 1 ASd <ea> 1 Bcc <label> BCHG Dn,<ea> BCHG #<data>,<ea> BCLR Dn,<ea> BCLR #<data>,<ea> BRA <label> BSET Dn,<ea> BSET #<data>,<ea> BSR <label> BTST Dn,<ea> BTST #<data>,<ea> CHK <ea>,Dn CLR <ea> CMP <ea>,Dn CMPA <ea>,An CMPI #<data>,<ea> MC68306 USER'S MANUAL Syntax MOTOROLA ...

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... Source ˘ CCR MOVE supervisor state then Source ˘ SR else TRAP MOVE USP If supervisor state then USP ˘ ˘ USP else TRAP MOTOROLA Operation –1 then ˘ PC) Destination ˘ Destination SR ˘ SR MC68306 USER'S MANUAL Syntax CMPM (Ay)+,(Ax)+ DBcc Dn,<label> ...

Page 78

... NEG <ea> NEGX <ea> NOP NOT <ea> OR <ea>,Dn OR Dn,<ea> ORI #<data>,<ea> ORI #<data>,CCR ORI #<data>,SR PEA <ea> RESET ROd Rx,Dy 1 ROd #<data>,Dy 1 ROXd Dx,Dy 1 ROXd #<data>,Dy 1 ROXd <ea> 1 RTE RTR RTS MC68306 USER'S MANUAL Syntax 16 16 ˘ ˘ ˘ ˘ ˘ ˘ 64 MOTOROLA ...

Page 79

... SR ˘ (SSP); Vector Address ˘ PC TRAPV If V then TRAP TST Destination Tested ˘ Condition Codes UNLK An ˘ SP; (SP) ˘ An ˘ SP NOTES direction, left or right. 2. List refers to register. MOTOROLA Operation SBCD Dx,Dy SBCD –(Ax),–(Ay) Scc <ea> STOP #<data> SUB <ea>,Dn SUB Dn,<ea> SUBA <ea>,An SUBI #<data>,<ea> SUBQ #<data>,<ea> ...

Page 80

... For interrupts, the processor performs an interrupt acknowledge bus cycle to obtain the vector number. For all other exceptions, internal logic provides the vector number. This vector number is used in the last step to calculate the address of the exception vector. Throughout this section, vector numbers are given in decimal notation. 4-12 MC68306 USER'S MANUAL MOTOROLA ...

Page 81

... SAVE INTERNAL FETCH VECTOR SAVE CONTENTS TO STACK FRAME EXECUTE EXCEPTION BEGIN INSTRUCTION NOTE: These blocks vary for reset and interrupt exceptions. Figure 4-3. General Exception Processing Flowchart MOTOROLA ENTRY COPY (SEE NOTE) NUMBER OTHERWISE BUS ERROR (DOUBLE BUS FAULT) ...

Page 82

... In the EC000 core this offset is used as the absolute address to obtain the exception vector itself, which is illustrated in Figure 4-6. 4-14 EVEN BYTE ODD BYTE 0 7 STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW MC68306 USER'S MANUAL 0 0 HIGHER ADDRESS MOTOROLA ...

Page 83

... Of the 255, 192 are reserved for user interrupt vectors. However, the first 64 entries are not protected, so user interrupt vectors may overlap at the discretion of the systems designer. MOTOROLA EVEN BYTE (A0=0) NEW PROGRAM COUNTER (HIGH) ...

Page 84

... NOTES: 1. Vector numbers 12, 13, 16–23, and 48–63 are reserved for future enhancements by Motorola. No user peripheral devices should be assigned these numbers. 2. Reset vector (0) requires four words, unlike the other vectors which only require two words, and is located in the supervisor program space. ...

Page 85

... If external logic requests an automatic vector, the processor internally generates a vector number corresponding to the interrupt level number. If external logic indicates a bus error, MOTOROLA MC68306 USER'S MANUAL 4- 17 ...

Page 86

... Illegal and Unimplemented Instructions Illegal instruction is the term used to refer to any of the word bit patterns that do not match the bit pattern of the first word of a legal processor instruction. If such an instruction is fetched, an illegal instruction exception occurs. Motorola reserves the right to define 4-18 MC68306 USER'S MANUAL ...

Page 87

... M68000 family-compatible microprocessors. The patterns are: $4AFA, $4AFB, and $4AFC. Two of the patterns, $4AFA and $4AFB, are reserved for Motorola system products. The third pattern, $4AFC, is reserved for customer use (as the take illegal instruction trap (ILLEGAL) instruction). ...

Page 88

... If a bus error occurs during the last step of exception processing, while either reading the exception vector or fetching the instruction, the value of the program counter is the address of the exception vector. Although this information is not generally sufficient to effect full recovery from the bus 4-20 MC68306 USER'S MANUAL MOTOROLA ...

Page 89

... Within group 0, reset has highest priority, followed by address error and then bus error. Within group 1, trace has priority over external interrupts, which in turn takes priority over illegal instruction and privilege violation. Since only one instruction can be executed at a time, no priority relationship applies within group 2. MOTOROLA ...

Page 90

... Processing Exception processing begins within two clock cycles. Exception processing begins before the next instruction. Exception processing is started by normal instruction execution. MC68306 USER'S MANUAL MOTOROLA ...

Page 91

... The full 32-bit address capability of the MC68306 (corresponding to a 4-Gbyte address space) is decoded internally. A small portion of this address space is devoted to internal resources such as the serial module, configuration registers, and parallel ports. Table 5 memory map of the MC68306. MOTOROLA NOTE RESET External ...

Page 92

... CHIP SELECT 0 CONFIGURATION (HIGH) RESERVED 2 RESERVED RESERVED AVAILABLE FOR CHIP SELECT/DRAM AVAILABLE FOR CHIP SELECT/DRAM INTERRUPT ACKNOWLEDGE: VECTOR SUPPLIED ON D7–D0 MC68306 USER'S MANUAL D(7–0) (ODD ADDRESS) TIMER VECTOR BUS TIMEOUT PERIOD 2 PORT B PIN ASSIGNMENT PORT B DATA DIRECTION PORT B DATA 2 3 SERIAL MODULE 4 MOTOROLA ...

Page 93

... This bit selects the function of the multiplexed address and chip select pins. The address mode pin is latched at the end of reset, so the value must be valid and stable at this time. Writes to this bit are ignored Address lines selected Chip select lines selected. MOTOROLA ...

Page 94

... TVEC TVEC TVEC TVEC TVEC SUPERVISOR ONLY BT6 BT5 BT4 BT3 BT2 SUPERVISOR ONLY EXTAL MC68306 USER'S MANUAL 1 0 TVEC TVEC BT1 BT0 U U MOTOROLA ...

Page 95

... Interrupts enabled. IEN7–1—Interrupt Enable 7 through 1 These bits enable interrupt and Interrupt disabled Interrupt enabled. AVEC7–1—Autovector Enable 7 through 1 These bits enable autovectoring for interrupts and autovector. MOTOROLA IEN3 IEN2 IEN1 — ...

Page 96

... IRQ3 IRQ2 IRQ1 IRQD IX7 IRQ7 MC68306 USER'S MANUAL IX6 IX5 IX4 IX3 IX2 PB7/IR PB6/IR IRQ4 PB5/IR PB4/ SUPERVISOR ONLY MOTOROLA 1 0 IX1 IRQ1 ...

Page 97

... The port direction register bits determine the direction of data flow at the port pins. PADIR7–0—Port A Direction Register Bit 7–0 This bit determines the direction of data flow at port A pins 7 through Input Output. PBDIR7–0—Port B Direction Register Bit 7–0 MOTOROLA ...

Page 98

... The other chip selects are not affected by any reset, and must be explicitly programmed. This applies to all chip selects, whether used or not. 5 PAD2 PAD1 PAD0 PBD7 PBD6 MC68306 USER'S MANUAL PBD5 PBD4 PBD3 PBD2 PBD1 SUPERVISOR ONLY MOTOROLA 0 PBD0 U ...

Page 99

... CSA31 CSA3 CSA2 CSA2 CSA2 RESE CSA31–CSA17—Chip Select Address This bit field selects the base address for each chip select. MOTOROLA NOTE CSA2 CSA2 CSA2 CSA2 CSA22 ...

Page 100

... CSFC CSFC — CSM3 CSM2 MC68306 USER'S MANUAL CSM1 CSM0 CSDT3 CSDT2 CSDT SUPERVISOR ONLY CSM1 CSM0 CSDT3 CSDT2 CSDT SUPERVISOR ONLY MOTOROLA 0 CSDT CSDT 0 U ...

Page 101

... Automatic DTACK, 2 wait states 0011 = Automatic DTACK, 3 wait states 0100 = Automatic DTACK, 4 wait states 0101 = Automatic DTACK, 5 wait states 0110 = Automatic DTACK, 6 wait states 0111 = Automatic DTACK, 7 wait states MOTOROLA Table 5-2. Chip Select Match Bits A27 A26 A25 A24 A23 ...

Page 102

... SPACE EACH A17 A18 A19 Figure 5-1. Chip Select Expansion MC68306 USER'S MANUAL 32 KBYTE ADDRESS SPACE EACH 74F138 EXCS0 ($080XXX EXCS1 ($088XXX EXCS2 ($090XXX EXCS3 ($098XXX EXCS4 ($0A0XXX EXCS5 ($0A8XXX EXCS6 ($0B0XXX) Q6 EXCS7 ($0B8XXX MOTOROLA ...

Page 103

... RAS address width of the DRAMs. If this is done, the DRAMA, CAS, and DRAMW signals should be buffered. This will almost certainly require the wait state. Also, DRAMs with more row address pins than column address pins are supported. MOTOROLA 2 bytes), because of the address At RAS When DRSZ2–0 Is: ...

Page 104

... RR3 RR2 SUPERVISOR ONLY EXTAL DRA2 DRA2 DRA2 DRA2 DRA2 NOTE MC68306 USER'S MANUAL 9 8 RR1 RR0 DRA21 DRA20 DRA19 DRA18 DRA1 SUPERVISOR ONLY MOTOROLA 0 DRW U ...

Page 105

... A31–A30 must match DRA31–DRA30; A29–A17 ignored in DRAM bank address match ..... 1111 = A31–A17 must match DRA31–DRA17 in DRAM bank address match Table 5-4 shows the entire range of address bits that must match for a DRAM bank to occur. MOTOROLA ...

Page 106

... MOTOROLA A17 • ...

Page 107

... The following equation can be used to calculate the size of external capacitance: Where the parasitic capacitance, which can be neglected in most cases the total input capacitance, consisting the total output capacitance, consisting of C2 and external parasitic OUT capacitances (e.g., board and package capacitances). MOTOROLA Generation OUT ...

Page 108

... EXTAL, X1 Figure 5-2. Oscillator Circuit Diagram 5- EXT MC68306 MC68306 USER'S MANUAL XTAL MOTOROLA ...

Page 109

... Two Independent Serial Communication Channels (A and B) • Baud Rate Generator Logic • Sixteen Bit Timer/Counter • Internal Channel Control Logic • Interrupt Control Logic Figure 6-1. Simplified Block Diagram MOTOROLA IP0 IP1 IP2 OP0 OP1 OP3 ...

Page 110

... Eight Maskable Interrupt Conditions • Timer/Counter Interrupt Can Be Independently Programmed • Parity, Framing, and Overrun Error Detection • False-Start Bit Detection • Line-Break Detection and Generation • Detection of Breaks Originating in the Middle of a Character • Start/End Break Interrupt/Status 6-2 MC68306 USER'S MANUAL MOTOROLA ...

Page 111

... The interrupt level of the serial module IRQ is programmed in the system register external to the serial module. When an interrupt at this level is acknowledged, the serial module is serviced before the external IRQ7 of the same level. MOTOROLA MC68306 USER'S MANUAL 6-3 ...

Page 112

... This signal is the transmitter serial data output for channel A. The output is held high ('mark' condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on this signal on the falling edge of the clock source, with the least significant bit transmitted first. 6-4 NOTE MC68306 USER'S MANUAL CC MOTOROLA ...

Page 113

... This signal is the transmitter serial data output for channel B. The output is held high ('mark' condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on this signal at the falling edge of the clock source, with the least significant bit transmitted first. MOTOROLA INTERNAL CONTROL LOGIC ...

Page 114

... It can generate an interrupt on change-of-state. CTSB 6.2.10.1 . When used for this function, this signal is the channel B clear-to-send input. 6.2.10.2 IP1. When used for this function, this signal is a general-purpose input. 6-6 RTSA/OP0 ) RTSB/OP1 ) CTSA /IP0) CTSB/ IP1) MC68306 USER'S MANUAL MOTOROLA ...

Page 115

... The functional block diagram of the transmitter and receiver, including command and operating registers, is shown in Figure 6-4. The paragraphs that follow contain descriptions for both these functions in reference to this diagram. For detailed register information, refer to 6.4 Register Description and Programming. MOTOROLA BAUD RATE GENERATOR LOGIC CRYSTAL ...

Page 116

... MODE REGISTER 1 (MR1B) MODE REGISTER 2 (MR2B) STATUS REGISTER (SRB) TRANSMIT HOLDING REGISTER TRANSMIT SHIFT REGISTER RECEIVER HOLDING REGISTER 1 RECEIVER HOLDING REGISTER 2 RECEIVER HOLDING REGISTER 3 RECEIVER SHIFT REGISTER MC68306 USER'S MANUAL EXTERNAL INTERFACE W R/W R TxDA FIFO R RxDA W R/W R TxDB FIFO R RxDB MOTOROLA ...

Page 117

... TxDx output remains high ('mark' condition), and the transmitter empty bit (TxEMP) in the DUSR is set. Transmission resumes and the TxEMP bit is cleared when the CPU loads a new character into the transmitter buffer (DUTB disable command is sent to the transmitter, it continues operating until the character in the MOTOROLA ...

Page 118

... RB and RxRDY bits in the DUSR are set. The RxDx signal must return to a high condition for at least one-half bit time before a search for the next start bit begins. 6-10 MC68306 USER'S MANUAL clock for MOTOROLA ...

Page 119

... FIFO STACK. The FIFO stack is used in each channel's receiver buffer logic. The stack consists of three receiver holding registers. The receive buffer consists of the FIFO and a receiver shift register connected to the RxDx (refer to Figure 6-4). Data is assembled in the receiver shift register and loaded into the top empty receiver holding MOTOROLA ...

Page 120

... If the FIFO stack contains characters and the receiver is disabled, the characters in the FIFO can still be read by the CPU. If the receiver is reset, the FIFO stack and all receiver status bits, corresponding output ports, and interrupt request are reset. No additional characters are received until the receiver is re-enabled. 6-12 MC68306 USER'S MANUAL MOTOROLA ...

Page 121

... Since the receiver is not active, received data cannot be read by the CPU, and the error status conditions are inactive. Received parity is not checked and is not recalculated for transmission. Stop bits are transmitted as received. A received break is echoed as received until the next valid start bit is detected. MOTOROLA MC68306 USER'S MANUAL 6-13 ...

Page 122

... CPU disables the receiver and initiates the process again. 6-14 Rx DISABLED DISABLED Tx (a) Automatic Echo Rx Tx (b) Local Loopback DISABLED DISABLED Rx DISABLED DISABLED Tx (c) Remote Loopback MC68306 USER'S MANUAL RxDx INPUT TxDx OUTPUT DISABLED RxDx INPUT DISABLED TxDx OUTPUT RxDx INPUT TxDx OUTPUT MOTOROLA ...

Page 123

... RxRDY bit and loads the character into the receiver holding register FIFO stack provided the received A/D bit is a one (address tag). The character is discarded if the received A/D bit is a zero (data tag). If the receiver is enabled, all received characters are transferred to the CPU via the receiver holding register stack during read operations. MOTOROLA A/D A/D ADDR ...

Page 124

... X1/CLK or an external input on input port pin IP2, divided by one or sixteen. The square wave generated by the timer has a period of twice the preload value times the period of the clock source, is available as a clock source for both communications channels, and 6-16 MC68306 USER'S MANUAL MOTOROLA ...

Page 125

... This section contains a detailed description of each register and its specific function as well as flowcharts of basic serial module programming. 6.4.1 Register Description The operation of the serial module is controlled by writing control bytes into the appropriate registers. A list of serial module registers and their associated addresses is MOTOROLA MC68306 USER'S MANUAL 6-17 ...

Page 126

... COUNTER/TIMER UPPER REGISTER COUNTER/TIMER LOWER REGISTER MODE REGISTER B (DUMR1B, DUMR2B) CLOCK-SELECT REGISTER B (DUCSRB) COMMAND REGISTER B (DUCRB) TRANSMITTER BUFFER B (DUTBB) INTERRUPT VECTOR REGISTER (DUIVR) OUTPUT PORT CONFIGURATION REGISTER OUTPUT PORT (DUOP) 2 BIT SET OUTPUT PORT (DUOP) 2 BIT RESET MC68306 USER'S MANUAL (DUOPCR) MOTOROLA ...

Page 127

... PM1–PM0—Parity Mode These bits encode the type of parity used for the channel (see Table 6-1). The parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. These bits can alternatively select multidrop mode for the channel. MOTOROLA ...

Page 128

... Six Bits 1 0 Seven Bits 1 1 Eight Bits CM0 TxRTS TxCTS SB3 SB2 MC68306 USER'S MANUAL Parity Type Even Parity Odd Parity Low Parity High Parity No Parity Data Character Address Character 1 0 SB1 SB0 0 0 MOTOROLA ...

Page 129

... If an external 1 clock is used for the transmitter, DUMR2 bit selects one stop bit, and DUMR2 bit selects two stop bits for transmission. MOTOROLA Table 6-3. CMx Control Bits CM1 CM0 ...

Page 130

... TxEMP TxRDY MC68306 USER'S MANUAL Length 5 Bits 1.063 1.125 1.188 1.250 1.313 1.375 1.438 1.500 1.563 1.625 1.688 1.750 1.813 1.875 1.938 2.000 1 0 FFULL RxRDY 0 0 MOTOROLA ...

Page 131

... The transmitter holding register was loaded by the CPU, or the transmitter is disabled. FFULL—FIFO Full character has been received in channel B and is waiting in the receiver buffer FIFO The FIFO is not full, but may contain up to two unread characters. MOTOROLA MC68306 USER'S MANUAL 6-23 ...

Page 132

... Set 1 is selected if DUACR bit and set 2 is selected if DUACR bit The receiver clock is always 16 times the baud rate shown in this list, except when the clock select bits = 1111. 6- RCS2 RCS1 RCS0 TCS3 TCS2 MC68306 USER'S MANUAL 1 0 TCS1 TCS0 0 0 MOTOROLA ...

Page 133

... Table 6-6 The baud rate set selected depends upon DUACR bit 7. Set 1 is selected if DUACR bit and set 2 is selected if DUACR bit The transmitter clock is always 16 times the baud rate shown in this list, except when the clock select bits = 1111. MOTOROLA Table 6-5. RCSx Control Bits RCS2 RCS1 ...

Page 134

... TIMER – – MISC2 MISC1 MISC0 TC1 TC0 MC68306 USER'S MANUAL Set 2 75 110 134.5 150 300 600 1200 2000 2400 4800 1800 9600 19.2k TIMER – – RC1 RC0 0 0 MOTOROLA ...

Page 135

... Stop Break—The stop break command causes the channel's TxDx to go high (mark) within two bit times. Characters stored in the transmitter buffer, if any, are transmitted. TC1–TC0—Transmitter Commands These bits select a single command as listed in Table 6-8. MOTOROLA Table 6-7. MISCx Control Bits MISC1 MISC0 ...

Page 136

... Table 6-8. TCx Control Bits TC1 TC0 Command Action Taken 0 1 Enable Transmitter 1 0 Disable Transmitter Not Use Table 6-9. RCx Control Bits RC1 RC0 Command Action Taken 0 1 Enable Receiver 1 0 Disable Receiver Not Use MC68306 USER'S MANUAL MOTOROLA ...

Page 137

... TB7–TB0—These bits contain the character in the transmitter buffer. 6.4.1.8 INPUT PORT CHANGE REGISTER (DUIPCR). The DUIPCR shows the current state and the change-of-state for the IP0, IP1, and IP2 pins. DUIPCR 7 0 RESET: 0 Read Only MOTOROLA RB6 RB5 RB4 ...

Page 138

... Register (DUCSR) for more information on the baud rates. CTMS2–0— Counter/Timer Mode and Source Select Table 6-10 lists the counter/timer mode and source select bit fields. 6- CTMS2 CTMS1 CTMS0 – IEC2 MC68306 USER'S MANUAL 1 0 IEC1 IEC0 0 0 MOTOROLA ...

Page 139

... Read Only COS—Change-of-State change-of-state has occurred at one of the IPx inputs and has been selected to cause an interrupt by programming bit 2, 1 and/or bit 0 of the DUACR selected COSx in the DUIPCR. MOTOROLA MISC0 Mode Command Clock Source Select Command 0 ...

Page 140

... IRQ output. The DUIMR does not mask the reading of the DUISR. DUIMR 7 COS RESET: 0 Write Only COS—Change-of-State 1 = Enable interrupt 0 = Disable interrupt 6- DBB FFULLB TxRDYB CTR/TM DBA R _RDY MC68306 USER'S MANUAL 1 0 FFULLA TxRDYA 0 0 MOTOROLA ...

Page 141

... The minimum value that can be loaded on the concatenation of DUCTUR with DUCTLR is 0002 (hex). This register is write only and cannot be read by the CPU. MOTOROLA MC68306 USER'S MANUAL 6-33 ...

Page 142

... DUOP for general-purpose use or for auxiliary functions serving the communication channels. 6- IVR6 IVR5 IVR4 IVR3 IVR2 IP5 IP4 IP3 IP2 IP2 NOTE MC68306 USER'S MANUAL 1 0 IVR1 IVR0 IP1 IP0 IP1 IP0 MOTOROLA ...

Page 143

... OPCR3–OPCR2—Output Port 3 Function Select 00 = OPR bit Counter/timer output 10 = TxCB (1X RxCB (1X) OP3 is open-drain in this mode, and an external pullup is required. OPCR1–OPCR0—Output Port 2 Function Select 00 = OPR bit TxCA (16X TxCA (1X RxCA (1X) MOTOROLA OP6 OP5 OP4 OP3 T≈RDYA R≈RDYB R≈ ...

Page 144

... DUISR CTR/TMR_RDY bit in counter or timer mode. The read data has no meaning. 6-36 Bit Set OP6 OP5 OP4 OP3 OP2 NOTE Bit Reset OP6 OP5 OP4 OP3 OP2 MC68306 USER'S MANUAL 1 0 OP1 OP0 OP1 OP0 0 0 MOTOROLA ...

Page 145

... A change- in-break (beginning of a break). SIRQ then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor. MOTOROLA MC68306 USER'S MANUAL 6-37 ...

Page 146

... STATUS CHK2 POINT TO CHANNEL B CALL CHCHK SAVE CHANNEL B STATUS Figure 6-10. Serial Module Programming Flowchart ( 6-38 ENABLA ANY ERRORS IN CHANNEL A ? ENABLE CHANNEL A'S RECEIVER ASSERT CHANNEL A REQUEST TO SEND ENABLB ANY ERRORS IN CHANNEL B ? ENABLE CHANNEL B'S TRANSMITTER SINITR RETURN MC68306 USER'S MANUAL MOTOROLA ...

Page 147

... STATUS WORD TxCHK IS TRANSMITTER READY ? Y SNDCHR SEND CHARACTER TO TRANSMITTER RxCHK HAS RECEIVER RECEIVED CHARACTER ? Y A Figure 6-10. Serial Module Programming Flowchart ( MOTOROLA N N WAITED Y TOO LONG ? WAITED TOO LONG ? MC68306 USER'S MANUAL SET TRANSMITTER- NEVER-READY FLAG SET RECEIVER- NEVER-READY FLAG B ...

Page 148

... ERROR FLAG PRCHK HAVE PARITY ERROR ? Y SET PARITY ERROR FLAG A CHRCHK GET CHARACTER FROM RECEIVER SAME AS CHARACTER TRANSMITTED ? N SET INCORRECT CHARACTER FLAG B Figure 6-10. Serial Module Programming Flowchart ( 6-40 RSTCHN DISABLE CHANNEL'S N RESTORE CHANNEL TO ORIGINAL MODE N Y MC68306 USER'S MANUAL B TRANSMITTER RETURN MOTOROLA ...

Page 149

... BREAK STATUS BIT REMOVE BREAK CHARACTER FROM RECEIVER FIFO REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS SIRQR RTE Figure 6-10. Serial Module Programming Flowchart ( MOTOROLA DOES N CHANNEL A RECEIVER HAVE A CHARACTER SAVE IN SYSTEM BUFFER RETURN N MC68306 USER'S MANUAL INCH ...

Page 150

... Figure 6-10. Serial Module Programming Flowchart ( 6-42 OUTCH IS CHANNEL N TRANSMITTER READY ? Y SEND CHARACTER TO CHANNEL TRANSMITTER RETURN MC68306 USER'S MANUAL MOTOROLA ...

Page 151

... Select character or block error mode (ERR bit). • Select parity mode and type (PM and PT bits). • Select number of bits per character (B/Cx bits). Mode Register 2 (DUMR2) • Select the mode of channel operation (CMx bits). • If desired, program operation of transmitter ready-to-send (TxRTS bit). MOTOROLA NOTE MC68306 USER'S MANUAL 6-43 ...

Page 152

... If desired, program operation of clear-to-send (TxCTS bit). • Select stop-bit length (SBx bits). Command Register (DUCR) • Enable the receiver and transmitter. 6-44 MC68306 USER'S MANUAL MOTOROLA ...

Page 153

... This description is not intended to be used without the supporting IEEE 1149.1 document. The discussion includes those items required by the standard and provides additional information specific to the MC68306 implementation. For internal details and applications of the standard, refer to the IEEE 1149.1 document. MOTOROLA NOTE NOTE MC68306 USER'S MANUAL 7-1 ...

Page 154

... TDO changes on the falling edge of TCK. TEST DATA REGISTERS 123 TDI BYPASS TRST TMS TAP CTLR TCK Figure 7-1. Test Access Port Block Diagram 7-2 2 MODE 31 ID BOUNDARY SCAN REGISTER (124 BITS) DECODER 2 3-BIT INSTRUCTION REGISTER MC68306 USER'S MANUAL 2040101D MOTOROLA TDO ...

Page 155

... RESET 0 RUN-TEST/IDLE 0 Figure 7-2. TAP Controller State Machine 7.3 BOUNDARY SCAN REGISTER The MC68306 IEEE 1149.1 implementation has a 124-bit boundary scan register. This register contains bits for all device signal and clock pins and associated control signals. MOTOROLA 1 1 SELECT-DR_SCAN 0 1 CAPTURE- SHIFT-DR ...

Page 156

... IO control bit to determine pin direction. 7-4 Name Bit Number 8 26 PPOE15 12 28 PPOE0 14 30 PPOE1 16 32 PPOE2 18 34 PPOE3 20 36 PPOE4 22 38 PPOE5 24 40 PPOE6 MC68306 USER'S MANUAL Name Bit Number 42 PPOE7 DOE 58 HiZ 67 86 DRAMWOE 88 DRAMOE CPMOE 97 100 CSOE 118 AOE MOTOROLA ...

Page 157

... En.Cell PPOE14 25 IO.Cell PA6 26 En.Cell PPOE15 27 IO.Cell PA7 28 En.Cell PPOE0 29 IO.Cell PB0/IACK2 30 En.Cell PPOE1 31 IO.Cell PB1/IACK3 32 En.Cell PPOE2 33 IO.Cell PB2/IACK5 MOTOROLA Bit Control Num Cell Type HiZ 34 En.Cell HiZ 35 IO.Cell 36 En.Cell 37 IO.Cell HiZ 38 En.Cell 39 IO.Cell HiZ 40 En.Cell 41 IO.Cell 42 En.Cell 43 IO.Cell OPOE3 44 O ...

Page 158

... A1/DRAMA0 CPMOE A2/DRAMA1 CPMOE A3/DRAMA2 CPMOE A4/DRAMA3 CPMOE A5/DRAMA4 CPMOE A6/DRAMA5 CPMOE A7/DRAMA6 CPMOE A8/DRAMA7 CPMOE A9/DRAMA8 CPMOE A10/DRAMA9 CPMOE A11/DRAMA10 CPMOE A12/DRAMA11 CPMOE A13/DRAMA12 CPMOE A14/DRAMA13 CPMOE A15/DRAMA14 CPMOE AOE A16 AOE A17 AOE A18 AOE A19 AOE AMODE MOTOROLA ...

Page 159

... EXTEST 0 – OTHERWISE G1 DATA FROM SYSTEM 1 LOGIC MUX 1 TO DEVICE LOGIC TO NEXT CELL MOTOROLA SHIFT MUX 1 C1 FROM CLOCK DR LAST CELL Figure 7-3. Output Cell (O.Cell MUX CLOCK DR FROM LAST Figure 7-4. Input Cell (I.Cell) MC68306 USER'S MANUAL ...

Page 160

... FROM PIN Figure 7-6. Bidirectional Cell (IO.Cell) 7 MUX 1 C1 CLOCK DR FROM LAST CELL SHIFT MUX 1 FROM LAST CLOCK DR INPUT TO CELL SYSTEM LOGIC MC68306 USER'S MANUAL TO NEXT CELL TO OUTPUT ENABLE 1D C1 UPDATE DR TO NEXT CELL TO OUTPUT DRIVER UPDATE DR MOTOROLA ...

Page 161

... Figure 7-8. General Arrangement for Bidirectional Pins 7.4 INSTRUCTION REGISTER The MC68306 IEEE 1149.1 implementation includes the three mandatory public instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS), the optional public ID instruction, plus one additional public instruction (CLAMP) defined by IEEE 1149.1. The MOTOROLA SHIFT MUX ...

Page 162

... The snapshot occurs on the rising edge of TCK in the capture- DR controller state. The data can be observed by shifting it transparently through the boundary scan register. 7-10 Table 7-3. Instructions Code Instruction EXTEST BYPASS CLAMP MODULE MODE BYPASS SAMPLE/PRELOAD BYPASS MC68306 USER'S MANUAL MOTOROLA ...

Page 163

... The control afforded by the output enable signals using the boundary scan register and the EXTEST instruction requires a compatible circuit-board test environment to avoid device-destructive configurations. The user must avoid situations in which the MC68306 output drivers are enabled into actively driven networks. Overdriving the TDO driver when it is active is not recommended. MOTOROLA NOTE ...

Page 164

... A minimum of five consecutive TCK rising edges withh TMS high. TMS has an internal pullup, and may be left unconnected. If TMS either remains unconnected or is connected then the TAP controller cannot leave the test-logic-reset state, regardless of the state of TCK or TRST. 7-12 MC68306 USER'S MANUAL MOTOROLA ...

Page 165

... However, sections of the device may not operate normally while being exposed to the electrical extremes. 8.2 THERMAL CHARACTERISTICS Characteristic Thermal Resistance—Junction to Case Plastic 132-Pin QFP Plastic 144-Pin Thin QFP Thermal Resistance—Junction to Ambient Plastic 132-Pin QFP Plastic 144-Pin Thin QFP * Estimated MOTOROLA Symbol Value Unit V CC –0 7 –0 7 ...

Page 166

... The measurement of the AC specifications is defined by the waveforms shown in Figure 8-1. To test the parameters guaranteed by Motorola, inputs must be driven to the voltage levels specified in that figure. Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown in Figure 8-1. Inputs are specified with minimum setup and hold times and are measured as shown ...

Page 167

... B. Minimum output hold time. C. Minimum input setup time specification. D. Minimum input hold time specification. E. Signal valid to signal valid specification (maximum or minimum). F. Signal valid to signal invalid specification (maximum or minimum). Figure 8-1. Drive Levels and Test Points for AC Specifications MOTOROLA 0 2.0 V VALID OUTPUT ...

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... A I TSI — –0.75 — — 0 — 100 — 0 — 10 — — 100 pF Min Max Unit 8.0 16.7 MHz 60 125 ns — TBD 62.5 ns — — – – MOTOROLA ...

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... LDS, UDS, Width Asserted (Write AS, LDS, UDS Width Negated 16 CLKOUT High to Control Bus High Impedance 2 17 AS, LDS, UDS Negated to R/W Invalid 1 18 CLKOUT High to R/W High (Read CLKOUT High to R/W Low (Write) MOTOROLA 1.5 V 1.5 V Figure 8-2. Clock Output Timing MC68306 USER'S MANUAL 3 3.8 V 1 ...

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... CS0–7 as the enable for the external decode. 8-6 16.67 MHz Min — — — 0 — — MC68306 USER'S MANUAL Max Unit 10 ns — ns — ns — — ns — ns — ns 110 ns — — 150 ns — ns — ns — ns — ns — Clks MOTOROLA ...

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... Setup time (#47) for asynchronous inputs (HALT, RESET, BR, BGACK, DTACK, BERR, IRQx) guarantees their recognition at the next falling edge of the clock need fall at this time only to ensure being recognized at the end of the bus cycle. Figure 8-3. Read Cycle Timing Diagram MOTOROLA ...

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... BR need fall at this time only to ensure being recognized at the end of the bus cycle. Figure 8-4. Write Cycle Timing Diagram 8 11A 20A 14A 15A MC68306 USER'S MANUAL S7 12 12A MOTOROLA ...

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... AS (NOTE 1) LDS / UDS 61 61A R/W CS IACKx DATA OE UW, LW NOTE: THE WRITE CYCLE ILLUSTRATED IS PART OF A TEST AND SET INSTRUCTION. Figure 8-5. Chip Select and Interrupt Acknowledge Timing Diagram MOTOROLA (The electrical specifications in this document are preliminary.) Characteristic S12 S13 ...

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... Figure 8-6. Bus Arbitration Timing Diagram 8-10 Characteristic MC68306 USER'S MANUAL (The electrical 16.67 MHz Min Max Unit — — — — 1.5 6.5 Clks 1.5 3.5 Clks 1.5 3.5 Clks 20 ns 1.5 Clks — 1.5 — Clks 10 — — Clks 1 — Clks MOTOROLA ...

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... Figure 8-7. Bus Arbitration Timing Diagram MOTOROLA MC68306 USER'S MANUAL 8- 11 ...

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... MOTOROLA ...

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... CLKOUT FC0–FC2 A15/DRAMA 14– A1/DRAMA 0 AS UDS, LDS R/W UW DTACK D15–D0 DRAMW RAS CAS Figure 8-8. DRAM Timing – 0-Wait Read, No Refresh MOTOROLA 71A MC68306 USER'S MANUAL 87 89 89A ...

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... STATE CLKOUT 102 DRAMW 99 RAS 80 95 CAS 90 98 Figure 8-10. DRAM Timing – 0- and 1-Wait Refresh 8- 71A 102 103 100 99 101 96 97 MC68306 USER'S MANUAL 87 89 89A 0-WAIT STATE 96 100 101 80 103 MOTOROLA ...

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... To use the standard baud rates selected by the clock-select register given in Tables 6-5 and 6-6, the X1/CLK frequency should be set to 3.6864 MHz or a 3.6864 MHz crystal should be connected across pins X1/CLK and X2. 3. IP5–2 for RxC, TxC are not supported in the MC68306. MOTOROLA ...

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... Figure 8-12. Clock Timing OLD DATA Figure 8-13. Port Timing MC68306 USER'S MANUAL Symbol Min Max t CTC 25 — — — CLK t CTC Symbol Min Max — — — NEW DATA MOTOROLA Unit Unit ...

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... CTS is an asynchronous input. This specification is only provided to guarantee CTS recognition on a particular Tx clock edge. Tx CLOCK SOURCE (X1 OR IP2) TxD OP0, OP1 WHEN USED AS TxRTS IP0, IP1 WHEN USED AS CTS MOTOROLA 1 BIT TIME t TxD Figure 8-15. Transmit Timing MC68306 USER'S MANUAL Symbol Min Max ...

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... RTS Output Valid from Rx Clock Rx CLOCK SOURCE (X1 OR IP2) RxD OP0, OP1 * * When used as RxRTS 8-18 t RxS Figure 8-16. Receive Timing MC68306 USER'S MANUAL Symbol Min Max Unit t RxS 240 — RxH 200 — RRD — 100 ns t RxH t RRD MOTOROLA ...

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... TMS, TDI Data Setup Time 11 TMS, TDI Data Hold Time 12 TCK Low to TDO Data Valid 13 TCK Low to TDO High Impedance 14 TRST Width Low V IH TCK Figure 8-17. Test Clock Input Timing Diagram MOTOROLA Min Max Unit 0 10.0 MHz 100 — — — ...

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... TCLK TDI TMS TDO TDO TDO Figure 8-19. Test Access Port Timing Diagram 8- INPUT DATA VALID 8 OUTPUT DATA VALID MC68306 USER'S MANUAL OUTPUT DATA VALID INPUT DATA VALID OUTPUT DATA VALID OUTPUT DATA VALID MOTOROLA ...

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... This section contains the ordering information, pin assignments, and package dimensions for the MC68306. 9.1 STANDARD ORDERING INFORMATION Package Type 132-Lead Plastic Quad Flat Pack (FC Suffix) 144-Lead Thin Quad Flat Pack (PV Suffix) MOTOROLA Frequency (MHz) Temperature 8–16 8–16 MC68306 USER'S MANUAL Order Number MC68306FC16 MC68306PV16 9- 1 ...

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... TOP VIEW 67 MC68306 USER'S MANUAL 117 116 N/C OP1/RTSB OP0/RTSA IP1/CTSB GND IP0/CTSA TXDB RXDB TXDA RXDA VDD OP3 IP2 X2 X1 PA0 100 GND PA1 PA2 PA3 PA4 PA5 VDD PA6 PA7 PB0/IACK2 PB1/IACK3 PB2/IACK5 GND PB3/IACK6 PB4/IRQ2 PB5/IRQ3 PB6/IRQ5 84 83 MOTOROLA ...

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... DRAMW GND LDS UDS R/W AS BGACK VCC BG BR EXTAL XTAL CLKOUT GND HALT RESET FC2 N/C N MOTOROLA MC68306 144-PIN TQFP (TOP VIEW) MC68306 USER'S MANUAL 109 108 N/C N/C OP1/RTSB OP0/RTSA IP1/CTSB GND IP0/CTSA TXDB RXDB TXDA RXDA VCC OP3 IP2 X2 X1 PA0 ...

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... DIMENSIONS S AND DETERMINED AT SEATING PLANE, DATUM -T DIMENSIONS AND DETERMINED AT DATUM PLANE -W- . 1.097 1.103 1.097 1.103 1.075 1.085 1.075 1.085 MC68306 USER'S MANUAL PIN 1 INDENT SECTION P-P -W- . MOTOROLA ...

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... Thin Quad Flat Pack (PV Suffix) MOTOROLA MC68306 USER'S MANUAL 9- 5 ...

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... Data Formats, 4-3 Data Types Access Errors, 4-1 M-bit, 4-14 Denormalized Numbers, 4-3 Infinities, 4-3 NANs, 4-3 Normalized Numbers, 4-3 Zeros, 4-3 Double Bus Fault, 3-29 DRAM Configuration Register, 5-14 Refresh Register, 5-13 DTACK, 3-4, 3-7, 3-10, 3-33, 3-37 DUACR, 6-30 MOTOROLA DUCR, 6-26 DUCSR, 6-24 DUCUR, 6-33 DUIMR, 6-33 DUIP, 6-34 DUIPCR, 6-29 DUISR, 6-31 DUIVR, 6-34 DUMR1, 6-18 DUMR2, 6-20 DUOP, 6-35 DUOPCR, 6-35 DURBA, 6-29 DURBB, 6-29 ...

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... Three-Wire Bus Arbitration, 3-12 Timer Mode, 6-16 Timer Vector Register, 5-4 Index-2 Timer/Counter, 6-3 Trace Exception, 4-19 Two-Wire Bus Arbitration, 3-12 UDS, 3-7 UDS/LDS, 3-4, 3-10 Uninitialized Interrupt Vector, 4-18 Valid Start Bit, 6-10 Vector Number, 4-12 Word Read Cycle Flowchart, 3-2 Write Cycle, 3-4 MC68306 USER’S MANUAL — U — — V — — W — MOTOROLA ...