UPD78P0208GF-3BA NEC, UPD78P0208GF-3BA Datasheet
UPD78P0208GF-3BA
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User’s Manual µ PD780208 Subseries 8-Bit Single-Chip Microcontrollers µ PD780204 µ PD780204A µ PD780205 µ PD780205A µ PD780206 µ PD780208 µ PD78P0208 Document No. U11302EJ4V0UM00 (4th edition) Date Published July 2003 N CP(K) c Printed in Japan ...
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User’s Manual U11302EJ4V0UM ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • ...
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Page Throughout Addition of the following products to target products • µ PD780204A • µ PD780205A Deletion of the following package from target products • µ PD78P0208KL-T (100-pin ceramic WQFN) CHAPTER 1 OUTLINE p.29 • Update of 1.6 78K/0 Series ...
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Readers This manual has been prepared for user engineers who wish to understand the functions of the µ PD780208 Subseries and design and develop its application systems and programs. Purpose This manual is intended to give users an understanding of ...
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices µ PD780204, 780205, 780206, 780208 Data Sheet µ PD78P0208 Data Sheet µ PD780208 Subseries User’s ...
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... NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing ...
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... XT1 and XT2 ........................................................................................................................... 2.2.19 V ........................................................................................................................................... DD 2.2.20 V ............................................................................................................................................ SS ( µ PD78P0208 only) .......................................................................................................... 2.2. 2.2.22 IC (mask ROM version only) .................................................................................................. 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ............................... 43 CHAPTER 3 CPU ARCHITECTURE .................................................................................................... 48 3.1 Memory Space ..................................................................................................................... 48 3.1.1 Internal program memory space ............................................................................................ 3.1.2 Internal data memory space ................................................................................................... 3.1.3 Special-function register (SFR) area ...................................................................................... 10 CONTENTS User’s Manual U11302EJ4V0UM ...
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Data memory addressing ........................................................................................................ 3.2 Processor Registers ........................................................................................................... 60 3.2.1 Control registers ...................................................................................................................... 3.2.2 General-purpose registers ...................................................................................................... 3.2.3 Special-function registers (SFRs) ........................................................................................... 3.3 Instruction Address Addressing ...................................................................................... 68 3.3.1 Relative addressing ................................................................................................................. 3.3.2 Immediate addressing ............................................................................................................. 3.3.3 Table indirect ...
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Divider ...................................................................................................................................... 113 5.4.4 When subsystem clock is not used ........................................................................................ 113 5.5 Clock Generator Operations ............................................................................................. 114 5.5.1 Main system clock operations ................................................................................................ 115 5.5.2 Subsystem clock operations ................................................................................................... 116 5.6 Changing System Clock and CPU Clock Settings ...
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CHAPTER 10 CLOCK OUTPUT CONTROLLER ................................................................................. 182 10.1 Clock Output Controller Functions .................................................................................. 182 10.2 Clock Output Controller Configuration ........................................................................... 183 10.3 Clock Output Function Control Registers ...................................................................... 183 CHAPTER 11 BUZZER OUTPUT CONTROLLER .............................................................................. 186 11.1 Buzzer Output Controller ...
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Key Scan Flag and Key Scan Data .................................................................................. 314 15.7.1 Key scan flag ........................................................................................................................... 314 15.7.2 Key scan data .......................................................................................................................... 314 15.8 Light Leakage of VFD ......................................................................................................... 315 15.9 Display Examples ............................................................................................................... 317 15.9.1 Segment type (display mode 1: ...
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CHAPTER 20 INSTRUCTION SET ....................................................................................................... 383 20.1 Conventions ........................................................................................................................ 384 20.1.1 Operand identifiers and description methods ........................................................................ 384 20.1.2 Description of “operation” column .......................................................................................... 385 20.1.3 Description of “flag operation” column ................................................................................... 385 20.2 Operation List ...................................................................................................................... 386 20.3 Instructions ...
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... Format of Display Mode Register 0 ............................................................................................... 105 5-5 Format of Display Mode Register 1 ............................................................................................... 108 5-6 External Circuit of Main System Clock Oscillator .......................................................................... 109 5-7 External Circuit of Subsystem Clock Oscillator ............................................................................. 110 5-8 Examples of Incorrect Resonator Connection ............................................................................... 111 5-9 Main System Clock Stop Function ................................................................................................. 115 5-10 System Clock and CPU Clock Switching ....................................................................................... 118 16 LIST OF FIGURES (1/6) Title User’ ...
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Figure No. 6-1 Block Diagram of 16-Bit Timer/Event Counter (Timer Mode) ....................................................... 123 6-2 Block Diagram of 16-Bit Timer/Event Counter (PWM Mode) ........................................................ 124 6-3 Block Diagram of 16-Bit Timer/Event Counter Output Controller ................................................. 125 6-4 Format of Timer Clock ...
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... Example of Method of Reducing Power Consumption in Standby Mode .................................... 202 12-9 Analog Input Pin Processing .......................................................................................................... 203 12-10 A/D Conversion End Interrupt Request Generation Timing .......................................................... 204 12-11 AV Pin Connection ....................................................................................................................... 204 DD 13-1 Block Diagram of Serial Interface Channel 0 ................................................................................ 208 13-2 Format of Timer Clock Select Register 3 ....................................................................................... 212 13-3 Format of Serial Operating Mode Register 0 ................................................................................. 213 13-4 Format of Serial Bus Interface Control Register ...
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Figure No. 13-16 Data .................................................................................................................................................. 229 13-17 Acknowledge Signal ........................................................................................................................ 230 13-18 BUSY and READY Signals ............................................................................................................. 231 13-19 RELT, CMDT, RELD, and CMDD Operations (Master) ................................................................ 236 13-20 RELD and CMDD Operations (Slave) ............................................................................................ 236 13-21 ACKT Operation .............................................................................................................................. ...
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... Relationship Between Display Data Memory Contents and Segment Outputs in 35-Segment x 16-Digit Display Mode ........................................................................................ 321 15-18 Display Data Memory Configuration and Data Reading Order (Display Mode 2) ....................... 322 15-19 Segment Connection Example ....................................................................................................... 323 15-20 Grid Driving Timing ......................................................................................................................... 324 15-21 Data Memory Status in 23-Segment x 5-Grid Display Mode ........................................................ 325 ...
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... EV-9200GF-100 Package Drawing (for Reference Purposes only) ............................................. 409 B-3 Recommended Footprint for EV-9200GF-100 (for Reference Purposes only) ............................ 410 B-4 Distance Between IE System and Conversion Adapter ................................................................ 411 B-5 Connection Conditions of Target System (When NP-100GF-TQ Is Used) .................................. 412 B-6 Connection Conditions of Target System (When NP-H100GF-TQ Is Used) ............................... 412 LIST OF FIGURES (6/6) Title User’s Manual U11302EJ4V0UM Page 21 ...
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Table No. 1-1 Mask Options in Mask ROM Versions ........................................................................................... 2-1 Types of Pin I/O Circuits ................................................................................................................. 3-1 Internal ROM Capacity .................................................................................................................... 3-2 Vector Table .................................................................................................................................... 3-3 Special-Function Register List ........................................................................................................ 4-1 Port Functions ................................................................................................................................. 4-2 Port Configuration ........................................................................................................................... 4-3 ...
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Table No. 9-5 Interval Timer Interval Time ............................................................................................................ 181 10-1 Clock Output Controller Configuration ........................................................................................... 183 11-1 Buzzer Output Controller Configuration ......................................................................................... 186 12-1 A/D Converter Configuration ........................................................................................................... 190 13-1 Differences Between Channels 0 and 1 ......................................................................................... 205 13-2 Modes ...
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Features Internal high-capacity ROM and RAM Item Program Memory ROM Part Number µ PD780204 32 KB µ PD780204A µ PD780205 40 KB µ PD780205A µ PD780206 48 KB µ PD780208 60 KB µ PD78P0208 — Notes 1. ...
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Applications Compact home stereo sets, cassette decks, tuners, CD players, VCRs, etc. 1.3 Ordering Information Part Number µ PD780204GF-xxx-3BA µ PD780204AGF-xxx-3BA µ PD780205GF-xxx-3BA µ PD780205AGF-xxx-3BA µ PD780206GF-xxx-3BA µ PD780208GF-xxx-3BA µ PD78P0208GF-3BA Remark xxx indicates ROM code suffix. 1.4 Quality ...
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... P16/ANI6 27 P15/ANI5 28 P14/ANI4 29 P13/ANI3 30 Cautions 1. Connect the IC (Internally Connected) pin directly Connect the Connect the AV SS Remark The pin connection in parentheses is intended for the µ PD78P0208. 26 CHAPTER 1 OUTLINE pin pin User’s Manual U11302EJ4V0UM 80 P87/FIP20 79 V LOAD ...
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... Analog reference voltage REF AV : Analog ground SS BUSY: Busy BUZ: Buzzer clock FIP0 to FIP52: Fluorescent indicator panel IC: Internally connected INTP0 to INTP3: External interrupt input P00 to P04: Port 0 P10 to P17: Port 1 P20 to P27: Port 2 P30 to P37: Port 3 P70 to P74: Port 7 P80 to P87: Port 8 ...
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... Cautions 1. (L): Connect independently (D): Connect via a driver Connect to ground RESET: Set to low level. 5. Open: Do not connect to anything A16: Address bus CE: Chip enable D0 to D7: Data bus 28 CHAPTER 1 OUTLINE via a pull-down resistor. SS OE: Output enable V : Power supply ...
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Series Lineup The 78K/0 Series product lineup is illustrated below. The part numbers in boxes indicate subseries names. Products in mass production Control µ PD78075B 100-pin µ PD78078 100-pin µ PD78070A 100-pin 100-pin µ PD780058 80-pin µ 80-pin ...
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The following lists the main functional differences between subseries products. • Non-Y subseries Function ROM Capacity (Bytes) 8-Bit 16-Bit Watch WDT A/D Subseries Name µ Control PD78075B ...
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Block Diagram TO0/P30 16-bit timer/ TI0/P00 event counter TO1/P31 8-bit timer/ event counter 1 TI1/P33 TO2/P32 8-bit timer/ TI2/P34 event counter 2 Watchdog timer Watch timer SI0/SB0/P25 Serial SO0/SB1/P26 interface 0 SCK0/P27 SI1/P20 SO1/P21 Serial SCK1/P22 interface 1 STB/P23 ...
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Overview of Functions Part Number Item ROM Internal memory High-speed RAM Expansion RAM Buffer RAM VFD display RAM General-purpose registers Minimum With main system instruction clock selected execution With subsystem time clock selected Instruction set I/O ports (including VFD ...
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... The mask ROM versions ( µ PD780204, µ PD780204A, µ PD780205, µ PD780205A, µ PD780206, and µ PD780208) have mask options. By specifying the mask options when ordering, the pull-up resistors and pull-down resistors listed in Table 1-1 can be incorporated. When these resistors are necessary, the number of external components and mounting space can be saved by utilizing the mask options. ...
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Pin Function List 2.1.1 Normal operating mode pins (1) Port pins (1/2) Pin Name I/O Port 0. P00 Input 5-bit I/O port. P01 I/O P02 P03 Note 1 P04 Input P10 to P17 I/O Port 1. 8-bit I/O port. ...
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... P120 to P127 I/O Port 12. P-ch open-drain 8-bit high-withstanding-voltage I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. In mask ROM versions, use of an on-chip pull-down resistor can be specified in 1-bit units with the mask option (connection specifiable in 4-bit units). SS CHAPTER 2 PIN FUNCTIONS Function ...
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... High withstanding voltage and high current output for VFD controller/ Output driver display output. In mask ROM versions, use of an on-chip pull-down resistor can be specified with the mask option. The µ PD78P0208 has on-chip pull-down resistors (connected LOAD High withstanding voltage and high current output for VFD controller/ ...
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... Non-port pins (2/2) Pin Name I/O X1 Input Crystal resonator connection for main system clock oscillation X2 — XT1 Input Crystal resonator connection for subsystem clock oscillation XT2 — V — Positive power supply DD V — High-voltage application for program write/verify. Connect PP directly — ...
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... P00 to P04 (Port 0) These pins constitute a 5-bit I/O port. Besides serving as I/O port pins, they function as external interrupt request inputs, an external count clock input to the timer, a capture trigger signal input, and crystal resonator connection for subsystem clock oscillation. The following operating modes can be specified in 1-bit units. ...
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... SI0, SI1, SO0, SO1 Serial interface serial data I/O pins (b) SCK0 and SCK1 Serial interface serial clock I/O pins (c) SB0 and SB1 NEC Electronics standard serial bus interface I/O pins (d) BUSY Serial interface automatic transmit/receive busy input pin (e) STB Serial interface automatic transmit/receive strobe output pin Caution If port 2 is used as serial interface pins, the I/O and output latches must be set according to the function ...
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Control mode P30 to P37 function as timer I/O, clock output, and buzzer output pins. (a) TI1 and TI2 Pins for external count clock input to the 8-bit timer/event counter. (b) TO0 to TO2 Timer output pins (c) PCL ...
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... These are display output pins for the VFD controller/driver. FIP0 to FIP12 are P-ch open-drain outputs. In mask ROM versions, use of pull-down resistors can be specified with the mask option. The µ PD78P0208 contains pull-down resistors at FIP0 to FIP12 (connected to V CHAPTER 2 PIN FUNCTIONS User’s Manual U11302EJ4V0UM ) ...
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... IC (mask ROM version only) The IC (Internally Connected) pin sets a test mode in which the µ PD780204, 780204A, 780205, 780205A, 780206, and 780208 are tested before shipment. In normal operation mode, connect the IC pin directly to the V as short a wiring length as possible. If there is a potential difference between the IC and V pins is too long, or external noise is superimposed on the IC pin, the user program may not run correctly. • ...
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... Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-1 shows the I/O circuit types of pins and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-1. Types of Pin I/O Circuits (1/2) Pin Name I/O Circuit Type P00/INTP0/TI0 2 P01/INTP1 8-A P02/INTP2 P03/INTP3 P04/XT1 ...
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... LOAD Note Leave open when an on-chip pull-up or pull-down resistor is specified by the mask option. 44 CHAPTER 2 PIN FUNCTIONS I/O Recommended Connection of Unused Pins I/O Input: Independently connect to V Output: Leave open. I/O Input: Independently connect to V Output: Leave open. Output Leave open. I/O Input: Independently connect to V Output: Leave open. — ...
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Figure 2-1. Pin I/O Circuits (1/3) Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5 Pull-up enable V DD Data P-ch Output N-ch disable Input enable Type 5-C V Pull-up enable V DD Data P-ch Output N-ch ...
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Type 11 Pull-up enable V DD Data P-ch Output N-ch disable P-ch Comparator + – N-ch V (Threshold voltage) REF Input enable Type 13-B Mask option Data N-ch Output disable V P-ch RD Middle-voltage input buffer Type 13-D Data N-ch ...
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Figure 2-1. Pin I/O Circuits (3/3) Type 15 P-ch P-ch Data N-ch RD N-ch Type 15 P-ch P-ch Data N-ch RD N-ch CHAPTER 2 PIN FUNCTIONS Type 16 DD Feedback cut-off IN/OUT P-ch XT1 ...
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CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Each product of the PD780208 Subseries accesses a memory space of 64 KB. Figures 3-1 to 3-5 show memory maps. Caution The initial values of the internal memory size switching register (IMS) in ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map ( PD780205 and PD780205A) FFFFH Special-function registers (SFRs) 256 x 8 bits FF00H FEFFH General-purpose registers bits FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FB00H FAFFH Buffer ...
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Figure 3-3. Memory Map ( PD780206) FFFFH Special-function registers (SFRs) FF00H FEFFH General-purpose registers bits FEE0H FEDFH Internal high-speed RAM FB00H FAFFH FAC0H FABFH Data memory FA80H space FA7FH VFD display RAM FA30H FA2FH F800H F7FFH Internal ...
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Figure 3-4. Memory Map ( PD780208) FFFFH Special-function registers (SFRs) 256 x 8 bits FF00H FEFFH General-purpose registers bits FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FB00H FAFFH Buffer RAM bits FAC0H ...
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Figure 3-5. Memory Map ( PD78P0208) FFFFH Special-function registers (SFRs) 256 x 8 bits FF00H FEFFH General-purpose registers bits FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FB00H FAFFH Buffer RAM bits FAC0H ...
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Internal program memory space The internal program memory space stores programs and table data. Normally, this space is addressed using the program counter (PC). Each product in the PD780208 Subseries contains internal ROM (or PROM) with the capacity shown ...
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Internal data memory space The PD780208 Subseries units incorporate the following RAMs. (1) Internal high-speed RAM Internal high-speed RAM is allocated to the 1024-byte area from FB00H to FEFFH of the PD780208 Subseries. Four banks of general-purpose registers, each ...
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Data memory addressing The method to specify the address of the instruction to be executed next or the address of a register or memory area to be manipulated when an instruction is executed is called addressing. The address of ...
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Figure 3-7. Data Memory Addressing ( PD780205 and PD780205A) FFFFH Special-function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers bits FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Data Memory Addressing ( PD780206) FFFFH Special-function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers bits FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FE20H FE1FH ...
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Figure 3-9. Data Memory Addressing ( PD780208) FFFFH Special-function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers bits FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH Buffer RAM ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data Memory Addressing ( PD78P0208) FFFFH Special-function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers bits FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FE20H FE1FH ...
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Processor Registers The PD780208 Subseries units incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses, and stack memory. The program counter (PC), program status word (PSW), and stack pointer (SP) are control ...
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Auxiliary carry flag (AC) If the operation result has a carry from bit borrow at bit 3, this flag is set (1 reset (0) in all other cases. (e) In-service priority flag (ISP) This ...
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Figure 3-14. Data to Be Saved to Stack Memory PUSH rp instruction SP SP – 2 Lower SP – 2 register pairs Higher SP – 1 register pairs SP Figure 3-15. Data to Be Reset from Stack Memory POP rp ...
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General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. They consist of 4 banks, each bank consisting of eight 8-bit registers ( and H). Each register ...
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Special-function registers (SFRs) Unlike a general-purpose register, each special-function register has a special function. The special-function registers are allocated in the FF00H to FFFFH area. Special-function registers can be manipulated, like general-purpose registers, with operation, transfer, and bit manipulation ...
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Table 3-3. Special-Function Register List (1/3) Address Special-Function Register (SFR) Name FF00H Port 0 FF01H Port 1 FF02H Port 2 FF03H Port 3 FF07H Port 7 FF08H Port 8 FF09H Port 9 FF0AH Port 10 FF0BH Port 11 FF0CH Port ...
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Table 3-3. Special-Function Register List (2/3) Address Special-Function Register (SFR) Name FF60H Serial operating mode register 0 FF61H Serial bus interface control register FF62H Slave address register FF63H Interrupt timing specification register FF68H Serial operating mode register 1 FF69H Automatic ...
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Table 3-3. Special-Function Register List (3/3) Address Special-Function Register (SFR) Name FFF0H Internal memory size switching register FFF4H Internal expansion RAM size switching register FFF7H Pull-up resistor option register FFF9H Watchdog timer mode register FFFAH Oscillation stabilization time select register ...
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Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of the instruction to be fetched each time another ...
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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and ...
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Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits the immediate data of an operation code are transferred to the program counter (PC) and branched. Table ...
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Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration ...
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... Register A for storage of digit data which undergoes digit rotation [Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of register A and register X is stored in AX. In this example, the A and AX registers are specified by implied addressing ...
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Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified by register bank select flags (RBS0 and RBS1) and the register specification code (Rn, RPn) in the operation code. Register ...
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Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier addr16 [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code [Illustration CHAPTER 3 CPU ARCHITECTURE ...
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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this addressing is applied to is the 256-byte space from FE20H ...
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Special-function register (SFR) addressing [Function] A memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped ...
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Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register bank select flag (RBS0 and RBS1) and the register ...
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Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL register pair to be accessed is in ...
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Based indexed addressing [Function] The register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. ...
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CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD780208 Subseries units incorporate two input ports, 16 output ports, and 56 I/O ports. Figure 4-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can ...
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... P90 to P97 Port 9. P-ch open-drain 8-bit high withstanding voltage output port. LEDs can be driven directly. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option (can be specified as connected to V CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions (1/2) Function Input only. ...
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... P120 to P127 Port 12. P-ch open-drain 8-bit high withstanding voltage I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option (can be specified as connected CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions (2/2) Function 4-bit units) ...
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... The P00 and P04 pins are input-only port pins. When the P01 to P03 pins are used as input port pins, on-chip pull-up resistors can be connected to them in 3-bit units using the pull- up resistor option register (PUO). ...
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Figure 4-2. Block Diagram of P00 and P04 RD Figure 4-3. Block Diagram of P01 to P03 WR PUO PUO0 RD WR PORT Output latch (P01 to P03 PM01 to PM03 PUO: Pull-up resistor option register PM: Port ...
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... Port 8-bit I/O port with an output latch. The P10 to P17 pins can be set to input mode/output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as input port pins, on-chip pull- up resistors can be connected to them in 8-bit units using the pull-up resistor option register (PUO). Alternate functions include A/D converter analog input. ...
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... When the P20 to P27 pins are used as input port pins, on-chip pull- up resistors can be connected to them in 8-bit units using the pull-up resistor option register (PUO). Alternate functions include serial interface data I/O, clock I/O, automatic transmit/receive busy input, and strobe output ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P22 and P27 WR PUO PUO2 RD WR PORT Output latch (P22, P27 PM22, PM27 Alternate function PUO: Pull-up resistor option register PM: Port mode register RD: Port 2 ...
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... When the P30 to P37 pins are used as input port pins, on-chip pull- up resistors can be connected to them in 8-bit units using the pull-up resistor option register (PUO). In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option. The µ ...
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... ROM version] • When a pull-up resistor is connected: • –3 µ A (max.) regardless of operational conditions • When a pull-up resistor is not connected: • –200 µ A (max.) during 1.5 clock cycles after read instruction execution to port 7 (P7) or port mode register 7 (PM7) • –3 µ A (max.) under other conditions [For PROM version] • ...
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... Port 8 Port 8-bit output-only port. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option. Pull-down resistor connection to V µ PD78P0208 does not contain pull-down resistors. Port 8 can drive LEDs directly. Alternate functions include VFD controller/driver display output. ...
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... Port 9 Port 8-bit output-only port. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option. Pull-down resistor connection to V µ PD78P0208 does not contain pull-down resistors. Port 9 can drive LEDs directly. Alternate functions include VFD controller/driver display output. ...
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... Port 8-bit I/O port with an output latch. The P100 to P107 pins can be set to input mode/output mode in 1-bit units using port mode register 10 (PM10). In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option. Pull-down resistor connection to V The µ PD78P0208 does not contain pull-down resistors. ...
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... Port 8-bit I/O port with an output latch. The P110 to P117 pins can be set to input mode/output mode in 1-bit units using port mode register 11 (PM11). In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option. Pull-down resistor connection to V The µ PD78P0208 does not contain pull-down resistors. ...
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... Port 8-bit I/O port with an output latch. The P120 to P127 pins can be set to input mode/output mode in 1-bit units using port mode register 12 (PM12). In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option. Pull-down resistor connection to V The µ PD78P0208 does not contain pull-down resistors. ...
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Port Function Control Registers The following two types of registers control the ports. • Port mode registers (PM0, PM1, PM2, PM3, PM7, PM10, PM11, PM12) • Pull-up resistor option register (PUO) (1) Port mode registers (PM0, PM1, PM2, PM3, ...
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Figure 4-14. Format of Port Mode Register Symbol PM0 PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM36 PM35 PM34 PM33 PM32 PM31 PM3 ...
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Pull-up resistor option register (PUO) The PUO register enables or disables the on-chip pull-up resistor for each port pin. To enable the on-chip pull- up resistor of a port pin, the pin must be in the input mode and ...
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Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, ...
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... Can incorporate pull-down resistors in P80/FIP13 to P87/FIP20, 1-bit units. P90/FIP21 to P97/FIP28, The pull-down resistors can be specified to P100/FIP29 to P107/FIP36, be connected to V P110/FIP37 to P117/FIP44, from P80. P120/FIP45 to P127/FIP52 CHAPTER 4 PORT FUNCTIONS Does not incorporate pull-down resistors. Does not incorporate pull-up resistors. Incorporates pull-down resistors (connected to V Does not incorporate pull-down resistors ...
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CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit ...
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CHAPTER 5 CLOCK GENERATOR Figure 5-1. Clock Generator Block Diagram FRC XT1/P04 f Subsystem XT clock oscillator XT2 /16 X DSPM06 Main system clock oscillator X2 STOP Notes 1. Bit 6 of display ...
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Clock Generator Control Registers The clock generator is controlled by the following three registers. • Processor clock control register (PCC) • Display mode register 0 (DSPM0) • Display mode register 1 (DSPM1) (1) Processor clock control register (PCC) PCC ...
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Figure 5-3. Format of Processor Clock Control Register Symbol <7> <6> <5> <4> 3 PCC MCC FRC CLS CSS 0 Notes 1. Bit read-only bit. 2. This bit can be set to 1 only when the subsystem ...
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The fastest instruction of the µ PD780208 Subseries is executed in two CPU clocks. Therefore, the relationship between the CPU clock (f ) and minimum instruction execution time is as shown in Table 5-2. CPU Table 5-2. Relationship Between CPU ...
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Figure 5-4. Format of Display Mode Register 0 (1/2) Symbol DSPM0 KSF DSPM06 DSPM05 SEGS4 SEGS3 SEGS2 R/W SEGS4 SEGS3 SEGS2 SEGS1 SEGS0 ...
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Figure 5-4. Format of Display Mode Register 0 (2/2) Symbol DSPM0 KSF DSPM06 DSPM05 SEGS4 SEGS3 SEGS2 R/W DSPM05 Display mode setting 0 Display mode 1 (segment/character type) 1 Display mode 2 (type in which ...
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Display mode register 1 (DSPM1) Register to set display operation/stop. DSPM1 is set with an 8-bit memory manipulation instruction. RESET input sets DSPM1 to 00H. Remark In addition to setting display operation/stop, DSPM1 can also set the display digits/number ...
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Figure 5-5. Format of Display Mode Register 1 Symbol DSPM1 DIGS3 DIGS2 DIGS1 DIGS0 DIMS3 DIMS2 DIMS0 Display mode cycle setting is 1 display cycle (1 display cycle = 204.8 µ 5.0 MHz ...
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... Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and its inverted signal to the X2 pin. ...
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... Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the XT1 pin and its inverted signal to the XT2 pin. ...
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... CHAPTER 5 CLOCK GENERATOR Figure 5-8. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring of connected circuit (c) High alternating current close to signal lines Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Further, insert resistors in series on the side of XT2. ...
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... XT2. Cautions 2. If XT2 and X1 are wired in parallel, malfunction may occur due to the crosstalk noise between XT2 and X1. To prevent this, connect the IC pin directly to the V pins, and do not wire XT2 and X1 in parallel. 112 CHAPTER 5 CLOCK GENERATOR ...
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... In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops. To prevent this from happening, set bit 6 (FRC) of the processor clock control register (PCC) to disable use of the above internal feedback resistor. In this case also, connect the XT1 and XT2 pins as described above. ...
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Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock f X • Subsystem clock f XT • CPU clock f CPU ...
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Main system clock operations During operation with the main system clock (when bit 5 (CLS) of the processor clock control register (PCC) is set to 0), the following operations are carried out via PCC settings. (a) Because the operation ...
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Figure 5-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC during main system clock operation MCC CSS CLS Main system clock oscillation Subsystem clock oscillation CPU clock 5.5.2 Subsystem clock operations During operation ...
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Changing System Clock and CPU Clock Settings 5.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by using bits (PCC0 to PCC2) and bit ...
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System clock and CPU clock switching procedure This section describes the procedure for switching between the system clock and CPU clock. Figure 5-10. System Clock and CPU Clock Switching V DD RESET Interrupt request signal System clock CPU clock ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.1 Outline of Timers Incorporated in µ PD780208 Subseries This chapter explains the 16-bit timer/event counter. First of all, the timers incorporated in the µ PD780208 Subseries and other related parts are outlined below. (1) ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Table 6-1. Timer/Event Counter Operations Operation Interval timer mode External event counter Function Timer output PWM output Pulse width measurement Square-wave output Interrupt request Test input Notes 1. The watch timer can perform both watch ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (1) Interval timer TM0 generates interrupt requests at the preset time interval. Table 6-2. 16-Bit Timer/Event Counter Interval Time Minimum Interval Time 2 x TI0 input cycle 2 x 1/f (400 ns ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.3 16-Bit Timer/Event Counter Configuration The 16-bit timer/event counter consists of the following hardware. Table 6-4. 16-Bit Timer/Event Counter Configuration Item Timer register Registers Timer outputs Control registers Note Refer to Figure 16-1 Basic Configuration ...
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Note 1 TI0/P00/INTP0 0 TCL06 TCL05 TCL04 Timer clock select register 0 Internal bus 15 16-bit compare register (CR00) Match Match 7 15 16-bit timer ...
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PWM pulse generator 16-bit timer register (TM0) 3 16-bit capture register (CR01) TCL06 TCL05 TCL04 Timer clock select register 0 Internal bus 16-bit ...
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LVR0 LVS0 TOC01 INTTM0 Edge TI0/P00/INTP0 detector 2 Note 1 ES10, ES11 PWM pulse generator TMC01 to TMC03 Level F/F (LV0 INV 3 3 Active level control TOC01 TMC01 to TMC03 TO0/P30 Note 2 P30 PM30 output ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (1) 16-bit compare register (CR00) CR00 is a 16-bit register whose value is constantly compared with the 16-bit timer register (TM0) count value, and an interrupt request (INTTM0) is generated if they match. It can ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.4 16-Bit Timer/Event Counter Control Registers The following six registers are used to control the 16-bit timer/event counter. • Timer clock select register 0 (TCL0) • 16-bit timer mode control register (TMC0) • 16-bit timer ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-4. Format of Timer Clock Select Register 0 Symbol <7> TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 Cautions 1. The TI0/INTP0 pin valid edge is specified by the external interrupt ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (2) 16-bit timer mode control register (TMC0) This register sets the 16-bit timer operating mode, the 16-bit timer register clear mode and output timing, and detects an overflow. TMC0 is set with a 1-bit or ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-5. Format of 16-Bit Timer Mode Control Register Symbol TMC0 OVF0 16-bit timer register overflow detection 0 Overflow not detected 1 Overflow detected Operating mode & clear TMC03 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (3) 16-bit timer output control register (TOC0) This register controls the operation of the 16-bit timer/event counter output controller. It sets/resets the R-S type flip-flop (LV0), sets the active level in PWM mode, and enables/disables ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P30/TO0 pin for timer output, set PM30 and the output latch of P30 to 0. PM3 is ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (5) External interrupt mode register (INTM0) This register is used to set the INTP0 to INTP2 and TI0 valid edges. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 to 00H. ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (6) Sampling clock select register (SCS) This register sets the clock to be used for sampling the valid edge input to INTP0. When remote controlled reception is carried out using INTP0, digital noise is eliminated ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.5 16-Bit Timer/Event Counter Operations 6.5.1 Interval timer operations By setting bits 2 and 3 (TMC02 and TMC03) of the 16-bit timer mode control register (TMC0 the 16-bit timer/event counter operates as ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-11. Interval Timer Operation Timing t Count clock TM0 count value 0000 0001 Count start CR00 N INTTM0 TO0 Interval time Remark Interval time = ( 0001H to ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.5.2 PWM output operations By setting bits (TMC01 to TMC03) of the 16-bit timer mode control register (TMC0 the 16-bit timer/ event counter operates as PWM output. Pulses ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-13 shows an example in which PWM output is converted to an analog voltage and used in a voltage synthesizer type TV tuner. Figure 6-13. TV Tuner Application Circuit Example +110 V µ PD780205 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-14. Configuration Diagram for Pulse Width Measurement in Free-Running Mode TI0/P00/INTP0 Figure 6-15. Timing of Pulse Width Measurement Operation in Free-Running ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (2) Pulse width measurement by means of restart When input of a valid edge to the TI0/P00 pin is detected, the count value of the 16-bit timer register (TM0) is taken into the 16-bit capture ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-17. External Event Counter Configuration Diagram TI0 valid edge Figure 6-18. External Event Counter Operation Timing (with Rising Edge Specified) TI0 pin input TM0 count value 0000 0001 0002 0003 0004 0005 CR00 INTTM0 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.5.5 Square-wave output operation The 16-bit timer/event counter outputs a square-wave of any frequency with the value preset to the 16-bit compare register (CR00) as the interval. The TO0/P30 pin output status is reversed at ...
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... If the value after the 16-bit compare register (CR00) is changed is smaller than that of the 16-bit timer register (TM0), TM0 continues counting, overflows and then restarts counting from 0. Thus, if the value after CR00 change (M) is smaller than that before change (N necessary to restart the timer after changing CR00. Figure 6-21. Timing After Compare Register Change During Timer Count Operation ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER (4) Capture register data retention timing If the valid edge of the TI0/P00 pin is input during 16-bit capture register (CR01) read, CR01 holds the data without carrying out the capture operation. However, the interrupt ...
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CHAPTER 7 7.1 8-Bit Timer/Event Counter Functions The following two modes are available for the 8-bit timer/event counter incorporated in the µ PD780208 Subseries. • 8-bit timer/event counter mode: • 16-bit timer/event counter mode: Two-channel 8-bit timer/event counter used as ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 7-1. 8-Bit Timer/Event Counter Interval Time Minimum Interval Time 2 x 1/f (400 ns 1/f (800 ns) ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 7-2. 8-Bit Timer/Event Counter Square-Wave ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals. Table 7-3. Interval Time When 8-Bit Timer/Event Counter Is Used as 16-Bit Timer/Event Counter Minimum Interval ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 7-4. Square-Wave Output Ranges When ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.2 8-Bit Timer/Event Counter Configuration The 8-bit timer/event counter consists of the following hardware. Table 7-5. 8-Bit Timer/Event Counter Configuration Item Timer register Registers Timer outputs Control registers Note Refer to Figure 4-7 Block Diagram ...
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TI1/P33 fx/2 to fx/2 12 fx/2 TI2/P34 4 TCL TCL TCL TCL TCL TCL TCL TCL ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter Output Controller 1 Level F/F LVR1 R LVS1 S TOC11 INV INTTM1 Note Bit 1 of port mode register 3 (PM3) Remark The circuitry enclosed by the ...
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... When the values of CR10 and CR20 after changing are smaller than those of the 8-bit timer registers (TM1, TM2), TM1 and TM2 continue to count. When they overflow, counting starts again from 0. Therefore necessary to restart the timer after changing the values of CR10 and CR20 if the values of CR10 and CR20 are smaller than the values before changing. ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-4. Format of Timer Clock Select Register 1 Symbol TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 Caution If TCL1 rewritten with data other than identical data, the ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER (2) 8-bit timer mode control register (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8- bit timer registers 1 and 2. TMC1 is set with ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER (3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output controllers 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER (4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and the output latches of P31 and ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4 8-Bit Timer/Event Counter Operations 7.4.1 8-bit timer/event counter mode (1) Interval timer operations The 8-bit timer/event counter operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER Table 7-6. 8-Bit Timer/Event Counter 1 Interval Time TCL13 TCL12 TCL11 TCL10 TI1 input cycle TI1 input cycle 1 ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER (2) External event counter operation The external event counter counts the number of external clock pulses input to the TI1/P33 and TI2/P34 pins using 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER (3) Square-wave output operation The 8-bit timer/event counter outputs a square wave of any frequency with the value preset to the 8-bit compare register (CR10, CR20) as the interval. The TO1/P31 or TO2/P32 pin output ...
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When bit 2 (TMC12) of the 8-bit timer mode control register (TMC1) is set to 1, the 16-bit timer/event counter mode is set. In this mode, the count clock is selected using bits 0 to ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the CR10 value, an interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter output controller 1 ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER (2) External event counter operations The external event counter counts the number of external clock pulses input to the TI1/P33 pin by using the two channels of 8-bit timer registers 1 and 2 (TM1 and ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER (3) Square-wave output operation Square-wave signals can be generated at the user-specified frequency. The frequency or pulse interval is determined by the value preset in the 8-bit compare registers (CR10 and CR20). To set a ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.5 8-Bit Timer/Event Counter Operating Precautions (1) Timer start error An error one clock may occur in the time required for a match signal to be generated after timer start. This is ...
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... TM2), TM1 and TM2 continue counting, overflow and then restart counting from 0. Thus, if the value after CR10 and CR20 (M) change is smaller than that before the change (N necessary to restart the timer after changing CR10 and CR20. Figure 7-16. Timing After Compare Register Change During Timer Count Operation ...
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Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768 kHz subsystem clock is used, a ...
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Watch Timer Configuration The watch timer consists of the following hardware. Table 8-2. Watch Timer Configuration Item Counter Control registers 8.3 Watch Timer Control Registers The following two registers are used to control the watch timer. • Timer clock ...
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TMC21 Clear Prescaler TCL24 Timer clock select register 2 Internal bus 5-bit counter Clear f f ...
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... Note When using a main system clock of 1.25 MHz or less and the VFD controller/driver, select f the count clock for the watch timer. Caution When changing the count clock, be sure to stop operation of the watch timer before rewriting TCL2 (stopping operation is not necessary when rewriting the same data). Remarks Main system clock oscillation frequency X 2 ...
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Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation ...
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Watch Timer Operations 8.4.1 Watch timer operation When the 32.768 kHz subsystem clock is used, the timer operates as a watch timer with a 0.5-second or 0.25- second interval. In addition, when the 4.19 MHz main system clock is ...
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CHAPTER 9 9.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode using the watchdog timer mode register (WDTM) (the watchdog timer ...
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Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 9-3. Watchdog Timer Configuration Item Control registers CHAPTER 9 WATCHDOG TIMER Configuration Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) User’s Manual U11302EJ4V0UM 175 ...
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8-bit prescaler f WDT WDT WDT WDT WDT WDT WDT Timer clock select register 2 ...
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Watchdog Timer Control Registers The following two registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the ...
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Figure 9-2. Format of Timer Clock Select Register 2 Symbol TCL2 TCL27 TCL26 TCL25 TCL24 Note must be selected as the watch timer count clock when using a main system clock of 1.25 ...
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Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 9-3. Format of Watchdog Timer ...
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Watchdog Timer Operations 9.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer operates to detect an inadvertent program loop. The watchdog timer count clock (program loop ...
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Interval timer operation The watchdog timer operates as an interval timer that generates interrupt requests repeatedly at intervals of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is cleared to 0. The ...
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CHAPTER 10 CLOCK OUTPUT CONTROLLER 10.1 Clock Output Controller Functions The clock output controller is used for carrier output during remote controlled transmission and clock output for supply to a peripheral LSI. The clock selected by timer clock select register ...
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CHAPTER 10 CLOCK OUTPUT CONTROLLER 10.2 Clock Output Controller Configuration The clock output controller consists of the following hardware. Table 10-1. Clock Output Controller Configuration Item Control registers Figure 10-2. Clock Output Controller Block Diagram ...
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Figure 10-3. Format of Timer Clock Select Register 0 Symbol <7> TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 Cautions 1. The TI0/P00/INTP0 pin valid edge is set by the external interrupt mode register (INTM0), and the sampling ...
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CHAPTER 10 CLOCK OUTPUT CONTROLLER (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P35/PCL pin for clock output, set PM35 and the output latch of P35 to 0. PM3 is ...
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CHAPTER 11 11.1 Buzzer Output Controller Functions The buzzer output controller outputs a 1.2 kHz, 2.4 kHz, or 4.9 kHz frequency square-wave. The buzzer frequency selected by timer clock select register 2 (TCL2) is output from the BUZ/P36 pin. Follow ...
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CHAPTER 11 BUZZER OUTPUT CONTROLLER 11.3 Buzzer Output Function Control Registers The following two registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select ...
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... TCL25 TCL24 Cautions 1. Be sure to stop operation of the watch timer or buzzer to be changed before rewriting TCL2 (stopping operation is not necessary when rewriting the same data). The operation is stopped by the following methods. • Buzzer output: Input 0 to bit 7 (TCL27) of TCL2 • Watch timer: 2 ...
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CHAPTER 11 BUZZER OUTPUT CONTROLLER (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P36/BUZ pin for buzzer output, set PM36 and the output latch of P36 to 0. PM3 is ...
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CHAPTER 12 12.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion ...
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Figure 12-1. Internal bus A/D converter input select register ADIS3 ADIS2 ADIS1 ADIS0 4 ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 3 ADM1 to ADM3 Falling edge INTP3/P03 detector Trigger enable CS TRG FR1 FR0 ADM3 ADM2 ADM1 A/D ...
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... Voltage comparator The voltage comparator compares the analog input with the series resistor string output voltage. (5) Series resistor string The series resistor string is connected between AV with the analog input. (6) ANI0 to ANI7 pins These are 8-channel analog input pins used to input the analog signals to undergo A/D conversion to the A/D converter ...
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... Caution A series resistor string of approximately 10 kΩ is connected between the AV the AV pin. Therefore, if the output impedance of the reference voltage source is high, SS this will result in series connection to the series resistor string between the AV and the AV pin, and there will be a large reference voltage error. SS ...
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A/D Converter Control Registers The following two registers are used to control the A/D converter. • A/D converter mode register (ADM) • A/D converter input select register (ADIS) (1) A/D converter mode register (ADM) This register sets the analog ...
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Figure 12-2. Format of A/D Converter Mode Register Symbol <7> <6> ADM CS TRG FR1 FR0 ADM3 ADM2 ADM1 ADM3 ADM2 ADM1 Analog input channel selection ANI0 ANI1 ...
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... Using the A/D converter mode register (ADM), select the channel to undergo A/ D conversion among the channels which were set to analog input using ADIS internal pull-up resistor can be connected to the channels set to analog input using ADIS, irrespective of the value of bit 1 (PUO1) of the pull-up resistor option register (PUO) ...
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A/D Converter Operations 12.4.1 Basic operations of A/D converter [1] Set the number of analog input channels using the A/D converter input select register (ADIS). [2] From among the analog input channels set by ADIS, select the channel for ...
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Figure 12-4. Basic Operation of A/D Converter Sampling time A/D converter Sampling operation Un- SAR 80H defined ADCR INTAD A/D conversion operations are performed continuously until bit 7 (CS) of ADM is reset (0) by software write to ...
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Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/ D conversion result (the value stored in the A/D conversion result register (ADCR)) is shown ...
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A/D converter operating mode Select one analog input channel from among ANI0 to ANI7 using the A/D converter input select register (ADIS) and A/D converter mode register (ADM) and start A/D conversion. A/D conversion can be started in the ...