MAX3945ETE+ Maxim Integrated Products, MAX3945ETE+ Datasheet - Page 17

• Manufacturer Part Number: MAX3945ETE+
• Description: IC AMP LIMITING 3.3V LP 16TQFN
• Manufacturer: Maxim Integrated Products
• Type: Limiting Amplifierr

Specifications of MAX3945ETE+

• Applications: Optical Networks
• Mounting Type: Surface Mount
• Package / Case: 16-WQFN Exposed Pad, 16-DQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 5. Timing for the 3-Wire Digital Interface
Table 11. Interface Timing Parameters
Bits 7 and 6: RXDE[1:0]. These 2 bits are used to control deemphasis of the output waveform. See Table 5 for the bit
settings and corresponding deemphasis levels.
Bit 4: SOFTRES. When this bit is set to 1 during a 3-wire interface write operation, all registers are set to the default
state when CSEL goes low.
Bits 3 and 2: BW[1:0]. When RATE_SEL = 0, these 2 bits control the bandwidth of the limiting amplifier. See Table 1 for
the settings and corresponding filter selection.
Bit 1: RATE_SEL. RATE_SEL selects between the low bandwidth data path (1.0625Gbps to 4.25Gbps) and the high
bandwidth data path (4.25Gbps to 11.3Gbps). When RATE_SEL is set to 1, the high bandwidth path is chosen. When
RATE_SEL is set to 0, the low bandwidth path is chosen.
Bit #
Name
Default Value
CSEL
CSEL
SDA
SDA
SCL
SCL
WRITE MODE
READ MODE
SYMBOL
t
t
t
t
CH
t
DS
DH
t
CL
t
D
L
T
*Do not change default setting.
t
t
L
L
A6
A6
______________________________________________________________________________________
RXDE1
7
0
t
t
CH
CH
0
0
t
t
CL
CL
A5
A5
1
1
CSEL leading time before the first SCL edge
SCL pulse-width high
SCL pulse-width low
SCL rise to SDA propagation time
SDA setup time
SDA hold time
CSEL trailing time after last SCL edge
RXDE0
t
t
DS
DS
A4
A4
2
2
6
0
SFP+ Dual-Path Limiting Amplifier
A3
A3
t
t
3
3
DH
DH
A2
A2
4
4
X*
5
1
A1
A1
5
5
SOFTRES
A0
A0
6
6
4
0
1.0625Gbps to 11.3Gbps,
RWN
RWN
7
7
D7
8
8
BW1
D7
3
1
D6
DEFINITION
9
9
D6
t
D
D5
10
10
D5
BW0
Receiver Control Register 1 (RXCTRL1)
2
1
D4
11
11
D4
D3
12
12
RATE_SEL
D3
D2
1
1
13
13
Register Descriptions
D2
D1
14
14
D1
D0
15
15
X*
0
1
D0
t
t
T
T
ADDRESS
H0x00
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