MAX3945ETE+ Maxim Integrated Products, MAX3945ETE+ Datasheet - Page 19

• Manufacturer Part Number: MAX3945ETE+
• Description: IC AMP LIMITING 3.3V LP 16TQFN
• Manufacturer: Maxim Integrated Products
• Type: Limiting Amplifierr

Specifications of MAX3945ETE+

• Applications: Optical Networks
• Mounting Type: Surface Mount
• Package / Case: 16-WQFN Exposed Pad, 16-DQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 1: POR_2d. When the V
voltage is above 2.75V, the POR circuitry deasserts, but the POR_2d bit remains high until it is read.
Bit 0: LOS_2d. Copy of the LOS status. This is a sticky bit, which means that it is cleared on a read. The first 0-to-1
transition is latched until the bit is read by the master or POR occurs.
Bits 7 to 0: SET_CML[7:0]. The SET_CML register is an 8-bit register that can be set up to 255 for maximum CML
output amplitude. See Table 13 for equations to determine CML output level vs. SET_CML.
Bits 5 to 0: SET_LOS[5:0]. The SET_LOS register is a 6-bit register used to program the LOS threshold. See the
Typical Operating Characteristics section for a typical LOS threshold voltage vs. DAC code for both the Rx input-based
LOS and the RSSI monitor-based LOS.
Bit #
Name
Default Value
Bit #
Name
Default Value
Bit #
Name
Default Value
SET_CML[7]
______________________________________________________________________________________
(MSB)
X
X
X
X
7
7
0
7
SET_CML[6] SET_CML[5] SET_CML[4] SET_CML[3] SET_CML[2] SET_CML[1]
CC
X
X
X
X
6
6
1
6
supply voltage is below 2.3V, the POR circuitry sets POR_2d high. When the supply
SFP+ Dual-Path Limiting Amplifier
SET_LOS[5]
(MSB)
X
X
5
5
0
5
0
SET_LOS[4] SET_LOS[3] SET_LOS[2] SET_LOS[1]
4
X
X
4
1
4
0
1.0625Gbps to 11.3Gbps,
LOS Threshold Assert Level Setting Register (SET_LOS)
3
X
X
3
1
3
1
CML Output Level Setting Register (SET_CML)
2
X
X
2
1
2
1
Receiver Status Register (RXSTAT)
(STICKY)
POR_2d
1
X
1
0
1
0
SET_CML[0]
SET_LOS[0]
(STICKY)
LOS_2d
(LSB)
(LSB)
0
X
0
0
0
0
ADDRESS
ADDRESS
ADDRESS
H0x02
H0x03
H0x04
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