MC68360 Motorola, MC68360 Datasheet
MC68360
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MC68360 Summary of contents
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... Motorola was negligent regarding the design or manufacture of the part. Motorola and the Equal Opportunity/Affirmative Action Employer. MC68360 QUad Integrated User’s Manual ...
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... MC68360 USER’S MANUAL MOTOROLA ...
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... The complete documentation package for the MC68360 consists of the MC68360UM/AD, MC68360 QUad Integrated Communications Controller User’s Manual , M68000PM/AD, MC68000 Family Programmer’s Reference Manual, and the MC68360/D, MC68360 QUad Integrated Communications Controller Product Brief . The MC68360 QUad Integrated Communications Controller User’s Manual describes the programming, capabilities, registers, and operation of the MC68360 and the MC68EN360 ...
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... MC68360 USER’S MANUAL MOTOROLA ...
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... Interrupt Request Level (IRQ7–IRQ1)..................................................... 2-7 2.1.7 Bus Control Signals................................................................................. 2-7 2.1.7.1 Data and Size Acknowledge (DSACK1–DSACK0). ................................ 2-8 2.1.7.2 Autovector/Interrupt Acknowledge (AVEC/IACK5).................................. 2-8 2.1.7.3 Address Strobe (AS). .............................................................................. 2-8 2.1.7.4 Data Strobe (DS)..................................................................................... 2-8 MOTOROLA Thi d Title Section 1 Introduction Section 2 Signal Descriptions MC68360 USER’S MANUAL ith Table of Contents Page Number i ...
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... Test Data Out (TDO)..............................................................................2-12 2.1.13 Initial Configuration Pins (CONFIG).......................................................2-12 2.1.14 Power Signals ........................................................................................2-13 2.1.14.1 VCCSYN and GNDSYN.........................................................................2-13 2.1.14.2 VCCCLK and GNDCLK. ........................................................................2-13 2.1.14.3 GNDS1 and GNDS2. .............................................................................2-13 2.1.14.4 VCC and GND. ......................................................................................2-13 2.1.14.5 NC4–NC1...............................................................................................2-13 2.2 System Bus Signal Index in Slave Mode ...............................................2-14 2.3 On-Chip Peripherals Signal Index..........................................................2-15 ii Title Section 3 MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... Interrupt Acknowledge Cycle—Terminated Normally............................ 4-36 4.4.4.2 Autovector Interrupt Acknowledge Cycle. ............................................. 4-38 4.4.4.3 Spurious Interrupt Cycle........................................................................ 4-40 4.5 Bus Exception Control Cycles ............................................................... 4-41 4.5.1 Bus Errors ............................................................................................. 4-42 4.5.2 Retry Operation ..................................................................................... 4-44 4.5.3 Halt Operation ....................................................................................... 4-46 4.5.4 Double Bus Fault................................................................................... 4-48 MOTOROLA Title QUICC Memory Map Section 4 Bus Operation MC68360 USER’S MANUAL Table of Contents Page Number iii ...
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... Shift and Rotate Instructions..................................................................5-22 5.3.3.6 Bit Manipulation Instructions ..................................................................5-23 5.3.3.7 Binary-Coded Decimal (BCD) Instructions.............................................5-24 5.3.3.8 Program Control Instructions .................................................................5-24 5.3.3.9 System Control Instructions ...................................................................5-25 5.3.3.10 Condition Tests ......................................................................................5-26 5.3.4 Using the TBL Instructions.....................................................................5-27 5.3.4.1 Table Example 1: Standard Usage ........................................................5-28 5.3.4.2 Table Example 2: Compressed Table....................................................5-29 iv Title Section 5 CPU32+ MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... Type II—Correcting Faults via RTE....................................................... 5-54 5.5.3.2.4 Type III—Correcting Faults via Software............................................... 5-54 5.5.3.2.5 Type III—Correcting Faults by Conversion and Restart........................ 5-55 5.5.3.2.6 Type III—Correcting Faults via RTE...................................................... 5-55 5.5.3.2.7 Type IV—Correcting Faults via Software .............................................. 5-55 5.5.4 CPU32+ Stack Frames ......................................................................... 5-56 MOTOROLA Title MC68360 USER’S MANUAL Table of Contents Page Number v ...
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... Dump Memory Block (DUMP)................................................................5-75 5.6.2.8.11 Fill Memory Block (FILL) ........................................................................5-76 5.6.2.8.12 Resume Execution (GO)........................................................................5-77 5.6.2.8.13 Call User Code (CALL) ..........................................................................5-77 5.6.2.8.14 Reset Peripherals (RST)........................................................................5-79 5.6.2.8.15 No Operation (NOP) ..............................................................................5-79 5.6.2.8.16 Future Commands .................................................................................5-80 5.6.3 Deterministic Opcode Tracking..............................................................5-80 5.6.3.1 Instruction Fetch (IFETCH) ....................................................................5-80 5.6.3.2 Instruction Pipe (IPIPE1–IPIPE0) ..........................................................5-80 5.6.3.3 Opcode Tracking during Loop Mode......................................................5-82 vi Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... Double Bus Fault Monitor........................................................................ 6-9 6.3.1.2.4 Software Watchdog Timer (SWT) ........................................................... 6-9 6.3.2 Periodic Interrupt Timer (PIT)................................................................ 6-10 6.3.2.1 PIT Period Calculation........................................................................... 6-10 6.3.2.2 Using the PIT as a Real-Time Clock ..................................................... 6-11 6.3.3 Freeze Support...................................................................................... 6-11 6.3.4 Low-Power Stop Support ...................................................................... 6-11 6.4 Low Power in Normal Operation ........................................................... 6-12 MOTOROLA Title Section 6 MC68360 USER’S MANUAL Table of Contents Page Number vii ...
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... System Configuration and Protection Registers ....................................6-29 6.9.3.1 Module Configuration Register (MCR)...................................................6-29 6.9.3.2 Autovector Register (AVR).....................................................................6-34 6.9.3.3 Reset Status Register (RSR) .................................................................6-34 6.9.3.4 Software Watchdog Interrupt Vector Register (SWIV)...........................6-35 6.9.3.5 System Protection Control Register (SYPCR) .......................................6-35 6.9.3.6 Periodic Interrupt Control Register (PICR).............................................6-37 viii Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... Base Register (BR) ............................................................................... 6-70 6.13.4 Option Register (OR)............................................................................. 6-74 6.13.5 DRAM-SRAM Performance Summary; ................................................. 6-78 Communication Processor Module (CPM) Introduction.............................................................................................. 7-1 7.1 RISC Controller ....................................................................................... 7-3 7.1.1 RISC Controller Configuration Register (RCCR).................................... 7-4 7.1.2 RISC Microcode Revision Number......................................................... 7-5 7.2 Command Set ........................................................................................ 7-5 7.2.1 Command Register Examples................................................................. 7-8 7.2.2 Command Execution Latency ................................................................. 7-8 MOTOROLA Title Section 7 MC68360 USER’S MANUAL Table of Contents Page Number ix ...
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... Channel Status Register (CSR) .............................................................7-32 7.6.2.8 Channel Mask Register (CMAR)............................................................7-33 7.6.2.9 Data Holding Register (DHR).................................................................7-33 7.6.3 Interface Signals ...................................................................................7-33 7.6.3.1 DREQ and DACK...................................................................................7-33 7.6.3.2 DONEx...................................................................................................7-33 7.6.4 IDMA Operation ....................................................................................7-34 7.6.4.1 Single Buffer ..........................................................................................7-34 7.6.4.2 Auto Buffer and Buffer Chaining ............................................................7-34 7.6.4.2.1 IDMA Parameter RAM ...........................................................................7-35 7.6.4.2.2 IDMA Buffer Descriptors (BDs) ..............................................................7-36 x Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... One Multiplexed Channel with Dynamic Frames .................................. 7-69 7.8.4.3 Two Multiplexed Channels with Static Frames...................................... 7-70 7.8.4.4 Two Multiplexed Channels with Dynamic Frames................................. 7-71 7.8.4.5 Programming SI RAM Entries ............................................................... 7-72 7.8.4.6 SI RAM Programming Example ............................................................ 7-75 7.8.4.7 SI RAM Dynamic Changes.................................................................... 7-75 7.8.5 SI Registers........................................................................................... 7-77 7.8.5.1 SI Global Mode Register (SIGMR) ........................................................ 7-77 MOTOROLA Title MC68360 USER’S MANUAL Table of Contents Page Number xi ...
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... Interrupts from the SCCs ....................................................................7-128 7.10.8.1 SCC Event Register (SCCE) ...............................................................7-128 7.10.8.2 SCC Mask Register (SCCM) ...............................................................7-129 7.10.8.3 SCC Status Register (SCCS) ..............................................................7-129 7.10.9 SCC Initialization.................................................................................7-129 7.10.10 SCC Interrupt Handling........................................................................7-130 7.10.11 SCC Timing Control .............................................................................7-130 7.10.11.1 Synchronous Protocols ........................................................................7-130 xii Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... S-Records Programming Example...................................................... 7-169 7.10.17 HDLC Controller .................................................................................. 7-169 7.10.17.1 HDLC Controller Key Features............................................................ 7-170 7.10.17.2 HDLC Channel Frame Transmission Processing................................ 7-171 7.10.17.3 HDLC Channel Frame Reception Processing..................................... 7-172 7.10.17.4 HDLC Memory Map............................................................................. 7-172 7.10.17.5 HDLC Programming Model ................................................................. 7-174 MOTOROLA Title MC68360 USER’S MANUAL Table of Contents Page Number xiii ...
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... BISYNC Channel Frame Reception.....................................................7-202 7.10.20.4 BISYNC Memory Map..........................................................................7-203 7.10.20.5 BISYNC Command Set........................................................................7-204 7.10.20.5.1 Transmit Commands............................................................................7-204 7.10.20.5.2 Receive Commands.............................................................................7-205 7.10.20.6 BISYNC Control Character Recognition ..............................................7-206 7.10.20.7 BSYNC-BISYNC SYNC Register.........................................................7-207 7.10.20.8 BDLE-BISYNC DLE Register...............................................................7-208 xiv Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... Learning Ethernet on the QUICC ........................................................ 7-238 7.10.23.4 Connecting QUICC to Ethernet ........................................................... 7-239 7.10.23.5 Ethernet Channel Frame Transmission............................................... 7-241 7.10.23.6 Ethernet Channel Frame Reception.................................................... 7-242 7.10.23.7 CAM Interface ..................................................................................... 7-243 7.10.23.8 Ethernet Memory Map......................................................................... 7-246 7.10.23.9 Ethernet Programming Model ............................................................. 7-250 7.10.23.10 Ethernet Command Set....................................................................... 7-250 MOTOROLA Title MC68360 USER’S MANUAL Table of Contents Page Number xv ...
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... SMC UART Comparison......................................................................7-276 7.11.7.3 SMC UART Memory Map ....................................................................7-277 7.11.7.4 SMC UART Transmission Processing .................................................7-278 7.11.7.5 SMC UART Reception Processing ......................................................7-279 7.11.7.6 SMC UART Programming Model.........................................................7-279 7.11.7.7 SMC UART Command Set ..................................................................7-279 7.11.7.7.1 Transmit Commands............................................................................7-279 xvi Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... SMC as a GCI Controller..................................................................... 7-305 7.11.14.1 SMC GCI Memory Map ....................................................................... 7-306 7.11.14.1.1 SMC Monitor Channel Transmission................................................... 7-306 7.11.14.1.2 SMC Monitor Channel Reception........................................................ 7-307 7.11.14.2 SMC C/I Channel Handling ................................................................. 7-307 7.11.14.2.1 SMC C/I Channel Transmission .......................................................... 7-307 7.11.14.2.2 SMC C/I Channel Reception ............................................................... 7-307 MOTOROLA Title MC68360 USER’S MANUAL Table of Contents Page Number xvii ...
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... SPI Slave Example ..............................................................................7-330 7.12.8 SPI Interrupt Handling..........................................................................7-331 7.13 Parallel Interface Port (PIP) .................................................................7-331 7.13.1 PIP Key Features.................................................................................7-331 7.13.2 PIP Overview .......................................................................................7-332 7.13.3 General-Purpose I/O Pins (Port B) ......................................................7-333 7.13.4 Interlocked Data Transfers...................................................................7-333 7.13.5 Pulsed Data Transfers .........................................................................7-334 7.13.5.1 Busy Signal ..........................................................................................7-335 xviii Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... Centronics Receiver Command Set .................................................... 7-354 7.13.8.20.1 INIT RX PARAMETERS Command .................................................... 7-354 7.13.8.20.2 CLOSE RX BD Command................................................................... 7-354 7.13.8.21 Receiver Errors ................................................................................... 7-354 7.13.8.21.1 Buffer Descriptor Busy ........................................................................ 7-354 7.13.8.22 Centronics Receive Buffer Descriptor ................................................. 7-354 7.13.8.23 Centronics Receiver Event Register (PIPE)........................................ 7-355 7.13.9 Port B Registers .................................................................................. 7-356 MOTOROLA Title MC68360 USER’S MANUAL Table of Contents Page Number xix ...
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... CPM Interrupt Configuration Register (CICR)......................................7-377 7.15.5.2 CPM Interupt Pending Register (CIPR) ...............................................7-379 7.15.5.3 CPM Interrupt Mask Register (CIMR) ..................................................7-380 7.15.5.4 CPM Interrupt In-Service Register (CISR) ...........................................7-380 7.15.6 Interrupt Handler Examples .................................................................7-381 7.15.6.1 Example 1—PC6 Interrupt Handler .....................................................7-381 7.15.6.2 Example 2—SCC1 Interrupt Handler...................................................7-381 xx Title MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... How to take A QUICC Software Test-Drive........................................... 9-13 Step 1: Decide on Reset Stack Pointer and Initial Program Counter .... 9-13 Step 2: Stay in Supervisor Mode........................................................... 9-13 Step 3: Write the VBR ........................................................................... 9-14 MOTOROLA Title Section 8 Scan Chain Test Access Port Section 9 Applications MC68360 USER’S MANUAL Table of Contents Page Number xxi ...
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... Step 16: Generate a SIM60 Interrupt.....................................................9-16 Step 17: Test the CPM...........................................................................9-17 Step 18: Generate Interrupts with the CPM ...........................................9-17 Step 19: Enable External Interrupts .......................................................9-17 Step 20: Enable External Bus Masters ..................................................9-18 Step 21: Off to the Races.......................................................................9-18 9.3 Porting MC68302 IMP Code to the MC68360 QUICC...........................9-18 9.3.1 CPU and Compilers ...............................................................................9-18 9.3.2 Differences/Similarities ..........................................................................9-18 9.3.3 Notes About Porting...............................................................................9-19 9 ...
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... Interfacing an MC68EC030 Master to the QUICC In Slave Mode ........ 9-74 9.8.1 MC68EC030 to QUICC Interface .......................................................... 9-74 9.8.1.1 MC68EC030 Reads and Writes to QUICC............................................ 9-75 9.8.1.2 Clocking Strategy. ................................................................................. 9-75 9.8.1.3 Reset Strategy....................................................................................... 9-77 9.8.1.4 Interrupts ............................................................................................... 9-77 9.8.1.5 Bus Arbitration....................................................................................... 9-78 9.8.1.6 Breakpoint Generation .......................................................................... 9-78 9.8.1.7 Bus Monitor Function ............................................................................ 9-78 9.8.1.8 Spurious Interrupt Monitor..................................................................... 9-78 9.8.1.9 Software Watchdog ............................................................................... 9-79 9.8.1.10 Periodic Interval Timer .......................................................................... 9-79 MOTOROLA Title MC68360 USER’S MANUAL Table of Contents Page Number xxiii ...
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... Bus Type Slave Mode Bus Arbitration AC Electrical Specifications10-49 10.16 040 Bus Type Slave Mode Internal Read/write/IACK Cycles AC Electrical Specifications10-51 10.17 040 Bus Type SRAM/DRAM Cycles Ac Electrical Specifications .......10-56 10.18 IDMA AC Electrical Specifications ......................................................10-62 10.19 PIP/PIO AC Electrical Specifications ...................................................10-64 xxiv Title Section 10 Electrical Characteristics MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... Direct Target Development .................................................................. B-10 C.1 Signaling System #7 Controller ..............................................................C-1 C.1.1 Performance............................................................................................C-2 C.2 Multiple GCI Controller ............................................................................C-3 C.2.1 Typical Application ..................................................................................C-3 C.2.2 MGCI Controller Key Features ................................................................C-3 C.2.3 Performance............................................................................................C-4 C.3 ATOM1/ATM Controller...........................................................................C-4 C.3.1 Key Features ...........................................................................................C-4 C.3.2 Performance............................................................................................C-5 MOTOROLA Title Section 11 Appendix A Serial Performance Appendix B Appendix C RISC Microcode from RAM MC68360 USER’S MANUAL Table of Contents Page Number xxv ...
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... QUICC Architecture Overview ................................................................ D-2 D.2.1 CPU32+ Core.......................................................................................... D-3 D.2.2 System Integration Module (SIM60) ....................................................... D-4 D.2.3 Communications Processor Module (CPM)............................................ D-4 4.2.3.1 QUICC32 Serial Configurations .............................................................. D-5 D.2.4 The QMC Microcode............................................................................... D-7 D.2.5 Data Flow................................................................................................ D-8 D.2.6 Data Management .................................................................................. D-8 D.2.7 Performance ........................................................................................... D-9 D.2.8 Development Support ........................................................................... D-10 D.2.9 Ordering Information ............................................................................. D-10 xxvi Title Appendix D MC68MH360 Product Brief MC68360 USER’S MANUAL Page Number MOTOROLA ...
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... CPU32RM/AD, M68300 Family CPU32 Reference Manual, also provides information on the CPU32. 1.1 QUICC KEY FEATURES The following list summarizes the key MC68360 QUICC features: • CPU32+ Processor (4.5 MIPS at 25 MHz) —32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32) —Background Debug Mode — ...
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... Continuous Mode Transmission and Reception on All Serial Channels —2.5 Kbytes of Dual-Port RAM —14 Serial DMA (SDMA) Channels —Three Parallel I/O Registers with Open-Drain Capability —Each Serial Channel Can Have Its Own Pins (NMSI Mode) • Four Baud Rate Generators 1-2 MC68360 USER’S MANUAL MOTOROLA ...
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... Independent Transmit and Receive Routing, Frame Syncs, Clocking —Allows Dynamic Changes —Can Be internally Connected to Six Serial Channels (Four SCCs and Two SMCs) 1. SDLC is a trademark of International Business Machines. 2. AppleTalk is a registered trademark of Apple Computer, Inc. 3. DDCMP is a trademark of Digital Equipment Corporation. MOTOROLA MC68360 USER’S MANUAL Introduction 1-3 ...
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... IMB definition always included an option for an on-chip 32-bit bus, the QUICC is the first device to implement this option. The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM. Each module utilizes the 32-bit IMB. The MC68360 QUICC block diagram is shown in Figure 1-1. CPU32+ ...
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... System Integration Module (SIM60) The SIM60 integrates general-purpose features that would be useful in almost any 32-bit processor system. The term “SIM60” is derived from the QUICC part number, MC68360. The SIM60 is an enhanced version of the SIM40 that exists on the MC68340 and MC68330 devices ...
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... Although the features of the SIM60 do not exactly correspond to those of the MC68302 SIM, they are very similar. The QUICC SIM60 combines the best MC68302 SIM features with the best MC68340 SIM features for improved performance. 1-6 MC68360 USER’S MANUAL MOTOROLA ...
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... Although the registers used to initialize the QUICC CPM are new (for example, the SCM on the MC68302 is replaced with the GSMR and PSMR on the QUICC), most registers retain their original purpose such as the SCC event, SCC mask, SCC status, and com- MOTOROLA MC68360 USER’S MANUAL Introduction 1-7 ...
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... EPROM, and supports two DRAM SIMMs. Depending on the capacitance on the system bus, external buffers may be required. From a logic standpoint, however, a glueless system is maintained. 1-8 CS0 OE WE0 DATA ADDRESS RAS1 R/W MC68360 USER’S MANUAL 8-BIT BOOT EPROM (FLASH OR REGULAR) CE (ENABLE) OE (OUTPUT ENABLE) WE (WRITE) DATA ADDRESS 16- OR 32-BIT DRAM SIMM ...
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... This functionality is implemented in the MC68160 enhanced Ethernet serial transceiver (EEST MOTOROLA CS0 OE WE0 CS7 RAS1 BUFFER R/W MC68360 USER’S MANUAL Introduction 8-BIT BOOT EPROM (FLASH OR REGULAR) CE (ENABLE) OE (OUTPUT ENABLE) WE (WRITE) DATA ADDRESS 8-, 16-, OR 32-BIT SRAM ...
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... EEST QUICC MC68160 SCC1 EEST QUICC MC68160 SCC1 EEST QUICC RS422 SCC XCVR QUICC RS422 SCC XCVR MC68302 MC68195 LA RS422 SCC XCVR NOTE: The QUICC implements the AppleTalk LAN protocol without the need for the MC68195. MC68360 USER’S MANUAL MOTOROLA ...
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... HDLC bus—any node can obtain mastership. 2. The QUICC handles collisions without external glue. Figure 1-6. HDLC Bus LAN QUICC SCC QUICC SCC SDLC BUS MC68302 SCC NOTE: No collisions are allowed in this master-slave approach. Also available on the MC68302. MC68360 USER’S MANUAL Introduction 1-11 ...
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... SCC UART MC68302 SCC NOTES: 1. Simple LAN based on UART mode. 2. Ninth bit is an "address" bit. QUICC SPI MASTER/SLAVE QUICC SPI SPI BUS MASTER/SLAVE QUICC SPI MASTER/SLAVE NOTE: SPI bus configuration—each QUICC can be the master in turn. MC68360 USER’S MANUAL MOTOROLA ...
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... NOTE: The QUICC can communicate over a Centronics Interface. Figure 1-12. Centronics Interface Implementation MOTOROLA SPI BUS SCP MASTER SPI BUS SPI SPI SLAVE MASTER SPI SLAVE CENTRONICS INTERFACE PIP 8 DATA LINES MC68360 USER’S MANUAL Introduction QUICC SPI SLAVE EEPROMS ETC. SPI SLAVE QUICC EEPROMS ETC. HOST COMPUTER OR PRINTER 1-13 ...
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... Figure 1-16 shows other point-to-point options that are possible with the QUICC and the MC68302. 1-14 PARALLEL INTERFACE PIP PIP 8 DATA LINES HDLC/SDLC BISYNC UART TRANSPARENT SCC SCC HDLC/SDLC BISYNC UART TRANSPARENT SYNCHRONOUS UART SS#7 SCC SCC MC68360 USER’S MANUAL QUICC MC68302 QUICC MOTOROLA ...
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... SMC UART TRANSPARENT SMC TRANSPARENT SMC UART TRANSPARENT QUICC TIME TIME DIVISION MULTIPLEXED BUS SLOT ASSIGNER T1, CEPT, IDL, GCI, ISDN, PRIMARY RATE, USER-DEFINED AND SMCs MAY BE and syncs are supported. MC68360 USER’S MANUAL Introduction MC68302 SCC MC68302 SCP QUICC SMC 1-15 ...
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... AND SMCs MAY BE CONNECTED TO ANY TDM. with the time slot assigner. QUICC SCC SCC TIME SCC SLOT SCC ASSIGNER SMC SMC QUICC SCC SCC TIME SCC SLOT SCC ASSIGNER SMC SMC MC68360 USER’S MANUAL TDM BUS 1 TDM BUS 2 TDM BUS MOTOROLA ...
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... TRANSCEIVER ASSIGNER SCC4 SMC2 SMC1 QUICC SYSTEM BUS QUICC MASTER CPU32+ SCC SCC SCC SCC SMC SMC SPI MC68360 USER’S MANUAL Introduction ETHERNET SIA APPLE TALK RS-422 X.25 (HDLC) T1 LINE FRAME RELAY (HDLC) RS-232 TRANSPARENT DATA RS-232 QUICC SLAVE CPU32+ SCC ...
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... When slave mode, the QUICC can also be interfaced to any MC68030-type bus master instead of the MC68EC040. MC68EC040 Figure 1-22. MC68040 Companion Mode 1-18 MC68EC040 SUPPORT FUNCTIONS SYSTEM BUS CONTROL MEMORY CONTROLLER EPROM DRAM ADDRESS MUXs SRAM MC68360 USER’S MANUAL QUICC SLAVE CPU32+ SCC SCC SCC SCC SMC SMC SPI MOTOROLA ...
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... WE1—Corresponds to A30 and selects data bits 23–16. Also may be referred to as UM- WE. WE2—Corresponds to A29 and selects data bits 15–8. Also may be referred to as LMWE. WE3—Corresponds to A28 and selects data bits 7–0. Also may be referred to as LLWE. MOTOROLA Thi d MC68360 USER’S MANUAL ith 2-1 ...
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... L1RSYNCB/CD3/PC9 SDACK1/L1TSYNCA/CTS4/PC10 L1RSYNCA/CD4/PC11 Figure 2-1. QUICC Functional Signal Groups 2-2 NOTE PORT A PORT B (PIP) QUICC MC68360 240 PINS MC68360 USER’S MANUAL ADDRESS BUS A27–A0 A31–A28/WE3–WE0 FC2–FC0/TM2–TM0 FC3/TT0 DATA BUS D31–D16 D15–D0 PRTY1–PRTY0/IOUT1–IOUT2 PRTY2/IOUT0/RQOUT ...
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... DRAM accesses if internal multiplexing is not used (O). Provides external interrupt requests to the CPU32+ at prior- IRQ7–IRQ1 ity levels 7–1. (I) Autovector request during an interrupt acknowledge cycle AVEC/IACK5 (open-drain I/O) or interrupt level 5 acknowledge line (O). MC68360 USER’S MANUAL Signal Descriptions Function 2-3 ...
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... Special ground for fast AC timing on certain system bus sig- GNDS1 nals. Special ground for fast AC timing on certain system bus sig- GNDS2 nals. VCC, GND Power supply and return to the QUICC. NC4–NC1 Four no-connect pins. MC68360 USER’S MANUAL Function MOTOROLA ...
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... Address Space Reserved (Motorola User Data Space User Program Space Reserved (User Reserved (Motorola Supervisor Data Space Supervisor Program Space Supervisor CPU Space DMA Space NOTE MC68360 USER’S MANUAL Signal Descriptions 2-5 ...
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... RAS2DD pin to increase the RAS2 line drive capability. 2.1.5.2 CHIP SELECT/ROW ADDRESS SELECT/INTERRUPT ACKNOWLEDGE (CS7/ RAS7/IACK7). This pin can be programmed as a CS7/RAS7 pin or as the IACK7 line. See Section 6 System Integration Module (SIM60) for more information on this selection. 2-6 NOTE MC68360 USER’S MANUAL chip- MOTOROLA ...
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... IRQ6–IRQ1 are internally maskable interrupts. Refer to Section 5 CPU32+ for more infor- mation on the interrupt request lines. 2.1.7 Bus Control Signals These signals control the bus transfer operations of the QUICC. Refer to Section 4 Bus Operation for more information on these signals. MOTOROLA – ) IRQ7 IRQ1 MC68360 USER’S MANUAL Signal Descriptions 2-7 ...
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... Complete cycle—data bus port size is 8 bits. 1 (Negated) Complete cycle—data bus port size is 16 bits. 0 (Asserted) Complete cycle—data bus port size is 32 bits. Table 2-4. SIZx Encoding SIZ1 SIZ0 Transfer Size 0 1 Byte 1 0 Word Bytes 0 0 Long Word MC68360 USER’S MANUAL Result MOTOROLA ...
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... BUS CLEAR OUT/INITIAL CONFIGURATION/ROW ADDRESS SELECT DOUBLE-DRIVE (BCLRO/CONFIG1/RAS2DD). This pin can be programmed as the bus clear out output or as the initial configuration pin 1 input signal during system reset or as the RAS2DD output double-drive signal. MOTOROLA NOTE MC68360 USER’S MANUAL Signal Descriptions 2-9 ...
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... These signals are used by the QUICC for controlling or generating the system clocks. Refer to Section 6 System Integration Module (SIM60) for more information on these clock signals. 2.1.10.1 SYSTEM CLOCK OUTPUTS (CLKO2–CLKO1). These output signals reflect the general system clock and are used as the bus timing reference by external devices. CLKO1 2-10 MC68360 USER’S MANUAL MOTOROLA ...
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... CPU32+. Additionally, this MOTOROLA Multi. Factor EXTAL Freq. ( (examples) Reserved Reserved No 1 >10 MHz 401 4.192 MHz No 401 32.768 kHz MC68360 USER’S MANUAL Signal Descriptions CLKIN to the Initial Freq. PLL (VCO/2) Reserved Reserved =EXTAL =EXTAL 32.75 kHz 13.14 MHz 32.768 kHz 13.14 MHz active- 2-11 ...
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... After reset, these pins may be programmed to their other function. The CONFIG2–CONFIG0 lines have internal pullup resistors so that if they are left floating, the default selection will be 111. See Section 6 System Integration Module (SIM60) for more information. 2-12 MC68360 USER’S MANUAL MOTOROLA ...
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... MC68040 companion mode; global CS 32-bit size; MBAR at $003FF00 input, BG output. 0 CPU enabled; global CS 32-bit size; MBAR at $003FF00. 1 CPU enabled; global CS 16-bit size; MBAR at $003FF00. 0 Slave mode; global CS disabled; MBAR at $003FF04. 1 CPU enabled; global CS 8-bit size; MBAR at $003FF00. (Default) NOTE MC68360 USER’S MANUAL Signal Descriptions Result 2-13 ...
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... Provides an MBAR access enable (I), or the initial QUICC con- CONFIG2 figuration select. (I) IRQ6,4,1/ Provides an interrupt request to the QUICC interrupt controller IOUT2–IOUT0/ (I), or interrupt output signals (O) (either RQOUT as a single re- IRQOUT quest or IOUT2–IOUT0 encoded). MC68360 USER’S MANUAL Slave Mode Function MOTOROLA ...
Page 63
... Input clocks to the SCCs, SMCs, SI, and the baud rate generators. (I) An acknowledgement (output) by the IDMA that an IDMA transfer is in progress. (O) of data. (I/O) Time reference input to the timer that allows it to function as a counter. (I) MC68360 USER’S MANUAL Signal Descriptions Slave Mode Function Function 2-15 ...
Page 64
... PIP Data I/O Pins This input causes the PIP output data to be placed on the PIP data STRBO pins. This input causes data on the PIP data pins to be latched by the PIP STRBI as input data. Ethernet receive frame. MC68360 USER’S MANUAL Function MOTOROLA ...
Page 65
... Signal Descriptions 2-17 MC68360 USER’S MANUAL MOTOROLA ...
Page 66
... Signal Descriptions 2-18 MC68360 USER’S MANUAL MOTOROLA ...
Page 67
... The 8-Kbyte block is divided into two 4-Kbyte sections. The RAM occupies the first section; the internal registers occupy the second section. The location of the QUICC registers is shown in Figure 3-1. MOTOROLA Thi d MC68360 USER’S MANUAL ith 3-1 ...
Page 68
... It may be partitioned in several ways, allowing programmable partition sizes to fit the system requirements. This is described in Section 7 Communication Processor Mod- ule (CPM). 3-2 DPRBASE (DUAL-PORT RAM BASE) DUAL-PORT RAM REGB (REGISTER BASE) = DPRBASE + 4K INTERNAL REGISTERS Figure 3-1. QUICC Memory Map NOTE MC68360 USER’S MANUAL MBAR (SIM) MOTOROLA ...
Page 69
... DPRBASE + $D00 SPI Base DPRBASE + $D80 Timer Base DPRBASE + $DB0 SCC3 Base DPRBASE + $E00 IDMA1 Base DPRBASE + $E70 MC68360 USER’S MANUAL QUICC Memory Map Description User Data / BDs / Microcode Program User Data / BDs User Data / BDs / Microcode Scratch User Data / BDs ...
Page 70
... Bold letters mark registers that are restricted to supervisor ac- cess. 3.3.1 SIM Registers Memory Map Table 3-3 lists the SIM registers memory map. 3-4 SMC1 Base DPRBASE + $E80 SCC4 Base DPRBASE + $F00 IDMA2 Base DPRBASE + $F70 SMC2 Base DPRBASE + $F80 NOTES MC68360 USER’S MANUAL MOTOROLA ...
Page 71
... Breakpoint Control Register Reserved Global Memory Register Memory Controller Status Register Reserved Base Register 0 Option Register 0 Reserved Base Register 1 Option Register 1 Reserved Base Register 2 Option Register 2 MC68360 USER’S MANUAL QUICC Memory Map Reset Value Block 0000 7cff H SIM 00 H H/S f(MODCK1) H f(MODCK1–0) ...
Page 72
... Description Reserved Channel Configuration Register Reserved IDMA1 Mode Register Reserved IDMA1 Source Address Pointer IDMA1 Destination Address Pointer IDMA1 Byte Count Register 8 IDMA1 Function Code Register MC68360 USER’S MANUAL 0000 0050 H F000 000x H 0000 0050 H F000 000x H 0000 0050 H F000 000x ...
Page 73
... Port A Open Drain Register Port A Data Register Reserved Port C Data Direction Register Port C Pin Assignment Register Port C Special Options Port C Data Register Port C Interrupt Control Register Reserved Timer Global Configuration Register MC68360 USER’S MANUAL QUICC Memory Map SDMA 0000 H XXXX XXXX IDMA2 ...
Page 74
... Reserved BRG1 Configuration Register BRG2 Configuration Register BRG3 Configuration Register BRG4 Configuration Register SCC1 General Mode Register SCC1 General Mode Register SCC1 Protocol-Specific Mode Register 0000 SCC1 Transmit on Demand MC68360 USER’S MANUAL 0000 0000 FFFF FFFF 0000 0000 0000 0000 ...
Page 75
... SCC4 Data Sync. Register SCC4 Event Register SCC4 Mask Register 8 SCC4 Status Register Reserved SMC1 Mode Register 8 SMC1 Event Register 8 SMC1 Mask Register Reserved MC68360 USER’S MANUAL QUICC Memory Map 7E7E 0000 0000 00 0000 0000 SCC2 0000 0000 0000 7E7E 0000 ...
Page 76
... Port B Pin Assignment Register Port B Open Drain Register Port B Data Register Reserved SI Mode Register 8 SI Global Mode Register 8 SI Status Register 8 SI Command Register Reserved SI Clock Route SI RAM Pointers Reserved MC68360 USER’S MANUAL 0000 SMC2 00 00 0000 H SPI 0000 H PIP 0000 ...
Page 77
... The user should be aware that misalignment of word or long- word operands can cause the CPU32+ to perform multiple bus cycles for operand transfers; therefore, processor performance is optimized if word and long-word memory operands are MOTOROLA Thi d NOTE MC68360 USER’S MANUAL ith 4-1 ...
Page 78
... In addition to meeting input setup and hold times for deterministic operation, all input signals must obey the protocols described in this sec- tion. CLK EXT Figure 4-1. Input Sample Window 4 SAMPLE WINDOW MC68360 USER’S MANUAL su MOTOROLA ...
Page 79
... Address Spaces Reserved (Motorola User Data Space User Program Space Reserved (User Reserved (Motorola Supervisor Data Space Supervisor Program Space Supervisor CPU Space DMA space MC68360 USER’S MANUAL Bus Operation 4-3 ...
Page 80
... The lower middle write enable (WE2) indicates that the lower middle eight bits of the data bus (D15–D8) contain valid data during a write cycle. The lower write enable (WE3) indicates that the lower eight bits of the data bus contain valid data during a write cycle. 4-4 MC68360 USER’S MANUAL MOTOROLA ...
Page 81
... BUS ERROR (BERR). This signal is also a bus cycle termination indicator and can be used in the absence of DSACKx to indicate a bus error condition. BERR can also be asserted in conjunction with DSACKx to indicate a bus error condition, provided it meets the MOTOROLA NOTE MC68360 USER’S MANUAL Bus Operation 4-5 ...
Page 82
... The addressed device uses the DSACKx signals to indicate 4-6 Table 4-2. DSACKx Encoding DSACK0 Result 1 Insert Wait States in Current Bus Cycle 0 Complete Cycle—Data Bus Port Size is 8 Bits 1 Complete Cycle—Data Bus Port Size is 16 Bits 0 Complete Cycle—Data Bus Port Size is 32 Bits MC68360 USER’S MANUAL MOTOROLA ...
Page 83
... The same is true for any of the operand bytes. The positioning of bytes is determined by the size and address outputs. MOTOROLA 0P0 0P1 0P2 15 WORD OPERAND 0P2 BYTE OPERAND MC68360 USER’S MANUAL Bus Operation 0 0P3 0 0P3 7 0 0P3 4-7 ...
Page 84
... D23–D16 D15–D8 BYTE 1 BYTE 2 BYTE 1 16-BIT PORT BYTE 3 8-BIT PORT Table 4-3. SIZx Encoding SIZ1 SIZ0 Size 0 1 Byte 1 0 Word Bytes 0 0 Long Word MC68360 USER’S MANUAL 0P3 3 INTERNAL TO THE MC68360 D7–D0 EXTERNAL BUS BYTE 3 32-BIT PORT MOTOROLA ...
Page 85
... OP1 OP0 OP1 OP2 OP3 x OP0 OP1 OP2 x x OP0 OP1 OP0 MC68360 USER’S MANUAL Bus Operation Offset Byte Port Word Port External External Data Data Bytes Required Bytes Required D31:D24 OP3 x OP3 x OP3 OP3 OP3 x OP3 x OP3 ...
Page 86
... OP0 OP0 OP0 LONG-WORD OPERAND 0P1 0P2 D16 MC68360 A1 LSB SIZ1 SIZ0 0P1 0P3 MC68360 USER’S MANUAL D23:D16 D15:D8 D7: OP3 OP3 x OP3 x OP3 OP3 x x OP2 OP3 x OP3 OP2 OP3 OP2 x OP2 OP2 ...
Page 87
... PC relative data addresses), some performance degradation occurs when additional bus cycles are required for long-word or word operands MOTOROLA 0P0 0P1 WORD WRITE LONG-WORD OPERAND WRITE TO 16-BIT PORT MC68360 USER’S MANUAL Bus Operation S2 S4 0P2 0P3 WORD WRITE 4-11 ...
Page 88
... Attempting to prefetch an instruction word at an odd address causes an address error exception. 15 WORD OPERAND 0P2 D31 DATA BUS BYTE MEMORY 0P2 0P3 Figure 4-6. Example of Word Transfer to Byte Port 4-12 0 0P3 D24 MC68360 SIZ1 SIZ0 MC68360 USER’S MANUAL MEMORY CONTROL A0 DSACK1 DSACK0 MOTOROLA ...
Page 89
... The address offset (A2–A0) is now 100; the port latches the final byte, and the operation is complete. Figure 4-9 shows the associated bus transfer signal timing. MOTOROLA OP2 OP3 OP2 OP3 BYTE WRITE WORD OPERAND WRITE MC68360 USER’S MANUAL Bus Operation S2 S4 OP3 OP3 OP3 OP3 BYTE WRITE 4-13 ...
Page 90
... OP3 Figure 4-8. Misaligned Long-Word Transfer to Word Port Example 4-14 LONG-WORD OPERAND 0P1 0P2 D16 MC68360 LSB SIZ1 SIZ0 A2 A1 0P0 0P2 XXX MC68360 USER’S MANUAL 0 0P3 MEMORY CONTROL DSACK1 DSACK0 MOTOROLA ...
Page 91
... MOTOROLA 0P0 0P1 0P0 0P2 0P1 0P1 0P2 0P2 WORD WRITE LONG-WORD OPERAND WRITE MC68360 USER’S MANUAL Bus Operation 0P3 0P3 0P3 0P3 BYTE WRITE 4-15 ...
Page 92
... WORD OPERAND 15 OP2 D31 DATA BUS WORD MEMORY MSB XXX 0P3 Figure 4-10. Misaligned Word Transfer to Word Port Example 4-16 0 OP3 D16 MC68360 LSB SIZ1 SIZ0 0P2 XXX MC68360 USER’S MANUAL MEMORY CONTROL DSACK1 DSACK0 MOTOROLA ...
Page 93
... The second bus cycle then consists of a three-byte access to a long-word boundary. Since the memory is long-word organized, no further bus cycles are necessary. MOTOROLA 0P2 0P2 0P3 0P2 WORD WRITE WORD OPERAND WRITE TO A1/ MC68360 USER’S MANUAL Bus Operation S4 S2 0P3 0P3 0P3 0P3 BYTE WRITE 4-17 ...
Page 94
... LONG-WORD MEMORY MSB UMB XXX XXX 0P1 0P2 Figure 4-12. Misaligned Long-Word Transfer to Long-Word Port Example 4-18 0 0P2 0P3 D0 LMB LSB SIZ1 SIZ0 0P0 0P0 0 0P3 XXX 1 MC68360 USER’S MANUAL MC68EC030 MEMORY CONTROL DSACK1 DSACK0 MOTOROLA ...
Page 95
... MOTOROLA 0P0 0P0 0P1 0P0 BYTE WRITE LONG-WORD OPERAND WRITE MC68360 USER’S MANUAL Bus Operation S2 S4 0P1 0P2 0P3 0P1 3-BYTE WRITE 4-19 ...
Page 96
... DSACKx, the QUICC inserts wait cycles in clock-period incre- ments until DSACKx is recognized. BERR and/or HALT can be asserted after DSACKx is asserted. BERR and/or HALT must be asserted within the time specified after DSACKx is 4-20 on Write Bus Cycles Number of Bus Cycles 1:2:4 N/A N/A 1:1:1 1:1:1 1:1:1 1:1:2 1:2:2 1:1:2 1:2:4 2:3:4 2:2:4 MC68360 USER’S MANUAL 11 N/A 1:1:1 2:2:2 2:3:4 MOTOROLA ...
Page 97
... S4. Figure 4-14 shows the DSACKx timing for a read with two wait states, followed by a fast termination read and write. MOTOROLA MC68360 USER’S MANUAL Bus Operation 4-21 ...
Page 98
... Bus operations are described in terms of external bus states. 4- TWO WAIT STATES IN READ FAST TERMINATION READ NOTES MC68360 USER’S MANUAL FAST TERMINATION WRITE MOTOROLA ...
Page 99
... REMOVE DATA FROM D31–D0 2) NEGATE DSACKx EXTERNAL DEVICE 1) DECODE ADDRESS 2) PLACE DATA ON D31–D24, OR D23–16, OR D15–D8, OR D7–D0. 3) ASSERT DSACKx TERMINATE CYCLE 1) REMOVE DATA FROM D31–D0 2) NEGATE DSACKx MC68360 USER’S MANUAL Bus Operation SLAVE PRESENT DATA 4-23 ...
Page 100
... WORD SIZ0 R DSACK1 DSACK0 D31–D24 D23–D16 D15–D8 D7–D0 WORD READ Figure 4-17. Byte and Word Read Cycles—32-Bit Port Timing 4- BYTE 0P2 0P3 0P3 BYTE READ MC68360 USER’S MANUAL 0P3 BYTE READ MOTOROLA ...
Page 101
... The QUICC drives R/W high for a read cycle. SIZ1 and SIZ0 become valid, indicating the number of bytes requested for transfer. MOTOROLA WORD 0P2 0P0 0P3 0P1 WORD READ MC68360 USER’S MANUAL Bus Operation LONG WORD 0P0 0P1 0P2 0P3 LONG-WORD READ FROM 32-BIT PORT 4-25 ...
Page 102
... NEGATE AS AND DS AND WEx 2) REMOVE DATA FROM D31–D0 START NEXT CYCLE Figure 4-19. Write Cycle Flowchart 4-26 EXTERNAL DEVICE PRESENT DATA 1) DECODE ADDRESS 2) PLACE DATA ON D31–D0 3) ASSERT DATA TRANSFER AND SIZE ACKNOWLEDGE (DSACKx) TERMINATE CYCLE 1) NEGATE DSACKx MC68360 USER’S MANUAL MOTOROLA ...
Page 103
... WE3) are asserted simultaneously with AS. State 2—During S2, the QUICC places the data to be written onto D31–D0 and samples DSACKx at the end of S2. MOTOROLA WRITE WRITE MC68360 USER’S MANUAL Bus Operation READ WITH WAIT STATES 4-27 ...
Page 104
... QUICC asserts RMC to indicate that an indivisible operation is occurring. The QUICC does not issue a bus grant (BG) signal in response to a bus request (BR) signal during this operation. Figure 4- example of a functional timing diagram of a read-modify-write instruction specified in terms of clock periods. 4-28 MC68360 USER’S MANUAL MOTOROLA ...
Page 105
... If DSACKx is not recognized by the start of S3, the QUICC inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchro- MOTOROLA READ INDIVISIBLE CYCLE MC68360 USER’S MANUAL Bus Operation WRITE 4-29 ...
Page 106
... S5. If more than one write cycle is required, S0–S5 are repeated for each write cycle. The external device keeps DSACKx asserted until it detects the negation (whichever it detects first). The device must remove its data and 4-30 MC68360 USER’S MANUAL MOTOROLA ...
Page 107
... CPU SPACE TYPE FIELD MC68360 USER’S MANUAL Bus Operation 0 BKPT LEVEL ...
Page 108
... BKAR and BKCR discussion in Section 6 System Integration Module (SIM60) for details). The breakpoint operation flowchart is shown in Figure 4-23. Figure 4-24 and Figure 4-25 show the timing diagrams for the breakpoint acknowledge cycle with instruction opcodes supplied on the cycle and with an exception signaled, respectively. 4-32 NOTE MC68360 USER’S MANUAL MOTOROLA ...
Page 109
... Figure 4-23. Breakpoint Operation Flowchart MOTOROLA IF BREAKPOINT INSTRUCTION EXECUTED: 1) PLACE REPLACEMENT OPCODE ON DATA BUS 2) ASSERT DSACKx 1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING IF BKPT PIN ASSERTED: 1) ASSERT DSACKx 1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING (B) 1) NEGATE DSACKx or BERR MC68360 USER’S MANUAL Bus Operation EXTERNAL DEVICE -OR- -OR- 4-33 ...
Page 110
... BERR HALT BKPT BREAKPOINT OCCURS Figure 4-24. Breakpoint Acknowledge Cycle Timing (Opcode Returned) 4- BREAKPOINT ENCODING (0000) BREAKPOINT NUMBER/T-BIT READ INSTRUCTION WORD FETCH MC68360 USER’S MANUAL CPU SPACE FETCHED INSTRUCTION EXECUTION BREAKPOINT ACKNOWLEDGE MOTOROLA ...
Page 111
... The external bus interface must get a copy of the interrupt mask level from the CPU32+, MOTOROLA BREAKPOINT ENCODING (0000) BREAKPOINT NUMBER/T-BIT READ MC68360 USER’S MANUAL Bus Operation CPU SPACE EXCEPTION STACKING BREAKPOINT ACKNOWLEDGE ...
Page 112
... The following paragraphs describe the interrupt acknowledge cycle for these devices. Other interrupting conditions or devices cannot supply a vector number and use the autovector cycle described in 4.4.4.2 Autovector Interrupt Acknowledge Cycle. 4- — MC68360 USER’S MANUAL MOTOROLA 0 I0 ...
Page 113
... TYPE FIELD (A19–A16 SET R/W TO READ 6) SET FC3–FC0 TO 0111 7) DRIVE SIZx PINS TO INDICATE A ONE-BYTE TRANSFER 8) NEGATE BCLRO. 9) ASSERT AS, DS, AND OE ACQUIRE VECTOR NUMBER 1) LATCH VECTOR NUMBER 2) NEGATE AS, DS, AND OE START NEXT CYCLE MC68360 USER’S MANUAL Bus Operation QUICC GRANT INTERRUPT 4-37 ...
Page 114
... AVEC to terminate the cycle. The DSACKx signals may not be asserted 4- 0–2 CLOCKS INTERRUPT LEVEL CPU SPACE 1 BYTE VECTOR FROM 16-BIT PORT VECTOR FROM 8-BIT PORT INTERNAL ARBITRATION IACK CYCLE MC68360 USER’S MANUAL WRITE STACK MOTOROLA ...
Page 115
... AVEC pin will not be asserted externally). Seven distinct autovectors can be used, corresponding to the seven levels of interrupt available with signals IRQ7–IRQ1. Figure 4-28 shows the timing for an autovector operation. MOTOROLA MC68360 USER’S MANUAL Bus Operation 4-39 ...
Page 116
... When no internal module (including the SIM60, which responds for external requests) responds during an interrupt acknowledge cycle by arbitrating for the 4- 0–2 CLOCKS* INTERRUPT LEVEL CPU SPACE 1 BYTE INTERNAL ARBITRATION IACK CYCLE MC68360 USER’S MANUAL WRITE STACK MOTOROLA ...
Page 117
... To ensure predictable operation, BERR and HALT should be negated according to the specifications in Section 10 Electrical Characteristics. DSACKx, BERR, and HALT may be negated after AS. If DSACKx or BERR remain asserted into S2 of the next bus cycle, that cycle may be terminated prematurely. MOTOROLA MC68360 USER’S MANUAL Bus Operation 4-41 ...
Page 118
... Normal cycle terminate and halt; continue when HALT negated Terminate and take bus error exception, possibly deferred Terminate and take bus error exception, possibly deferred Terminate and retry when HALT negated Terminate and retry when HALT negated. A MC68360 USER’S MANUAL Result MOTOROLA ...
Page 119
... Exceptions are taken in both cases. (Refer to Section 5 CPU32+ for details of bus error exception processing CLKO1 A31–A0 FC3–FC0 R DSACKx D31–D0 BERR READ CYCLE WITH BUS Figure 4-29. Bus Error without DSACKx MOTOROLA INTERNAL ERROR PROCESSING MC68360 USER’S MANUAL Bus Operation STACK WRITE 4-43 ...
Page 120
... After a synchronization delay, the QUICC retries the previous cycle using the same access information (address, function code, size, etc.). BERR should be negated before S2 of the retried cycle to ensure correct operation of the retried cycle. 4- WRITE INTERNAL CYCLE PROCESSING MC68360 USER’S MANUAL S2 S4 STACK WRITE MOTOROLA ...
Page 121
... When the relinquish and retry is asserted during an internal mas- ter's word access to an 8-bit port, and the external master that takes the bus performs an external-to-internal bus cycle, the en- MOTOROLA DATA IGNORED HALT RETRY Figure 4-31. Retry Sequence NOTE MC68360 USER’S MANUAL Bus Operation READ RERUN 4-45 ...
Page 122
... The single-step operation and the software trace capability allow the system debugger to trace single bus cycles, sin- gle instructions, or changes in program flow. 4- WRITE HALT CYCLE MC68360 USER’S MANUAL S2 S4 WRITE RERUN MOTOROLA ...
Page 123
... This is due to a pipelining characteristic of the QUICC coupled with the HALT signal being asserted late into an internal-to-external bus cycle. Note that show cycles mode is not the normal configura- tion for the QUICC. MOTOROLA NOTES MC68360 USER’S MANUAL Bus Operation 4-47 ...
Page 124
... QUICC. However, bus arbitration can still occur (refer to 4.6 Bus Arbitration). A second bus error or address error that occurs after exception processing has 4- READ HALT (ARBITRATION PERMITTED WHILE THE PROCESSOR IS HALTED) Figure 4-33. HALT Timing MC68360 USER’S MANUAL READ MOTOROLA ...
Page 125
... BGACK and maintains BGACK during the entire bus cycle (or cycles) for which it is bus master. The following conditions must be met for an external device to assume mastership of the bus through the normal bus arbitration procedure: it must have MOTOROLA NOTE MC68360 USER’S MANUAL Bus Operation 4-49 ...
Page 126
... NEXT BUS MASTER WAITS FOR BGACK TO BE NEGATED 3) NEXT BUS MASTER ASSERTS BGACK TO BECOME NEW MASTER 4) BUS MASTER NEGATES BR OPERATE AS BUS MASTER 1) PERFORM DATA TRANSFERS (READ AND WRITE CYCLES) ACCORDING TO THE SAME RULES THE PROCESSOR USES RELEASE BUS MASTERSHIP 1) NEGATE BGACK MC68360 USER’S MANUAL MOTOROLA ...
Page 127
... CLKO1 A31–A0 D31– DSACK1–DSACK0 BR BG BGACK NOTE: BR has synchronous timing. BR has asynchronous timing. Figure 4-35. Bus Arbitration Timing Diagram—Idle Bus Case MOTOROLA MC68360 USER’S MANUAL Bus Operation 4-51 ...
Page 128
... BGACK is received while the BR is active, the QUICC remains bus master once BR is negated. This prevents unnecessary interference with ordinary processing if the arbitration circuitry inadvertently responds to noise external device determines that it no longer requires use of the bus before it has been granted mastership. 4- MC68360 USER’S MANUAL MOTOROLA ...
Page 129
... When working in asynchronous mode (ASTM bit in the MCR is cleared) and SHEN0– and one of the QUICC internal masters requests an external accesses, the mini- mum time depends on internal synchronization plus one clock. • If SHEN1–SHEN0 = 1 , another clock is added for internal bus arbitration. MOTOROLA MC68360 USER’S MANUAL Bus Operation 4-53 ...
Page 130
... The QUICC does not allow arbitration of the external bus during the RMC sequence. For the duration of this sequence, the QUICC ignores the BR input. If mastership of the bus is required during an RMC operation, BERR must be used to abort the RMC sequence. 4-54 MC68360 USER’S MANUAL MOTOROLA ...
Page 131
... MOTOROLA + STATE STATE STATE 6 RA G—BUS GRANT T —THREE-STATE SIGNAL TO BUS CONTROL V—BUS AVAILABLE TO BUS CONTROL MC68360 USER’S MANUAL Bus Operation STATE 4-55 ...
Page 132
... EXTERNAL MASTER ACCESS TO DUAL PORT RAM QUICC REQUIRES EXTERNAL BUS HALT IS ASSERTED AND DRAM REFRESH DOES NOT REQUIRE EXTERNAL BUS QUICC OWNS BUS BR NEGATED BGACK ASSERTED QUICC STILL NEEDS BUS MC68360 USER’S MANUAL QUICC WAITING FOR BUS BR ASSERTED MOTOROLA ...
Page 133
... USE OF BUS INTERNAL MASTER (IDMA, SDMA, OR DRAM REFRESH) REQUESTS BUS HALT IS ASSERTED AND DRAM REFRESH DOES NOT REQUIRE EXTERNAL BUS QUICC OWNS BUS BG NEGATED BB ASSERTED QUICC STILL NEEDS BUS MC68360 USER’S MANUAL Bus Operation QUICC WAITING FOR BUS BG NEGATED 4-57 ...
Page 134
... See Figure 4-40 for the slave mode bus arbitration timing diagram. CLKO1 A31–A0 D31– R/W DSACK1-DSACK0 BR (OUT) BG (IN) BGACK (IN/OUT) NOTES: 1. Synchronous arbitration with SHEN1–SHEN0 = 00. 2. Minimum bus idle time. Figure 4-40. Slave Mode Bus Arbitration Timing Diagram 4- MC68360 USER’S MANUAL S5 MOTOROLA ...
Page 135
... QUICC (see 4.3 Data Transfer Cycles). The QUICC supports the interrupt acknowledge cycles presented in 4.4.4 Interrupt Acknowledge Bus Cycles. The QUICC also supports the MC68EC040 read and write accesses and inter- rupt acknowledge cycles (see Figure 4-41–Figure 4-44). MOTOROLA NOTE NOTE NOTE MC68360 USER’S MANUAL Bus Operation 4-59 ...
Page 136
... TM2–TM0 R TBI D31–D0 Figure 4-41. MC68EC040 Internal Registers Read Cycle CLKO1 A31–A0 SIZ1–SIZ0 TT1–TT0 TM2–TT0 R TBI D31–D0 Figure 4-42. MC68EC040 Internal Registers Write Cycle 4- MC68360 USER’S MANUAL CW CW MOTOROLA ...
Page 137
... A31–A0 SIZ1–SIZ0 TT1–TT0 TM2–TM0 R TBI D31–D8 D7–D0 IACK7 IACK1 Figure 4-44. MC68EC040 Interrupt Acknowledge Cycle MOTOROLA INTERRUPT LEVEL INTERNAL ARBITRATION INTERRUPT LEVEL INTERNAL ARBITRATI0N MC68360 USER’S MANUAL Bus Operation VECTOR# 4-61 ...
Page 138
... The external data bus drivers are enabled so that data becomes valid on the external bus as soon available on the internal bus. State 0 – The address, function codes, read/write, and size pins change to begin the next cycle. Data from the preceding cycle is valid through state 0. 4-62 MC68360 USER’S MANUAL MOTOROLA ...
Page 139
... Resetting the QUICC causes any bus cycle in progress to terminate as if DSACKx or BERR had been asserted. In addition, the QUICC appropriately initializes registers for a reset exception. MOTOROLA S0 S0 S41 S42 S43 S1 SHOW CYCLE START OF EXTERNAL CYCLE MC68360 USER’S MANUAL Bus Operation S2 4-63 ...
Page 140
... INTRST Sys Prot Asynchronous INTRST Sys Prot Asynchronous INTRST Clock Asynchronous INTRST CPU32+ Asynchronous INTRST 512 CYCLES T 32 CLKS NOTE MC68360 USER’S MANUAL INTSYSRST CLKRST EXTSYSRST — — EXTRST INTSYSRST CLKRST EXTSYSRST INTSYSRST — EXTSYSRST INTSYSRST CLKRST EXTSYSRST INTSYSRST CLKRST ...
Page 141
... In QUICC slave mode (disable CPU32+) the reset operates the same as in the normal (mas- ter) mode except that the RESET instruction does not exist. MOTOROLA 512 14 CLOCKS CLKOUT ADDRESS AND CONTROL SIGNALS THREE-STATED NOTE MC68360 USER’S MANUAL Bus Operation 4-65 ...
Page 142
... In the case where the CP32+ excutes a RESET command, the QUICC drives RESETS pin. In that case RESETS will be driven from CLOCK low (not CLOCK high as in all other cases). This requires a special AC timing parameter which is spec 58A in 10.9 Bus Operation AC Timing Specifications. 4-66 NOTE MC68360 USER’S MANUAL MOTOROLA ...
Page 143
... PC relative data addresses), some performance degradation occurs when additional bus cycles are required for long-word or word operands that are misaligned. For maximum performance, data items should be MOTOROLA Thi d MC68360 USER’S MANUAL ith 5-1 ...
Page 144
... Additional Addressing Modes —Scaled Index —Address Register Indirect with Base Displacement and Index —Expanded PC Relative Modes —32-Bit Branch Displacements • Instruction Set Additions —High-Precision Multiply and Divide —Trap on Condition Codes —Upper and Lower Bounds Checking 5-2 MC68360 USER’S MANUAL MOTOROLA ...
Page 145
... The termination condition and count are checked after each execution of the data operations of the looped instruction. The CPU32+ automatically exits the loop mode during interrupts or other exceptions. MOTOROLA INSTRUCTION UNIT PREFETCH AND DECODE BUS CONTROL UNIT MC68360 USER’S MANUAL CPU32+ BUS CONTROL 5-3 ...
Page 146
... To support generic handlers, the processor places the vector offset in the exception stack frame. The processor also marks the frame with a frame format. The format 5-4 ONE-WORD INSTRUCTION DBcc DBcc DISPLACEMENT $FFFC = 4 VECTOR BASE REGISTER (VBR) MC68360 USER’S MANUAL 0 MOTOROLA ...
Page 147
... Separate User and Supervisor Stack Pointers (USP and SSP) • Separate User and Supervisor Address Spaces • Separate Program and Data Address Spaces • Many Data Types • Flexible Addressing Modes • Full Interrupt Processing • Expansion Capability MOTOROLA MC68360 USER’S MANUAL CPU32+ 5-5 ...
Page 148
... Figure 5-3. User Programming Model 5 (USP CCR MC68360 USER’S MANUAL DATA REGISTERS ADDRESS REGISTERS USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER MOTOROLA ...
Page 149
... The MOVEC instruction can use registers SFC and DFC to specify the function code of a memory address. MOTOROLA (SSP (CCR VBR SFC DFC MC68360 USER’S MANUAL CPU32+ SUPERVISOR STACK POINTER STATUS REGISTER VECTOR BASE REGISTER ALTERNATE FUNCTION CODE REGISTERS 5-7 ...
Page 150
... However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 core enhancements. 5-8 (CONDITION CODE REGISTER INTERRUPT PRIORITY MASK Figure 5-5. Status Register MC68360 USER’S MANUAL USER BYTE EXTEND NEGATIVE ZERO OVERFLOW CARRY MOTOROLA ...
Page 151
... SWAP Swap Data Register Halves TAS Test and Set Operand TBLS, TBLSN Table Lookup and Interpolate, TBLU, TBLUN Table Lookup and Interpolate, TRAPcc Trap Conditionally (16 Tests) TRAPV Trap on Overflow TST Test UNLK Unlink MC68360 USER’S MANUAL CPU32+ Description Signed Unsigned 5-9 ...
Page 152
... The remaining words, called extension words, further specify the instruction and operands. These words may be imme- diate operands, extensions to the effective address mode specified in the operation word, branch displacements, bit number, special register specifications, trap operands, or argu- ment counts. 5-10 MC68360 USER’S MANUAL MOTOROLA ...
Page 153
... Dym, Dyn Data registers, table interpolation values MOTOROLA A register field of the instruction contains the num- ber of the register. An effective address field of the instruction con- tains address mode information. The definition of an instruction implies the use of specific registers. MC68360 USER’S MANUAL CPU32+ 0 5-11 ...
Page 154
... Status register SSP Supervisor stack pointer USP User stack pointer FC Function code DFC Destination function code register SFC Source function code register Arithmetic addition or postincrement – Arithmetic subtraction or predecrement / Arithmetic division or conjunction symbol Arithmetic multiplication = Equal to 5-12 MC68360 USER’S MANUAL MOTOROLA ...
Page 155
... Integer Arithmetic Binary-Coded Decimal Arithmetic Logic Program Control Shift and Rotate System Control The complete range of instruction capabilities combined with the addressing modes de- scribed previously provide flexibility for program development. All CPU32+ instructions are summarized in Table 5-2. MOTOROLA MC68360 USER’S MANUAL CPU32+ 5-13 ...
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... BGND BKPT # data BRA label Z; BSET Dn, eaÒ BSET # data ea (SP BSR label BTST Dn BTST # data ea CHK ea ,Dn CHK2 ea ,Rn CLR ea cc CMP ea ,Dn CMPA ea ,An CMPI # data ea cc CMPM (Ay)+,(Ax)+ MC68360 USER’S MANUAL Syntax MOTOROLA ...
Page 157
... LINK An,# displacement SP SR External Bus Interface (EBI) LPSTOP # data LSd Destination LSd LSd MOVE ea ea MOVEA ea ,An MOVE CCR, ea MOVE ea ,CCR MOVE SR MOVE ea ,SR MC68360 USER’S MANUAL CPU32+ Syntax 16r:16q 32q 32r:32q 32r:32q 16r:16q 32q 32r:32q 32r:32q 1 Dx, data ,Dy 1 ...
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... Destination Destination Destination Destination Destination Destination CCR SR (SP) Destination Destination SP SP; (SP) PC; SP; SP MC68360 USER’S MANUAL Syntax MOVE USP,An MOVE An,USP MOVEC Rc,Rn MOVEC Rn,Rc MOVEM register list, ea MOVEM ea ,register list MOVEP Dx,(d,Ay) MOVEP (d,Ay),Dx MOVEQ # data ,Dn MOVES Rn, ea MOVES ea ,Rn MULS MULS ...
Page 159
... TBLSN. size ea ,Dx TBLSN. size Dym:Dyn, Dx TBLU. size ea ,Dx TBLU. size Dym:Dyn, Dx TBLUN. size ea ,Dx TBLUN. size Dym:Dyn,Dx (SSP); (SSP); SSP – 2 SSP; TRAP # vector PC TRAPcc TRAPcc.W # data TRAPcc.L TRAPV Condition Codes TST ea An UNLK An MC68360 USER’S MANUAL CPU32+ Syntax data 5-17 ...
Page 160
... – – MC68360 USER’S MANUAL Special Definition (IR < LB > UB > UB) (R < LB ...
Page 161
... Dn [31:24 Immediate Data 32 SP – SP; (SP) MC68360 USER’S MANUAL CPU32+ = Source operand MSB = Destination operand MSB = Result operand MSB = Register tested = Bit Number = Shift count = Lower bound = Upper bound = NOT Rm Operation (SP ...
Page 162
... A set of extended instructions provides multiprecision and mixed-size arithmetic. These instructions are add extended (ADDX), subtract extended (SUBX), sign extend (EXT), and negate binary with extend (NEGX). Refer to Table 5-5 for a summary of the integer arith- metic operations. 5-20 MC68360 USER’S MANUAL MOTOROLA ...
Page 163
... Dyn – Dym Temp 8, 16, 32 (Temp Dn [7:0]) (Dym 256) + Temp Dyn – Dym Temp 8, 16, 32 (Temp Dn [7:0]) / 256 Dym + Temp Dn MC68360 USER’S MANUAL CPU32+ Operation Destination Destination Destination Destination Destination Destination (signed or un- Destination Destination Destination (signed or un- Destination Destination Destination ...
Page 164
... Immediate Data 8, 16, 32 Source Destination 8, 16, 32 Immediate Data 8, 16, 32 Destination Destination 8, 16, 32 Source V Destination 8, 16 16, 32 Immediate Data V Destination 8, 16, 32 Source – set condition codes MC68360 USER’S MANUAL Operation Destination Destination Destination Destination Destination Destination Destination Destination MOTOROLA ...
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... Size X 16 MC68360 USER’S MANUAL CPU32+ Operation 0 X MSW LSW 5-23 ...
Page 166
... Operand Size 8 Source 10 + Destination – Destination 10 – Destination 10 – Source 10 – MC68360 USER’S MANUAL Operation Z bit bit bit of Z instructions support Operation Destination Destination Destination MOTOROLA ...
Page 167
... Returns 16 (SP) PC none (SP) CCR none (SP) PC — LT — MI — NE — PL — T — VC — VS — MC68360 USER’S MANUAL CPU32+ Operation PC PC; PC (SP (SP); destination PC SP SP; (SP) PC Low or same Less than Minus Not equal Plus ...
Page 168
... If V set, then overflow TRAP exception Condition Code Register 8 Immediate Data CCR 8 Immediate Data CCR 16 Source CCR 16 CCR Destination 8 Immediate Data V CCR MC68360 USER’S MANUAL Operation SP; (SP) PC SP; EBI; STOP – (SSP); – (SSP); (vector) PC (SSP); (SSP); (SSP); ...
Page 169
... Overflow Clear 1000 Overflow Set 1001 Plus 1010 Minus 1011 Greater or Equal 1100 Less Than 1101 Greater Than 1110 Less or Equal 1111 MC68360 USER’S MANUAL CPU32+ Test ...
Page 170
... X INDEPENDENT VARIABLE Figure 5-7. Table Example MC68360 USER’S MANUAL X 49152. Table Y-Value 1311 1659 1669 1679 1690 1966 65536 MOTOROLA ...
Page 171
... Since the table is reduced from 257 to 5 entries, independent variable X must be scaled appropriately. In this case the scaling factor is 64, and the scaling is done by a single instruc- tion: LSR.W #6,Dx MOTOROLA 256 512 786 X INDEPENDENT VARIABLE Figure 5-8. Table Example 2 NOTE X-Value 2 512 3 786 MC68360 USER’S MANUAL CPU32+ 1024 Y-Value 1311 1966 5-29 ...
Page 172
... The subroutine uses the data listed in Table 5-15, based on the function shown in Figure 5-9. Y 1024 5- 2048 3072 X INDEPENDENT VARIABLE Figure 5-9. Table Example 3 MC68360 USER’S MANUAL example shows 4096 MOTOROLA 0 0 ...
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... MC68360 USER’S MANUAL CPU32 5- ...
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... TBL # 1 0010 0000 . TBL # 2 0011 1111 . TBL # 3 0000 0001 . 0010 0000 . 0011 1111 . 0000 0001 . 0110 0000 . MC68360 USER’S MANUAL MOTOROLA 0 0 ...
Page 175
... Long addition avoids problems with carry Move radix point Fraction MSB in carry Copy entry number and fraction number Surface interpolation, with round Read just the result No round necessary Half round up MC68360 USER’S MANUAL CPU32+ 5-33 ...
Page 176
... STOP or LPSTOP instruction, execution of instructions can resume when a trace, interrupt, or reset exception occurs. 5.4.2 Privilege Levels To protect system resources, the processor can operate with either of two levels of access— user or supervisor. Supervisor level is more privileged than user level. All instructions are 5-34 MC68360 USER’S MANUAL MOTOROLA ...
Page 177
... The RTE instruction causes a return to a program that was executing when an exception occurred. When RTE is executed, the exception stack frame saved on the supervisor stack can be restored in either of two ways. MOTOROLA MC68360 USER’S MANUAL CPU32+ 5-35 ...
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... Sources of external exception include interrupts, breakpoints, bus errors, and reset requests. Interrupts are peripheral device requests for processor action. Breakpoints are used to support development equipment. Bus error and reset are used for access control and processor restart. 5-36 MC68360 USER’S MANUAL MOTOROLA ...
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... Level 5 Interrupt Autovector 078 SD Level 6 Interrupt Autovector 07C SD Level 7 Interrupt Autovector 080 Trap Instruction Vectors (0–15) SD 0BC — 0C0 (Reserved for Coprocessor) SD 0E8 — (Unassigned, Reserved) 0EC SD 0FC — 100 SD User-Defined Vectors (192) 3FC CAUTION MC68360 USER’S MANUAL CPU32+ Assignment 5-37 ...
Page 180
... See 5.5.4 CPU32+ Stack Frames for a complete discussion of exception stack frames FORMAT Figure 5-10. Exception Stack Frame 5-38 STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW VECTOR OFFSET OTHER PROCESSOR STATE INFORMATION, DEPENDING ON EXCEPTION ( WORDS) MC68360 USER’S MANUAL 0 MOTOROLA ...
Page 181
... Suspends processing (instruction or excep- tion); saves internal context. Exception processing is a part of instruction execution. Exception processing begins before instruc- tion execution. Exception processing begins when current in- struction or previous exception processing is complete. MC68360 USER’S MANUAL CPU32+ Characteristics 5-39 ...
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... Direct assertion of the internal BERR signal by an internal module 3. Direct assertion of the internal BERR signal by the on-chip hardware watchdog after detecting a no-response condition Bus error exception processing begins when the processor attempts to use information from an aborted bus cycle. 5-40 MC68360 USER’S MANUAL MOTOROLA ...
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... Exception processing for bus error exceptions follows the regular sequence, but context preservation is more involved than for other exceptions because a bus exception can be ini- MOTOROLA ENTRY T0,T1 $7 I2:IO $0 VBR BUS ERROR SP BUS ERROR PC BUS ERROR/ ADDRESS ERROR (DOUBLE BUS FAULT) ASSERT HALT EXIT EXIT MC68360 USER’S MANUAL CPU32+ 5-41 ...
Page 184
... Exception processing for traps follows the regular sequence. If tracing is enabled when an instruction that causes a trap begins execution, a trace exception will be generated by the instruction, but the trap handler routine will not be traced. (The trap exception will be pro- cessed first, then the trace exception.) 5-42 MC68360 USER’S MANUAL MOTOROLA ...
Page 185
... This check ensures that the program does not make erroneous assumptions about information in the stack frame. If the format of the control data is improper, the processor generates a format error excep- tion. This exception saves a four-word format exception frame and then vectors through vec- MOTOROLA MC68360 USER’S MANUAL CPU32+ 5-43 ...
Page 186
... An attempt to execute one of these instructions at the user level will cause an exception. The privileged exceptions are as follows: • AND Immediate to SR • EOR Immediate to SR • LPSTOP • MOVE from SR 5-44 0000. MC68360 USER’S MANUAL MOTOROLA ...
Page 187
... If the instruction is not executed, either because an inter- rupt is taken or because the instruction is illegal, unimplemented, or privileged, an exception is not generated. MOTOROLA Table 5-18. Tracing Control T0 Tracing Function tracing 0 1 Trace on change of flow 1 0 Trace on instruction execution 1 1 Undefined; reserved MC68360 USER’S MANUAL CPU32+ 5-45 ...
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... INTERRUPTS. There are seven levels of interrupt priority and 192 assignable interrupt vectors within each exception vector table. Careful use of multiple vector tables and hardware chaining will permit a virtually unlimited number of peripherals to interrupt the pro- cessor. 5-46 MC68360 USER’S MANUAL MOTOROLA ...
Page 189
... RETURN FROM EXCEPTION. When exception stacking operations for all pend- ing exceptions are complete, the processor begins execution of the handler for the last exception processed. After the exception handler has executed, the processor must restore MOTOROLA MC68360 USER’S MANUAL CPU32+ 5-47 ...
Page 190
... SSW contains the internal processor state corresponding to the fault SZC1 SZC0 MC68360 USER’S MANUAL $14 in the stack frame. The SIZ FUNC MOTOROLA 0 ...
Page 191
... B0—Breakpoint Channel 0 Pending B0 indicates that a breakpoint exception was pending on channel 0 (internal breakpoint source) when the bus error exception was processed. Pending breakpoint status is stacked, regardless of the type of bus error exception Breakpoint not pending 1 = Breakpoint pending MOTOROLA MC68360 USER’S MANUAL CPU32+ 5-49 ...
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... FC2–FC0 for the faulted bus cycle. This field is reloaded into the bus controller if the RR bit is set during unstacking. All unused bits are stacked as zeros and are ignored during unstacking. Further discussion of the SSW is included in 5.5.3.1 Types of Faults. 5-50 MC68360 USER’S MANUAL MOTOROLA ...
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... The trace pending bit is always cleared since the instruction will be restarted upon return from the handler. Saving a pending exception on the stack causes a trace exception to be MOTOROLA SZC0 SZC0 MC68360 USER’S MANUAL CPU32 SIZ FUNC SIZ FUNC 5- ...
Page 194
... However, if the exception is one that causes a four- or six-word stack frame to be written, a bus cycle fault frame is written below the faulted exception stack frame. 5- SZC0 MC68360 USER’S MANUAL SIZ FUNC MOTOROLA 0 ...
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... RW, FUNC, and SIZ fields are restored and the released write cycle is rerun. To maintain long-word operand coherence, stack contents must be adjusted prior to the RTE execution. The fault address must be decremented the SZCx bits are set to long MOTOROLA SZC0 MC68360 USER’S MANUAL CPU32 SIZ FUNC 5-53 0 ...
Page 196
... set in the stacked SSW, create a six-word stack frame and execute the trace handler. If either set in the SSW, create another six-word stack frame and execute the hardware breakpoint handler. 5-54 MC68360 USER’S MANUAL MOTOROLA ...
Page 197
... Once the exception handler determines that the fault has been corrected, recovery can pro- ceed as described previously. If the fault cannot be corrected, move the supervisor stack to another area of memory, copy all valid stack frames to the new stack, create a faulted MOTOROLA MC68360 USER’S MANUAL CPU32+ $10). The return PC value is 5-55 ...
Page 198
... The CPU32+ bus error stack frame differs significantly from the equivalent stack 5-56 STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW 0 VECTOR OFFSET STATUS REGISTER NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW 0 VECTOR OFFSET FAULTED INSTRUCTION PROGRAM COUNTER HIGH FAULTED INSTRUCTION PROGRAM COUNTER LOW MC68360 USER’S MANUAL 0 0 MOTOROLA ...
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... SSW is located at SP The fault address of a dynamically sized bus cycle is the address of the upper byte, regard- less of the byte that caused the error. MOTOROLA SZC0 8 7 $12.) MC68360 USER’S MANUAL CPU32 SIZ FUNC TRANSFER COUNT 5- ...
Page 200
... SPECIAL STATUS WORD STATUS REGISTER NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW 0 VECTOR OFFSET FAULTED ADDRESS HIGH FAULTED ADDRESS LOW PRE-EXCEPTION STATUS REGISTER FAULTED EXCEPTION FORMAT/VECTOR WORD INTERNAL TRANSFER COUNT REGISTER SPECIAL STATUS WORD MC68360 USER’S MANUAL MOTOROLA ...