T7633 Agere Systems, T7633 Datasheet - Page 24

• Manufacturer Part Number: T7633
• Manufacturer: Agere Systems

Advance Data Sheet
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
May 2002
List of Tables
(continued)
Table
Page
Table 191. FDL Register FDL_PR7...................................................................................................................... 215
Table 192. FDL Receiver Match Character Register (FDL_PR8) (808; E08)....................................................... 215
Table 193. FDL Transparent Control Register (FDL_PR9) (809; E09) ................................................................ 216
Table 194. FDL Transmit ANSI ESF Bit Codes (FDL_PR10) (80A; E0A) ............................................................ 216
Table 195. FDL Interrupt Status Register (Clear on Read) (FDL_SR0) (80B; E0B) ............................................ 217
Table 196. FDL Transmitter Status Register (FDL_SR1) (80C; E0C).................................................................. 218
Table 197. FDL Receiver Status Register (FDL_SR2) (80D; E0D)...................................................................... 218
Table 198. Receive ANSI FDL Status Register (FDL_SR3) (80E; E0E) .............................................................. 218
Table 199. FDL Receiver FIFO Register (FDL_SR4) (807; E07) ......................................................................... 218
Table 200. Global Register Set ............................................................................................................................ 219
Table 201. Line Interface Unit Register Set.......................................................................................................... 219
Table 202. Framer Unit Status Register Map ....................................................................................................... 220
Table 203. Receive Signaling Registers Map....................................................................................................... 222
Table 204. Framer Unit Parameter Register Map ................................................................................................ 223
Table 205. Transmit Signaling Registers Map...................................................................................................... 226
Table 206. Facility Data Link Register Map.......................................................................................................... 227
Table 207. ESD Threshold Voltage ...................................................................................................................... 228
Table 208. Logic Interface Characteristics (T
= –40 °C to 85 °C, V
= 3.3 V ± 5%, V
= 0).......................... 229
A
DD
SS
12
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