DSP56852VF120 Motorola, DSP56852VF120 Datasheet
DSP56852VF120
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DSP56852VF120 Summary of contents
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... WR Enable Bus Control RD Enable CS[2:0] muxed (GPIOA) Figure 1. DSP56852 Block Diagram © Motorola, Inc., 2004. All rights reserved. For More Information On This Product, • Interrupt Controller • General Purpose 16-bit Quad Timer • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • ...
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Freescale Semiconductor, Inc. Part 1 Overview 1.1 DSP56852 Features 1.1.1 Digital Signal Processing Core • Efficient 16-bit DSP engine with dual Harvard architecture • 120 Million Instructions Per Second (MIPS) at 120MHz core frequency • Single-cycle 16 16-bit parallel Multiplier-Accumulator ...
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Freescale Semiconductor, Inc. • 81-pin MAPBGA package • GPIO * Each peripheral I/O can be used alternately as a General Purpose I/O if not needed 1.1.4 Energy Information • Fabricated in high-density CMOS with 3.3V, TTL-compatible digital ...
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... Freescale Semiconductor, Inc. 1.4 Product Documentation The four documents listed in Table 1 DSP56852. Documentation is available from local Motorola distributors, Motorola semiconductor sales offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors/. Table 1. DSP56852 Chip Documentation Topic DSP56800E Detailed description of the DSP56800E architecture, Reference Manual 16-bit DSP core processor and the instruction set ...
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Freescale Semiconductor, Inc. Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the DSP56852 are organized into functional groups, as shown in and as illustrated in Figure 2. In Table 3 present. Table 2. Functional Group Pin ...
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Freescale Semiconductor, Inc. VDD Logic Power VSS VDDIO I/O VSSIO Power Analog VDDA 1 Power VSSA A0–16 A17(TI/O) A18(TI/O) Address Bus A19(CS3) CLKO(A20) GPIOA0(CS0) GPIOA1(CS1) Chip Select GPIOA2(CS2) D0-D12 Data D13-D15/MODEA-C Bus RD Bus WR Control Figure 2. DSP56852 Signals ...
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Freescale Semiconductor, Inc. Part 3 Signals and Package Information All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are enabled by default. Exceptions: 1. When a pin has GPIO functionality, the pull-up may be ...
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Freescale Semiconductor, Inc. Table 3. DSP56852 Signal and Package Information for the 81-pin MAPBGA Pin No. Signal Name Type E4 A0 Output( ...
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Freescale Semiconductor, Inc. Table 3. DSP56852 Signal and Package Information for the 81-pin MAPBGA Pin No. Signal Name Type D3 CS1 Output GPIOA1 Input/Output C3 CS2 Output GPIOA2 Input/Output G7 D0 Input/Output ...
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Freescale Semiconductor, Inc. Table 3. DSP56852 Signal and Package Information for the 81-pin MAPBGA Pin No. Signal Name Type E3 WR Output B4 RXD Input GPIOE0 Input/Output D4 TXD Output(Z) GPIOE1 Input/Output B2 GPIOC0 Input/Output STXD Output A2 GPIOC1 Input/Output ...
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Freescale Semiconductor, Inc. Table 3. DSP56852 Signal and Package Information for the 81-pin MAPBGA Pin No. Signal Name Type C4 MISO Input/Output GPIOC4 Input/Output SRCK Input/Output C5 MOSI Input/ Output (Z) GPIOC5 Input/Output SRFS Input/Output A1 IRQA Input C2 IRQB ...
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Freescale Semiconductor, Inc. Table 3. DSP56852 Signal and Package Information for the 81-pin MAPBGA Pin No. Signal Name Type D5 RESET Input C6 TCK Input B7 TDI Input A8 TDO Output C7 TMS Input D6 TRST Input B8 DE Input/Output ...
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Freescale Semiconductor, Inc. Part 4 Specifications 4.1 General Characteristics The DSP56852 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process ...
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Freescale Semiconductor, Inc. Table 5. Recommended Operating Conditions Characteristic Supply voltage for Logic Power Supply voltage for I/O Power Supply voltage for Analog Power Ambient operating temperature 1 PLL clock frequency 2 Operating Frequency Frequency of peripheral bus Frequency of ...
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Freescale Semiconductor, Inc. 4.2 DC Electrical Characteristics Table 7. DC Electrical Characteristics Operating Conditions 0V SSIO SSA Characteristic Input high voltage (XTAL/EXTAL) Input low voltage (XTAL/EXTAL) Input high voltage Input low voltage ...
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Freescale Semiconductor, Inc. 150 EMI Mode 120 Figure 3. Maximum Run I 4.3 Supply Voltage Sequencing and Separation Cautions Figure 4 shows two situations to avoid in sequencing the V 3.3V 1. Notes: ...
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Freescale Semiconductor, Inc. V should not be allowed to rise early (1). This is usually avoided by running the regulator for the V DD supply (1.8V) from the voltage generated by the 3.3V V rising faster than V . DDIO ...
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Freescale Semiconductor, Inc. 4.4 AC Electrical Characteristics Timing waveforms in Section 4.2 are tested with a V all pins except XTAL, which is tested using the input levels in and V for an input signal are shown ...
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Freescale Semiconductor, Inc. Crystal Frequency = 2–4MHz (optimized for 4MHz) EXTAL XTAL 4.5.2 High Speed External Clock Source (> 4MHz) The recommended method of connecting an external clock is given in is connected to XTAL and the EXTAL pin is ...
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Freescale Semiconductor, Inc. Table 8. External Clock Operation Timing Requirements Operating Conditions 0V SSIO SSA Characteristic Frequency of operation (external clock driver) 4 Clock Pulse Width 2, 4 External clock input rise ...
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Freescale Semiconductor, Inc. 4.6 External Memory InterfaceTiming The External Memory Interface is designed to access static memory and peripheral devices. shows sample timing and parameters that are detailed in The timing of each parameter consists of both a fixed delay ...
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Freescale Semiconductor, Inc. Table 10. External Memory Interface Timing Operating Conditions SSIO SSA Characteristic Symbol Address Valid to WR Asserted WR Width Asserted to WR Deasserted Data Out Valid to ...
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Freescale Semiconductor, Inc. 4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 11. Reset, Stop, Wait, Mode Select, and Interrupt Timing Operating Conditions 0V SSIO SSA Characteristic RESET Assertion to Address, ...
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Freescale Semiconductor, Inc. RESET t RAZ A0–A20, D0–D15 CS, RD, WR Figure 13. Asynchronous Reset Timing IRQA IRQB Figure 14. External Interrupt Timing (Negative-Edge-Sensitive) A0–A20, CS IDM IRQA, IRQB Purpose I/O Pin t IG IRQA, IRQB ...
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Freescale Semiconductor, Inc IRQA A0–A20, CS, RD, WR Figure 17. Recovery from Stop State Using Asynchronous Interrupt Timing RESET Figure 18. Reset Output Timing DSP56852 Technical Data For More Information On This Product, Preliminary Reset, Stop, Wait, Mode ...
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Freescale Semiconductor, Inc. 4.8 Serial Peripheral Interface (SPI) Timing Operating Conditions 0V SSIO SSA Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCLK) high ...
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Freescale Semiconductor, Inc. SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output MISO (Input) MOSI (Output) Figure 19. SPI Master Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) ...
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Freescale Semiconductor, Inc. SS (Input) SCLK (CPOL = 0) (Input) t ELD SCLK (CPOL = 1) (Input MISO Slave MSB out (Output MOSI MSB in (Input) Figure 21. SPI Slave Timing (CPHA = 0) ...
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Freescale Semiconductor, Inc. 4.9 Quad Timer Timing Operating Conditions 0V SSIO SSA Characteristic Timer input period Timer input high/low period Timer output period Timer output high/low period 1. In the formulas listed, ...
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Freescale Semiconductor, Inc. 4.10 Synchronous Serial Interface (SSI) Timing Table 14. SSI Master Mode Operating Conditions 0V SSIO SSA Parameter STCK frequency 3 STCK period STCK high time STCK low time Output ...
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Freescale Semiconductor, Inc. t SCKW t SCKH STCK output t TFSBHM STFS (bl) output t TFSWHM STFS (wl) output t TXVM t TXEM STXD SRCK output t RFSBHM SRFS (bl) output t RFSWHM SRFS (wl) output t SM SRXD Figure ...
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Freescale Semiconductor, Inc. Table 15. SSI Slave Mode Operating Conditions 0V SSIO SSA Parameter Delay from SRCK high to SRFS (bl) high - Slave Delay from SRCK high to SRFS (wl) high ...
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Freescale Semiconductor, Inc. t SCKW t SCKH STCK input t TFSBHS STFS (bl) input t TFSWHS STFS (wl) input t FTXVS t FTXES t TXVS t TXES STXD SRCK input t RFSBHS SRFS (bl) input t RFSWHS SRFS (wl) input ...
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Freescale Semiconductor, Inc. RXD SCI receive data pin (Input) TXD SCI receive data pin (Input) MSCAN_RX CAN receive data pin (Input) Figure 28. Bus Wakeup Detection 4.12 JTAG Timing Operating Conditions 0V ...
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Freescale Semiconductor, Inc TCK (Input – Figure 29. Test Clock Input Timing Diagram TCK (Input) TDI TMS (Input) TDO (Output TDO (Output ) TDO (Output) ...
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Freescale Semiconductor, Inc. 4.13 GPIO Timing Operating Conditions 0V SSIO SSA Characteristic GPIO input period GPIO input high/low period GPIO output period GPIO output high/low period GPIO Inputs P IN GPIO Outputs ...
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Freescale Semiconductor, Inc. Part 5 DSP56852 Packaging & Pinout Information This section contains package and pin-out information for the 81-pin MAPBGA configuration of the DSP56852 D15 TD0 XTAL V DE TDI DDIO D14 TMS V SSIO D13 ...
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Freescale Semiconductor, Inc. Table 19. DSP56852 Pin Identification by Pin Number Pin No. Signal Name Pin No ...
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Freescale Semiconductor, Inc LASER MARK FOR PIN 1 Y IDENTIFICATION IN THIS AREA E 0. 81X 0. VIEW M-M 0. Figure 35. 81-pin MAPBGA ...
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Freescale Semiconductor, Inc. Part 6 Design Considerations 6.1 Thermal Design Considerations An estimation of the chip junction temperature, T Equation Where ambient temperature ° package junction-to-ambient thermal ...
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Freescale Semiconductor, Inc. on the case of the package will estimate a junction temperature slightly hotter than actual. Hence, the new thermal metric, Thermal Characterization Parameter, or gives a better estimate of the junction temperature in natural convection when using ...
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Freescale Semiconductor, Inc. • Designs that utilize the TRST pin for JTAG port or Enhance OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means ...
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... Table 20. DSP56852 Ordering Information Supply Part Voltage DSP56852 1.8–3.3 V Mold Array Process Ball Grid Array (MAPBGA) DSP56852 Technical Data For More Information On This Product, Preliminary Electrical Design Considerations Pin Package Type Count 81 Go to: www.freescale.com Frequency Order Number (MHz) 120 DSP56852VF120 43 ...
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... Motorola was negligent regarding the design or manufacture of the part. Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners ...