MCM69P618CTQ4.5 Motorola, MCM69P618CTQ4.5 Datasheet

MCM69P618CTQ4.5

Manufacturer Part Number

MCM69P618CTQ4.5

Description

Manufacturer

Motorola

Datasheet

1.MCM69P618CTQ4.5.pdf (12 pages)

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

64K x 18 Bit Pipelined BurstRAM

Synchronous Fast Static RAM

vide a burstable, high performance, secondary cache for the 68K Family,

PowerPC , 486, i960 , and Pentium microprocessors. It is organized as 64K

words of 18 bits each. This device integrates input registers, an output register,

a 2–bit address counter, and high speed SRAM onto a single monolithic circuit

for reduced parts count in cache data RAM applications. Synchronous design

allows precise cycle control with the use of an external clock (K). BiCMOS cir-

cuitry reduces the overall power consumption of the integrated functions for

greater reliability.

enable (G) and Linear Burst Order (LBO) are clock (K) controlled through

positive–edge–triggered noninverting registers.

addresses can be generated internally by the MCM69P618C (burst sequence

operates in linear or interleaved mode dependent upon the state of LBO) and

controlled by the burst address advance (ADV) input pin.

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

chronous write enable SW are provided to allow writes to either individual bytes

or to both bytes. The two bytes are designated as “a” and “b”. SBa controls DQa

and SBb controls DQb. Individual bytes are written if the selected byte writes SBx

are asserted with SW. Both bytes are written if either SGW is asserted or if both

SBx and SW are asserted.

edge–triggered output register and then released to the output buffers at the next

rising edge of clock (K).

and outputs are LVTTL compatible and 5 V tolerant.

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

i960 and Pentium are trademarks of Intel Corp.

REV 2

2/16/98

MOTOROLA FAST SRAM

Motorola, Inc. 1998

The MCM69P618C is a 1M–bit synchronous fast static RAM designed to pro-

Addresses (SA), data inputs (DQx), and all control signals except output

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

Write cycles are internally self–timed and initiated by the rising edge of the

Synchronous byte write (SBx), synchronous global write (SGW), and syn-

For read cycles, pipelined SRAMs output data is temporarily stored by an

The MCM69P618C operates from a single 3.3 V power supply and all inputs

MCM69P618C–4 = 4 ns Access / 7.5 ns Cycle

MCM69P618C–4.5 = 4.5 ns Access / 8 ns Cycle

MCM69P618C–5 = 5 ns Access / 10 ns Cycle

MCM69P618C–6 = 6 ns Access / 12 ns Cycle

MCM69P618C–7 = 7 ns Access / 13.3 ns Cycle

Single 3.3 V + 10%, – 5% Power Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Internally Self–Timed Write Cycle

Byte Write and Global Write Control

Single–Cycle Deselect Timing

5 V Tolerant on all Pins (Inputs and I/Os)

100–Pin TQFP Package

MCM69P618C

Order this document

by MCM69P618C/D

CASE 983A–01

TQ PACKAGE

MCM69P618C

TQFP

Related parts for MCM69P618CTQ4.5

MCM69P618CTQ4.5 Summary of contents

Page 1

... V Tolerant on all Pins (Inputs and I/Os) 100–Pin TQFP Package The PowerPC name is a trademark of IBM Corp., used under license therefrom. i960 and Pentium are trademarks of Intel Corp. REV 2 2/16/98 MOTOROLA FAST SRAM Motorola, Inc. 1998 Order this document by MCM69P618C/D MCM69P618C TQ PACKAGE TQFP CASE 983A–01 ...

Page 2

... SBa SBb SE1 SE2 SE3 G MCM69P618C 2 FUNCTIONAL BLOCK DIAGRAM BURST COUNTER K2 CLR 2 16 ADDRESS REGISTER WRITE REGISTER a WRITE REGISTER ENABLE ENABLE REGISTER REGISTER 2 16 64K x 18 ARRAY DATA–0UT DATA–IN REGISTER REGISTER K DQa, DQb MOTOROLA FAST SRAM ...

Page 3

... DQb 18 DQb DQb 22 DQb 23 DQb MOTOROLA FAST SRAM PIN ASSIGNMENT ...

Page 4

... Other vendors’ RAMs may have implemented the Sleep Mode (ZZ) feature. NC — No Connection: There is no connection to the chip. Description MOTOROLA FAST SRAM ...

Page 5

... INTERLEAVED BURST ADDRESS TABLE 1st Address (External) 2nd Address (Internal X00 X01 X10 X11 WRITE TRUTH TABLE Cycle Type Read Read Write Byte a Write Byte b Write All Bytes Write All Bytes MOTOROLA FAST SRAM SE2 SE3 ADSP ADSC ADV ...

Page 6

... Symbol Max Unit Notes MOTOROLA FAST SRAM ...

Page 7

... Data states are all zero. 4. Device in Deselected mode as defined by the Truth Table. CAPACITANCE (f = 1.0 MHz 3 Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance Input/Output Capacitance MOTOROLA FAST SRAM (Voltages Referenced Symbol Min V DD 3.135 V IL – 0.5* ...

Page 8

... Max Unit Notes 12 — 13.3 — — 4.5 — — 4.5 — ns — 6 — — 5 — — 0 — — 2 — — 0 — — 5 — 2.5 — 2.5 — ns 0.5 — 0.5 — ns MOTOROLA FAST SRAM ...

Page 9

... MOTOROLA FAST SRAM MCM69P618C 9 ...

Page 10

... Non–Burst Sync Non–Burst, Pipelined SRAM NOTE: Although X is specified in the table as a don’t care, the pin must be tied either high or low. D Q(B) Q(C) Q( ADSP ADSC ADV SE1 SE2 LBO D(E) D(F) D(G) D(H) WRITES MOTOROLA FAST SRAM ...

Page 11

... ORDERING INFORMATION (Order by Full Part Number) MCM 69P618C Blank = Trays Tape and Reel Speed ( ns, 4.5 = 4 ns) Package (TQ = TQFP) MCM69P618CTQ4R MCM69P618CTQ4.5 MCM69P618CTQ4.5R MCM69P618CTQ5 MCM69P618CTQ5R MCM69P618CTQ6 MCM69P618CTQ6R MCM69P618CTQ7 MCM69P618CTQ7R are registered trademarks of Motorola, Inc. Motorola, Inc Equal MCM69P618C 11 ...

Page 12

... VIEW AB How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 1-602-244-6609 Motorola Fax Back System – US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 – http://sps.motorola.com /mfax / HOME PAGE : http://motorola ...

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