AD8304ARU-REEL Analog Devices Inc, AD8304ARU-REEL Datasheet - Page 13

• Manufacturer Part Number: AD8304ARU-REEL
• Description: IC LOGARITHMIC CONV 14-TSSOP T/R
• Manufacturer: Analog Devices Inc
• Type: Logarithmic Converterr

Specifications of AD8304ARU-REEL

• Rohs Status: RoHS non-compliant
• Design Resources: Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056) Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector
• Applications: Fiber Optics
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP

The use of a capacitor at the VLOG Pin to create a single-pole
filter has already been mentioned. The small added cost of the few
external components needed to realize a multipole filter is often
justified in a high performance measurement system. Figure 8
shows a Sallen-Key filter structure. Here, the resistor needed at
the front of the network is provided entirely by the accurate 5 kΩ
present at the VLOG output; R
frequency and Q (damping factor) are determined by the capacitors
C
point for choosing these components using various gains is pro-
vided in Table IV; the values shown are for a 1 kHz corner (also
see TPC 12). This frequency can be increased or decreased by
scaling the capacitor values. Note that R
C
shape of the ac amplitude response and pulse overshoot provided
by the values shown in this table. In all cases, the roll-off rate above
the corner is 40 dB/dec.
Table IV. Two-Pole Filter Parameters for 1 kHz Cutoff
Frequency*
R
(k )
0
10
12
24
Operation in Comparator Modes
In certain applications, the need may arise to generate a logical
output when the input current has reached a certain value. This
can be easily addressed by using a fraction of the voltage refer-
ence to provide the setpoint (threshold) and using the buffer
without feedback in a comparator mode, as illustrated in Figure 9.
Since V
reference is more than adequate to cover the full dynamic range
of I
while the release point for decreasing currents is 5 dB below
this. Raising R
may be increased using a lower value for R
REV. A
NC = NO CONNECT
The corner frequency can be adjusted by scaling capacitors C
example, to reduce the corner frequency to 100 Hz, raise the values of C
C
*See TPC 12.
A
A
A
R1
750k
B
C1
1nF
10nF
/C
I
PD
and C
PD
by 10 .
B
. Note that the threshold for an increasing I
NC
should not deviate from the suggested values to maintain the
LOG
R
(k )
open
10
8
6
6
3
4
5
B
B
VSUM
VSUM
VPDB
INPT
and the gain G = (R
VNEG
runs from ground up to 1.6 V maximum, the 2 V
Figure 8. Two-Pole Low-Pass Filter
VPS2
H
1
to 5 MΩ reduces the hysteresis to 0.5 dB, or it
G
1
2
2.5
5
PDB
10
PWDN
~10k
V
(V/decade)
0.2
0.4
0.5
1.0
Y
COMPENSATION
ACOM
TEMPERATURE
BIAS
2
B
will have a similar value. The corner
A
14
+ R
B
0.5V
VPS1
)/R
D
, G, and the capacitor ratio
VREF
R
(k )
11.3
6.02
12.1
10.0
VOUT
12
B
5k
D
. A suggested starting
H
11
.
BFNG
BFIN
PD
13
A
is unchanged,
C
(nF)
12
33
33
33
7
8
9
V
and C
P
VLOG
VREF
A
CA
RD
RA
B
RB
. For
C
(nF)
12
22
18
18
A
B
and
CB
V
OUT
–13–
Using a Negative Supply
Most applications of the AD8304 will require only a single supply
of 3.0 V to 5.5 V. However, to provide further versatility, dual
supplies may be employed, as illustrated in Figure 10.
The use of a negative supply, V
be placed exactly at ground level, because the input transistor
(Q1 in Figure 1) will have a negative bias on its emitter. V
be as small as –0.5 V, making the V
case. This bias need not be accurate, and a poorly defined source
can be used.
A larger supply of up to –5 V may be used. The effect on scaling
is minor. It merely moves the intercept by ~0.01 dB/V. Accord-
ingly, an uncertainty of 0.2 V in V
error of 0.002 dB. The slope is unaffected by V
earity will be degraded at the extremes of the dynamic range as
indicated in Figure 11. The bias current, buffer output (and its
load) current, and the full I
negative supply, and its supply capacity must be ensured for the
maximum current condition.
With the summing node at ground, the AD8304 may now be used
as a voltage-input log amp, simply by inserting a suitably scaled
resistor from the voltage source to the INPT Pin. The logarith-
mic accuracy for small voltages is limited by the offset of the JFET
op amp, appearing between this pin and VSUM.
The use of a negative supply also allows the output to swing below
ground, thereby allowing the intercept to correspond to a midrange
value of I
NC = NO CONNECT
NC = NO CONNECT
R1
750
R1
750
C1
1nF
C1
1nF
10nF
I
I
PD
PD
NC
NC
Figure 9. Using the Buffer as a Comparator
PD
. However, the voltage V
4
4
6
3
5
6
3
5
Figure 10. Using a Negative Supply
VSUM
VSUM
VSUM
VSUM
VPDB
VPDB
INPT
INPT
V
VNEG
N
(–0.5V TO –3V)
VPS2
VPS2
1
1
PDB
PDB
VNEG
10
10
PWDN
PWDN
~10k
~10k
PD
COMPENSATION
COMPENSATION
ACOM
ACOM
TEMPERATURE
TEMPERATURE
BIAS
BIAS
2
2
N
all have to be absorbed by this
, allows the summing node to
14
14
N
CE
LOG
would result in a negligible
the same as for the default
remains referenced to the
VPS1
0.5V
0.5V
VPS1
VREF
VREF
VOUT
VOUT
12
12
5k
5k
11
11
N
AD8304
BFNG
BFNG
BFIN
BFIN
. The log lin-
13
13
7
8
9
7
8
9
V
V
P
P
VLOG
VLOG
VREF
VREF
RH
RB
V
V
N
OUT
OUT
RG
RA
RA
may