XC68HC912D60CPV8 Motorola, XC68HC912D60CPV8 Datasheet
XC68HC912D60CPV8
Available stocks
Related parts for XC68HC912D60CPV8
XC68HC912D60CPV8 Summary of contents
Page 1
... Freescale Semiconductor, Inc. M68HC12 Microcontrollers WWW.MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.com MC68HC(9)12D60 Advance Information MC68HC912D60/D Rev. 4, 11/2003 ...
Page 2
Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
Page 3
... Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...
Page 4
... Freescale Semiconductor, Inc. 68HC(9)12D60 — Rev 4.0 4 For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
Page 5
... Section 10. ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Section 11. I/O Ports with Key Wake- 135 Section 12. Clock Functions . . . . . . . . . . . . . . . . . . . . . 143 Section 13. Pulse Width Modulator . . . . . . . . . . . . . . . 181 Section 14. Enhanced Capture Timer 197 Section 15. Multiple Serial Interface 237 Section 16. Motorola Interconnect Bus . . . . . . . . . . . . 263 68HC(9)12D60 Rev 4.0 — MOTOROLA For More Information On This Product, ...
Page 6
... Section 20. Electrical Specifications . . . . . . . . . . . . . . 365 Section 21. Appendix: CGM Practical Aspects . . . . . . 387 Section 22. Appendix: 68HC912D60A Flash EEPROM399 Section 23. Appendix: 68HC912D60A EEPROM . . . . . 407 Glossary 419 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 Advance Information 6 For More Information On This Product, List of Paragraphs Go to: www.freescale.com 68HC(9)12D60 Rev 4.0 — MOTOROLA ...
Page 7
... Advance Information — 68HC(9)12D60 1.1 1.2 1.3 1.4 1.5 2.1 2.2 2.3 2.4 2.5 2.6 2.7 68HC(9)12D60 Rev 4.0 — MOTOROLA For More Information On This Product, List of Paragraphs Table of Contents List of Tables List of Figures Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ordering Information 68HC(9)12D60 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . .29 Section 2. Central Processing Unit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Data Types ...
Page 8
... Register Block .63 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Internal Resource Mapping .79 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Section 6. Bus Control and Input/Output Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Detecting Access Type from External Signals . . . . . . . . . . . . .87 Registers .88 Section 7. Flash Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Table of Contents Go to: www.freescale.com 68HC(9)12D60 Rev 4.0 — MOTOROLA ...
Page 9
... Rev 4.0 — MOTOROLA For More Information On This Product, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Overview .100 Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . .100 Flash EEPROM Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . 108 Erasing the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Program/Erase Protection Interlocks . . . . . . . . . . . . . . . . . . .113 Stop or Wait Mode ...
Page 10
... Phase-Locked Loop (PLL 145 Acquisition and Tracking Modes .147 Limp-Home and Fast STOP Recovery modes . . . . . . . . . . . . 149 System Clock Frequency formulas . . . . . . . . . . . . . . . . . . . . .167 Clock Divider Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 Computer Operating Properly (COP .172 Section 13. Pulse Width Modulator Table of Contents Go to: www.freescale.com 68HC(9)12D60 Rev 4.0 — MOTOROLA ...
Page 11
... Section 15. Multiple Serial Interface Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 Serial Communication Interface (SCI .238 Serial Peripheral Interface (SPI .250 Port 260 Section 16. Motorola Interconnect Bus Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Push-pull sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 Biphase coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 Message validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Interfacing to MI Bus 268 Table of Contents Go to: www ...
Page 12
... Protocol Violation Protection 289 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Section 18. Analog-to-Digital Converter Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324 ATD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 ATD Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 Section 19. Development Support Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 Table of Contents Go to: www.freescale.com 68HC(9)12D60 Rev 4.0 — MOTOROLA ...
Page 13
... Section 22. Appendix: 68HC912D60A Flash EEPROM 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 68HC(9)12D60 Rev 4.0 — MOTOROLA For More Information On This Product, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 Breakpoints 355 Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Section 20. Electrical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Tables of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Section 21. Appendix: CGM Practical Aspects Contents ...
Page 14
... EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .408 EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 409 Program/Erase Operation .415 Shadow Word Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Programming EEDIVH and EEDIVL Registers 416 Glossary Revision History Changes from Rev 3.0 to Rev 4 429 Changes from Rev 2.0 to Rev 3 429 Table of Contents Go to: www.freescale.com 68HC(9)12D60 Rev 4.0 — MOTOROLA ...
Page 15
... PWM Center-Aligned Boundary Conditions . . . . . . . . . . . . . . 196 14-1 Compare Result Output Action . . . . . . . . . . . . . . . . . . . . . . . . 212 14-2 Edge Detector Circuit Configuration . . . . . . . . . . . . . . . . . . . .212 14-3 Prescaler Selection 214 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Title Device Ordering Information 68HC(9)12D60 Development Tools Ordering Information . . . .28 M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . .34 Summary of Indexed Operations ...
Page 16
... Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366 20-2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 20-3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .368 20-4 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 20-5 ATD DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 369 20-6 Analog Converter Characteristics (Operating .370 20-7 ATD AC Characteristics (Operating .371 Advance Information 16 For More Information On This Product, List of Tables Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 17
... Suggested 8MHz Synthesis PLL Filter Elements 23-1 EEDIV Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410 23-2 2K byte EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . 412 23-3 Erase Selection .413 23-4 Shadow word mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, (Tracking Mode 393 (Acquisition Mode .394 List of Tables Go to: www.freescale.com ...
Page 18
... Freescale Semiconductor, Inc. List of Tables Advance Information 18 For More Information On This Product, List of Tables Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 19
... Block Diagram of PWM Center-Aligned Output Channel . . . . 183 13-3 PWM Clock Sources 184 14-1 Timer Block Diagram in Latch Mode .199 14-2 Timer Block Diagram in Queue Mode 200 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Title 68HC(9)12D60 112-pin QFP Block Diagram . . . . . . . . . . . . . . 29 68HC(9)12D60 80-pin QFP Block Diagram . . . . . . . . . . . . . . . 30 Programming Model ...
Page 20
... POR and External Reset Timing Diagram . . . . . . . . . . . . . . . 376 20-5 STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .377 20-6 WAIT Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 378 20-7 Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 Advance Information 20 For More Information On This Product, Pulse Accumulator .203 Conditioning Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373 FP Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 FP List of Figures Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 21
... Port Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .380 20-9 Port Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .380 20-10 Multiplexed Expansion Bus Timing Diagram . . . . . . . . . . . . . 382 20-11 SPI Timing Diagram ( 384 20-12 SPI Timing Diagram ( 385 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, List of Figures Go to: www.freescale.com List of Figures Advance Information ...
Page 22
... Freescale Semiconductor, Inc. List of Figures Advance Information 22 For More Information On This Product, List of Figures Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 23
... PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module 80QFP) I/O port pins are available with Key-Wake-Up capability from STOP or WAIT mode. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ordering Information ...
Page 24
... Two receive and three transmit buffers – Flexible identifier filter programmable bit bit bit – Four separate interrupt channels for Rx, Tx, error and wake-up General Description Go to: www.freescale.com 2 C start bit detector (112TQFP 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 25
... Rev 4.0 MOTOROLA For More Information On This Product, – Low-pass filter wake-up function – In 80QFP, only TxCAN and RxCAN pins are available – Loop-back for self test operation – Programmable link to a timer input capture channel, for time- stamping and network synchronization ...
Page 26
... general-purpose I/O lines, plus input-only lines in 112TQFP general-purpose I/O lines, plus input-only lines in 80QFP 8MHz operation at 5V Development support – Single-wire background debug™ mode (BDM) – On-chip hardware breakpoints General Description Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 27
... Designator C 4.5V–5.5V 8 MHz 4.5V–5.5V 8 MHz 4.5V–5.5V 8 MHz 4.5V–5.5V 8 MHz V M* General Description Go to: www.freescale.com General Description Ordering Information Order Number XC68HC912D60PV8 XC68HC912D60CPV8 XC68HC912D60VPV8 XC68HC912D60MPV8 XC68HC912D60FU8 XC68HC912D60CFU8 XC68HC912D60VFU8 XC68HC912D60MFU8 XC68HC12D60PV8 XC68HC12D60CPV8 XC68HC12D60VPV8 XC68HC12D60MPV8 XC68HC12D60FU8 XC68HC12D60CFU8 XC68HC12D60VFU8 XC68HC12D60MFU8 Advance Information 27 ...
Page 28
... Third party tools: http://www.mcu.motsps.com/dev_tools/3rd/index.html Advance Information 28 For More Information On This Product, Name Free from World Wide Web M68SDIL (3–5V), M68DIL12 (SDIL + MCUez + SDI SDBUG12) M68EVB912D60 (EVB only) EVB M68KIT912D60 (EVB + SDIL12) General Description Go to: www.freescale.com Order Number 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 29
... Narrow bus Notes: * 68HC912D60 only $ 68HC12D60 only § On the 68HC12D60 this pin is not connected and can be tied 12V without effect. Figure 1-1. 68HC(9)12D60 112-pin QFP Block Diagram 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, * VRH0 VRH0 ATD0 VRL0 ...
Page 30
... PS1 PS2 PS3 PS4 PS5 PS6 PS7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 TxCAN PCAN1 RxCAN PCAN0 PG4 VDD ×2 VSS ×2 Power for internal circuitry VDDX ×2 VSSX ×2 PH4 Power for I/O drivers 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 31
... Programming Model CPU12 registers are an integral part of the CPU and are not addressed as if they were memory locations. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Section 2. Central Processing Unit Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Addressing Modes ...
Page 32
... Figure 2-1. Programming Model Central Processing Unit Go to: www.freescale.com 0 8-BIT ACCUMULATORS A & 16-BIT DOUBLE ACCUMULATOR D 0 INDEX REGISTER X 0 INDEX REGISTER Y 0 STACK POINTER 0 PROGRAM COUNTER CONDITION CODE REGISTER 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 33
... The CPU12 includes all of the addressing modes of the M68HC11 CPU as well as several new forms of indexed addressing. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Bit data 8-bit and 16-bit signed and unsigned integers 16-bit unsigned fractions ...
Page 34
... Operand is a 16-bit address pc accumulator offset from (16-bit offset in two extension bytes) Pointer to operand is found at... (16-bit offset in two extension bytes) Pointer to operand is found at... plus the value in D 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 35
... B,r D,r 111rr111 [D,r] 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Specify which index register is used. Determine whether a value in an accumulator is used as an offset. Enable automatic pre- or post-increment or decrement Specify use of 5-bit, 9-bit, or 16-bit signed offsets. Table 2-2. Summary of Indexed Operations 5-bit constant offset n = – ...
Page 36
... Postbytes implement certain forms of indexed addressing, transfers, exchanges, and loop primitives. Extension bytes contain additional program information such as addresses, offsets, and immediate data. Advance Information 36 For More Information On This Product, Central Processing Unit Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 37
... Section 3. Pinout and Signal Descriptions 3.1 Contents 3.2 3.3 3.4 3.5 3.6 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, 68HC(9)12D60 Pin Assignments in 112-pin QFP 68HC(9)12D60 Pin Assignments in 80-pin QFP Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Pinout and Signal Descriptions Go to: www.freescale.com ...
Page 38
... PAD16/AN16 PAD06/AN06 81 80 PAD15/AN15 79 PAD05/AN05 PAD14/AN14 78 77 PAD04/AN04 PAD13/AN13 76 75 PAD03/AN03 74 PAD12/AN12 PAD02/AN02 73 72 PAD11/AN11 71 PAD01/AN01 PAD10/AN10 70 69 PAD00/AN00 V 68 RL0 V 67 RH0 PA7/ADDR15/DATA15/DATA7 63 PA6/ADDR14/DATA14/DATA6 PA5/ADDR13/DATA13/DATA5 62 61 PA4/ADDR12/DATA12/DATA4 PA3/ADDR11/DATA11/DATA3 60 PA2/ADDR10/DATA10/DATA2 59 58 PA1/ADDR9/DATA9/DATA1 PA0/ADDR8/DATA8/DATA0 57 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 39
... 0.050 θ C1 (Y) (Z) VIEW AB Figure 3-2. 112-pin TQFP Mechanical Dimensions (case no. 987) 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, 68HC(9)12D60 Pin Assignments in 112-pin QFP 0. TIPS VIEW AB θ ...
Page 40
... For More Information On This Product, 68HC(9)12D60 80 QFP Pinout and Signal Descriptions Go to: www.freescale.com 60 PAD07/AN07 59 PAD06/AN06 58 PAD05/AN05 57 PAD04/AN04 56 PAD03/AN03 55 PAD02/AN02 54 PAD01/AN01 53 PAD00/AN00 52 V RL0 51 V RH0 PA7/ADDR15/DATA15/DATA7 47 PA6/ADDR14/DATA14/DATA6 46 PA5/ADDR13/DATA13/DATA5 45 PA4/ADDR12/DATA12/DATA4 44 PA3/ADDR11/DATA11/DATA3 43 PA2/ADDR10/DATA10/DATA2 42 PA1/ADDR9/DATA9/DATA1 41 PA0/ADDR8/DATA8/DATA0 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 41
... S 0. -C- H SEATING PLANE G DATUM -H- PLANE DETAIL C Figure 3-4. 80-pin QFP Mechanical Dimensions (case no. 841B) 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, 68HC(9)12D60 Pin Assignments in 80-pin QFP 41 40 -B- B DETAIL - DETAIL C ...
Page 42
... ATD converter 0. RL0 : reference voltage high and low for ATD converter 1. RL1 Pinout and Signal Descriptions Go to: www.freescale.com and V . Because fast signal the ATD modules are not DD connected to V will not RH DD 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 43
... Flash EEPROM programming voltage and supply voltage during normal operation (68HC912D60 only – on the 68HC12D60 this pin is not connected and can be tied 12V without effect). 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Appendix: CGM Practical Aspects VDDPLL ...
Page 44
... Programming voltage for the Flash EEPROM and required supply for normal operation. (68HC912D60 only – on the 97 68HC12D60 this pin is not connected and can be tied 12V without effect) Pinout and Signal Descriptions Go to: www.freescale.com Description 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 45
... In all cases take extra care in the circuit board layout around the oscillator pins. Load capacitances in the oscillator circuits include all stray layout capacitances. Refer to diagrams of oscillator circuits. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product crystal or ceramic resonator EXTAL MCU ...
Page 46
... For More Information On This Product, Power-on-reset (POR) COP watchdog enabled and watchdog timer times out Clock monitor enabled and Clock monitor detects slow or stopped clock User applies a low level to the reset pin Pinout and Signal Descriptions Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 47
... This pin is always an input and can always be read. There is an active pull-up on this pin while in reset and immediately out of reset. The pull- up can be turned off by clearing PUPE in the PUCR register. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Pinout and Signal Descriptions Go to: www.freescale.com ...
Page 48
... The BKGD pin receives and transmits serial background debugging commands. A special self-timing protocol is used. The BKGD pin has an active pull-up when configured as input; BKGD has no pull-up control. Refer to Advance Information 48 For More Information On This Product, Development Support. Pinout and Signal Descriptions Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 49
... This pin is also used as TAGLO in Special Expanded modes and is multiplexed with the LSTRB function. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Pinout and Signal Descriptions Go to: www.freescale.com ...
Page 50
... If the DBE function is enabled it will override the enabled CAL output. The CAL pin output is disabled by clearing CALE bit in the PEAR register. Advance Information 50 For More Information On This Product, Development Support. Pinout and Signal Descriptions Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 51
... IRQ 39 55 68HC(9)12D60 — Rev 4.0 MOTOROLA Description Crystal driver and external clock input pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. An active low bidirectional control signal, RESET acts as an input to initialize the MCU to a known start-up state, and an output when COP or clock monitor causes a reset ...
Page 52
... Key wake-up and general purpose I/O; can cause an interrupt when an input transitions from high to low. On 80-pin QFP all 8 I/O should be initialised. Defines if I/O port resistive load is a pull- pull-down, when enabled. Pinout and Signal Descriptions For More Information On This Product, Go to: www.freescale.com Development 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 53
... Setting the RDPA bit in register RDRIV causes all port A outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to Input/Output. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Pinout and Signal Descriptions Go to: www.freescale.com Pinout and Signal Descriptions ...
Page 54
... DDRE register makes the corresponding bit in port E an output; clearing a bit in the DDRE register makes the corresponding bit in port E an input. The default reset state of DDRE is all zeros. Advance Information 54 For More Information On This Product, Pinout and Signal Descriptions Go to: www.freescale.com Bus Control and 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 55
... Setting the RDPG bit in register RDRIV causes all port G outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to Input/Output. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, I/O Ports with Key Wake-up. Pinout and Signal Descriptions Go to: www ...
Page 56
... MSCAN12 address space. In 80QFP all PortCAN[2:7] pins should either be defined as outputs or have their pull-ups enabled. Advance Information 56 For More Information On This Product, I/O Ports with Key Wake-up. Pinout and Signal Descriptions Go to: www.freescale.com Bus Control and 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 57
... When the PUPP bit in the PWCTL register is set, all input pins are pulled up internally by an active pull-up device. Pull-ups are disabled after reset. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Analog-to-Digital Converter. Analog-to-Digital Converter ...
Page 58
... Register DDRT determines pin direction of port T when used for general- purpose I/O. When DDRT bits are set, the corresponding pin is Advance Information 58 For More Information On This Product, Pulse Width Modulator. Multiple Serial Pinout and Signal Descriptions Go to: www.freescale.com Interface. 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 59
... Setting the RDPT bit in the TMSK2 register configures all port T outputs to have reduced drive levels. Levels are at normal drive capability after reset. The TMSK2 register can be read or written anytime after reset Refer to 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Enhanced Capture Timer. Pinout and Signal Descriptions Go to: www ...
Page 60
... I/O. General-purpose I/O when not enabled for input capture In/Out and output compare in the timer and pulse accumulator DDRT ($00AF) subsystem. Table 3-4 Pinout and Signal Descriptions Go to: www.freescale.com Description summarizes the port pull-up/pull- 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 61
... Reset Bit Name State RDPA Full drive RDPB Full drive RDPE Full drive RDPE Full drive RDPG Full drive RDPH Full drive Full drive RDPS0 Full drive RDPS1 Full drive RDPS2 Full drive TDRB Full drive 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 62
... Freescale Semiconductor, Inc. Pinout and Signal Descriptions Advance Information 62 For More Information On This Product, Pinout and Signal Descriptions Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 63
... The register block occupies the first 512 bytes of the 2K byte block. Default addressing (after reset) is indicated in Table Resource 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Register Block .63 4-1. For additional information refer to Mapping. Registers Go to: www ...
Page 64
... COPCTL 2 1 Bit 0 COPRST Reserved Reserved Reserved Reserved Reserved Reserved INTCR PSEL1 0 HPRIO 0 0 BRKCT0 BK0RWE BK0RW BRKCT1 10 9 Bit 8 BRKAH 68HC(9)12D60 — Rev 4.0 MOTOROLA (1) (1) (1) (1) (3) (3) (3) (3) (2) (2) (3) (3) (3) (3) (3) (3) ...
Page 65
... Bit 7 6 $004A Bit 7 6 $004B Bit 7 6 $004C Bit 7 6 $004D Bit 7 6 $004E Bit 7 6 Table 4-1. 68HC(9)12D60 Register Map (Sheet 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product ...
Page 66
... CC0 ATD0STAT0 CCF1 CCF0 ATD0STAT1 ATD0TEST SAR3 SAR2 TST1 TST0 ATD0TESTL Reserved PAD01 PAD00 PORTAD0 10 9 Bit 8 ADR00H ADR00L 10 9 Bit 8 ADR01H ADR01L 10 9 Bit 8 ADR02H ADR02L 10 9 Bit 8 ADR03H ADR03L 68HC(9)12D60 — Rev 4.0 MOTOROLA H ...
Page 67
... Bit 15 14 $0099 Bit 7 6 $009A Bit 15 14 $009B Bit 7 6 $009C Bit 15 14 $009D Bit 7 6 Table 4-1. 68HC(9)12D60 Register Map (Sheet 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product ...
Page 68
... Bit 8 TC0H 2 1 Bit 0 TC0H 10 9 Bit 8 TC1H 2 1 Bit 0 TC1H 10 9 Bit 8 TC2H 2 1 Bit 0 TC2H 10 9 Bit 8 TC3H 2 1 Bit 0 TC3H SBR9 SBR8 SC0BDH SBR1 SBR0 SC0BDL ILT PE PT SC0CR1 RE RWU SBK SC0CR2 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 69
... FSTE GADR $00F6 ( $00F7 ( $00F8 ( $00F9 (5) FSTE GADR $00FA Table 4-1. 68HC(9)12D60 Register Map (Sheet 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product RDRF IDLE OR MDL1 MDL0 R5/T5 R4/T4 R3/T3 R2/T2 BRLD SBR12 SBR11 SBR10 SBR5 ...
Page 70
... AM0 CIDMR3 AC1 AC0 CIDAR4 AC1 AC0 CIDAR5 AC1 AC0 CIDAR6 AC1 AC0 CIDAR7 AM1 AM0 CIDMR4 AM1 AM0 CIDMR5 AM1 AM0 CIDMR6 AM1 AM0 CIDMR7 Reserved 0 PUPCAN RDPCAN PCTLCAN TxCAN RxCAN PORTCAN 0 0 DDRCAN RxFG 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 71
... Bit 15 14 $01FD Bit 7 Bit 6 $01FE Bit 15 14 $01FF Bit 7 Bit 6 Table 4-1. 68HC(9)12D60 Register Map (Sheet 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product TRANSMIT BUFFER 0 TRANSMIT BUFFER 1 TRANSMIT BUFFER 2 (4) Unimplemented Reserved Reserved AWAI 0 ...
Page 72
... Port E and DDRE not in map in peripheral mode; also not in map in expanded modes with EME set. 3. Registers also not in map in peripheral mode. 4. Data read at these locations is undefined. 5. Available on 68HC912D60 only. Registers are unimplemented on 68HC12D60 - data read at these locations is undefined. Advance Information 72 For More Information On This Product, Registers Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 73
... BKGD, MODB, and MODA pins during reset. The SMODN, MODB, and MODA bits in the MODE register show current operating mode and provide limited mode switching during operation. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Internal Resource Mapping ...
Page 74
... Special modes — allow greater access to protected control registers and bits for special purposes such as testing and emulation. Operating Modes and Resource Mapping Go to: www.freescale.com Port A Port B G.P. I/O G.P. I/O ADDR/DATA ADDR — — ADDR/DATA ADDR/DATA G.P. I/O G.P. I/O ADDR/DATA ADDR ADDR/DATA ADDR/DATA ADDR/DATA ADDR/DATA 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 75
... I.C. tester, can control the on-chip peripherals. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Normal Single-Chip Mode — There are no external address and data buses in this mode. The MCU operates as a stand- alone device and all program and data resources are on-chip ...
Page 76
... Background debugging should not be used while the MCU is in special peripheral mode as internal bus conflicts between BDM and the external master can cause improper operation of both modes. Operating Modes and Resource Mapping Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 77
... SMODN is Read anytime. May only be written in special modes (SMODN = 0). The first write is ignored; MODB, MODA may be written once in Normal modes (SMODN = 1). Write anytime in special modes (first write is ignored) – special peripheral and reserved modes cannot be selected. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product ...
Page 78
... External bus and registers continue functioning during wait mode External bus is shut down during wait mode. Normal modes: write anytime; Special modes: write never. Read anytime. Advance Information 78 For More Information On This Product, Operating Modes and Resource Mapping Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 79
... The 68HC912D60 contains 60K bytes of Flash EEPROM nonvolatile memory which can be used to store program code or static data 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Operating Modes and Resource Mapping Go to: www.freescale.com Operating Modes and Resource Mapping ...
Page 80
... Advance Information 80 For More Information On This Product, Table 5-2. Mapping Precedence Precedence 1 BDM ROM (if active On-Chip Flash EEPROM (68HC912D60) 5 ROM (68HC12D60) 6 External Memory Operating Modes and Resource Mapping Go to: www.freescale.com Resource Register Space RAM EEPROM 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 81
... Normal modes: write anytime; special modes: write never. Read anytime Memory mapping interface continues to function during Wait mode Memory mapping interface access is shut down during Wait mode. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product REG13 REG12 REG11 ...
Page 82
... These bits specify the upper five bits of the 16-bit RAM address. Normal modes: write once; special modes: write anytime. Read anytime. Advance Information 82 For More Information On This Product RAM13 RAM12 RAM11 Operating Modes and Resource Mapping Go to: www.freescale.com 2 1 Bit $0010 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 83
... EEON — internal EEPROM On (Enabled) This bit is forced to one in single-chip modes. Read or write anytime Removes the EEPROM from the map Places the on-chip EEPROM in the memory map at the address selected by EE[15:12]. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product EE13 EE12 ...
Page 84
... If the registers are moved this space follows. Advance Information 84 For More Information On This Product RFSTR0 EXSTR1 EXSTR0 ROMON28 ROMON32 Operating Modes and Resource Mapping Go to: www.freescale.com 1 Bit Exp Modes Modes $0013 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 85
... FEE32 (68HC912D60) or ROM arrays ROM28 and ROM32 (68HC12D60) respectively Corresponding Flash EEPROM/ROM array disabled from the memory map Corresponding Flash EEPROM/ROM array enabled in the memory map. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Table 5-3. RFSTR Stretch Bit Definition RFSTR1 RFSTR0 0 0 ...
Page 86
... TO ANY 4K SPACE) $0FFF $1000 * 28K Flash EEPROM (FEE28 28K ROM (ROM28) $7FFF $6000 - $7FFF Protected BOOT $8000 * 32K Flash EEPROM (FEE32 32K ROM (ROM32) $E000 - $FFFF Protected BOOT $FFFF $FF00 BDM (if active) $FFFF * 68HC912D60 $ 68HC12D60 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 87
... LSTRB = because the internal RAM is specifically designed to allow misaligned 16-bit accesses in a single cycle. In these cases the data for the address 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Section 6. Bus Control and Input/Output Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Detecting Access Type from External Signals ...
Page 88
... Bus Control and Input/Output Go to: www.freescale.com Type of Access 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 89
... This register determines the primary direction for each port A pin when functioning as a general-purpose I/O port. DDRA is not in the on-chip map in expanded and peripheral modes. Read and write anytime Associated pin is a high-impedance input 1 = Associated pin is an output 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product PA5 ...
Page 90
... ADDR4 ADDR3 ADDR2 DDB5 DDB4 DDB3 DDB2 Bus Control and Input/Output Go to: www.freescale.com 2 1 Bit 0 PB2 PB1 PB0 — — — ADDR1/ ADDR0/ DATA1 DATA0 ADDR1 ADDR0 $0001 2 1 Bit 0 DDB1 DDB0 $0003 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 91
... Bit 7 6 DDE7 DDE6 RESET DDRE — Port E Data Direction Register This register determines the primary direction for each port E pin configured as general-purpose I/O. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product PE5 PE4 PE3 — — — ...
Page 92
... LSTRE RDWE Bus Control and Input/Output Go to: www.freescale.com 2 1 BIT 0 CALE DBENE Normal Expanded Special Expanded Peripheral Normal single chip Special single chip $000A 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 93
... Normal: write never; Special: write anytime EXCEPT the first. Read anytime PE6 is general-purpose I/O or pipe output PE6 is a test signal output from the CGM module (no effect in 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, memories, or inverted E clock. general-purpose I/O. single chip or normal expanded modes). PIPOE = 1 overrides this function and forces PE6 pipe status output signal ...
Page 94
... CGM module). queue (only effective in expanded modes). limitation: In single-chip modes, to get an E clock output signal necessary to have ESTR = 0 in addition to NECLK = 0. the MCU is not in single chip or normal expanded narrow modes. Bus Control and Input/Output Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 95
... PE7 pin used for DBE external control of data enable PE7 pin used for inverted E clock output in expanded modes 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, has no effect and PE2 is a general-purpose I/O pin. I/O in single chip or peripheral modes or if the NDBE bit is set. ...
Page 96
... This bit has no effect if port A is being used as part of the address/data bus (the pull-ups are inactive). Advance Information 96 For More Information On This Product PUPE Bus Control and Input/Output Go to: www.freescale.com 1 Bit 0 PUPB PUPA 0 0 $000C 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 97
... All port B output pins have reduced drive capability. RDPA — Reduced Drive of Port All port A output pins have full drive enabled All port A output pins have reduced drive capability. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product ...
Page 98
... Freescale Semiconductor, Inc. Bus Control and Input/Output Advance Information 98 For More Information On This Product, Bus Control and Input/Output Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 99
... The Flash EEPROM is ideal for program storage for single-chip applications allowing for field reprogramming. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Section 7. Flash Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Overview .100 Flash EEPROM Control Block ...
Page 100
... The Flash EEPROM can be mapped to an alternate address range. See Operating Modes and Resource Advance Information 100 For More Information On This Product, pin. To prevent damage to the flash array Mapping. Flash Memory Go to: www.freescale.com should FP Table 20-10 in Electrical 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 101
... The boot blocks are located at $6000–$7FFF and $E000–$FFFF for each Flash EEPROM module Enable erase and program of 8K byte boot block 1 = Disable erase and program of 8K byte boot block 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product ...
Page 102
... For More Information On This Product HVT FENLV FDISVFP VTCK Voltage Lock FP pin is below normal programming voltage the Flash FP Flash Memory Go to: www.freescale.com 2 1 Bit 0 STRE MWPR $00F6/$00FA pin low FP is low FP 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 103
... ADDR[1:0] = 10, will both be programmed with the same word data from the programming latches. This bit should not be changed during programming Multiple word programming disabled 1 = Program 32 bits of data 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Check Test Enable T FP voltage. ...
Page 104
... ERAS Voltage FP pin is below normal programming voltage levels FP pin is above normal programming voltage levels FP Table 7-1 Flash Memory Go to: www.freescale.com 1 Bit 0 LAT ENPE 0 0 $00F7/$00FB for more information. Status of Table 7-1 for the effects of LAT 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 105
... Operation The Flash EEPROM can contain program and data. On reset, it can operate as a bootstrap memory to provide the CPU with internal initialization information during the reset sequence. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Table 7-1 for more information. ENPE ...
Page 106
... LAT is set. Writes to the control registers will occur normally. Program/Erase Verification — When programming or erasing the Flash EEPROM array, a special verification method is required to ensure Advance Information 106 For More Information On This Product, Flash Memory Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 107
... The erase software is responsible for all timing during an erase sequence. This includes the total number of erase pulses (e 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, PPULSE voltage must be applied and stabilized. The ERAS bit FP ...
Page 108
... BOOTP is asserted, an attempt to program an address in the boot block will be ignored. Flash Memory Go to: www.freescale.com ) from always greater or equal to V power supply with the Programming can FP DD pin. FP pin PPULSE 68HC(9)12D60 — Rev 4.0 MOTOROLA DD DD ...
Page 109
... If there are more locations to program, repeat steps 2 through 10. 12. Turn off V The flowchart in programming sequence. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, If the location is not programmed, repeat steps 4 through 7 until the location is programmed or until the specified maximum number of program pulses has been reached (n If the location is programmed, repeat the same number of pulses as required to program the location ...
Page 110
... CLEAR LAT GET NEXT DONE? ADDRESS/DATA NO YES TURN OFF V FP DONE PROG Figure 7-1. Program Sequence Flow Flash Memory Go to: www.freescale.com ) PP SET MARGIN FLAG INCREMENT n COUNTER PP READ NO LOCATION DATA CORRECT? YES 50 YES NO LOCATION FAILED TO PROGRAM 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 111
... Read the entire array to ensure that the Flash EEPROM is erased. 10. Clear LAT. 11. Turn off V The flowchart in sequence. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, FP (apply program/erase voltage to the V FP erasing. voltage to be turned on; the data written and the address written are not important ...
Page 112
... YES DECREMENT ARRAY n COUNTER EP ERASED YES ARRAY ERASED? NO YES CLEAR LAT TURN OFF V FP ARRAY ERASED ARRAY FAILED TO ERASE Figure 7-2. Erase Sequence Flow Flash Memory Go to: www.freescale.com SET MARGIN FLAG YES YES 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 113
... STOP mode. If the operating bus frequency is greater than 4MHz, the Flash cannot be used when recovering from STOP mode when the DLY bit in the INTCR register is cleared. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Program/Erase Protection Interlocks is not present, no ...
Page 114
... Freescale Semiconductor, Inc. Flash Memory Advance Information 114 For More Information On This Product, Flash Memory Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 115
... The EEPROM module has hardware interlocks which protect stored data from corruption by accidentally enabling the program/erase voltage. Programming voltage is derived from the internal V 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Section 8. EEPROM Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Future EEPROM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 EEPROM Programmer’ ...
Page 116
... Successive writes to an EEPROM location must be preceded by an erase cycle. To ensure full compatibility it is recommended that all of 68HC912D60A EEPROM Advance Information 116 For More Information On This Product, contains detailed information to be reviewed. EEPROM Memory Go to: www.freescale.com Appendix: 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 117
... NOSHB is cleared. At the next reset the SHADOW byte data is loaded into the EEMCR. The SHADOW byte can be protected from being programmed or erased by setting the SHPROT bit of EEPROT register. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Operating Modes and Resource EEPROM Memory Go to: www ...
Page 118
... Bit 6 of the SHADOW byte should not be cleared (set to '0') in order to have the full EEPROM array visible. If Bit 6 from the SHADOW byte is cleared then the following thirty-one bytes $0FC1–$0FFF have no meaning and are reserved by Motorola. Advance Information 118 For More Information On This Product, ...
Page 119
... SHPROT — SHADOW Byte Protection 0 = The SHADOW byte can be programmed and erased The SHADOW byte is protected from being programmed and 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, pump. Internal RC oscillator is stopped. oscillator is required when the system bus clock is lower than f ...
Page 120
... BPROT2 $0F00 to $0F7F BPROT1 $0F80 to $0FBF BPROT0 $0FC0 to $0FFF BYTE ROW ERASE EEPROM Memory Go to: www.freescale.com Block Size 512 Bytes 256 Bytes 128 Bytes 64 Bytes 64 Bytes 1 Bit 0 EELAT EEPGM 0 0 $00F3 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 121
... EEPGM and EELAT bits are required before reading the programmed data. A write to an EEPROM location has no effect when EEPGM is set. Latched address and data cannot be modified during program or erase. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Table 8-2. Erase Selection BYTE ROW ...
Page 122
... Write EEPGM = 0 6. Write EELAT = possible to program/erase more bytes or words without intermediate EEPROM reads, by jumping from step 5 to step 2. Advance Information 122 For More Information On This Product erase (t PROG EEPROM Memory Go to: www.freescale.com ) delay time erase 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 123
... The remainder of the vectors are used for maskable interrupts, and all must be initialized to point to the address of the appropriate service routine. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Section 9. Resets and Interrupts Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Latching of Interrupts ...
Page 124
... HPRIO can only be written while the I bit is set (interrupts inhibited). sources and vectors in default order of priority. Advance Information 124 For More Information On This Product, Resets and Interrupts Go to: www.freescale.com Table 9-1 lists interrupt 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 125
... These interrupt flags should be cleared during an interrupt service routine or when interrupts are masked by the I bit. By doing this, the MCU will never get an unknown interrupt source and take the trap vector. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Resets and Interrupts Go to: www.freescale.com ...
Page 126
... TMSK1 (C4I) $E6 TMSK1 (C5I) $E4 TMSK1 (C6I) $E2 TMSK1 (C7I) $E0 TMSK2 (TOI) $DE PACTL (PAOVI) $DC PACTL (PAI) $DA SP0CR1 (SPIE) $D8 SC0CR2 $D6 SC1CR2 $D4 $D2 CRIER (WUPIE) $D0 KWIEG[6:0] and $CE KWIEH[7:0] MCCTL (MCZI) $CC PBCTL (PBOVI) $CA TWRNIE, $C8 BOFFIE, OVRIE) CRIER (RXFIE) $C6 $C4 $C2 $80–$C0 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 127
... No stabilization delay imposed on exit from STOP mode Stabilization delay is imposed before processing resumes after DLY can be read anytime and written once in normal modes. In special modes, DLY can be read and written anytime. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product ...
Page 128
... MC34064 or MC33464) to prevent power transitions or corruption of RAM or EEPROM. Advance Information 128 For More Information On This Product PSEL5 PSEL4 PSEL3 PSEL2 causes a power-on reset (POR). An external DD Resets and Interrupts Go to: www.freescale.com 2 1 Bit 0 PSEL1 $001F 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 129
... A premature write will also reset the part. 9.6.4 Clock Monitor Reset If clock frequency falls below a predetermined limit when the clock monitor is enabled, a reset occurs. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Resets and Interrupts Go to: www.freescale.com Resets and Interrupts ...
Page 130
... However, the interrupt mask bits in the CPU12 CCR are set to mask X- and I-related interrupt requests. 9.7.4 Parallel I/O If the MCU comes out of reset in a single-chip mode, all ports are configured as general-purpose high-impedance inputs. Advance Information 130 For More Information On This Product, Resets and Interrupts Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 131
... Other Resources The enhanced capture timer (ECT), pulse width modulation timer (PWM), serial communications interfaces (SCI0 and SCI1), serial peripheral interface (SPI), Motorola Scalable CAN (MSCAN) and analog-to-digital converters (ATD0 and ATD1) are off after reset. 9.8 Register Stacking Once enabled, an interrupt request can be recognized at any time after the I bit in the CCR is cleared ...
Page 132
... For More Information On This Product, Table 9-2. Stacking Order on Entry to Interrupts Memory Location CPU Registers SP – – – – – 9 Resets and Interrupts Go to: www.freescale.com Table 9-2. RTN : RTN CCR 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 133
... K byte array mapped from $8000 to $FFFF at reset. The MAPROM bit in the MISC register allows the swapping of the two arrays. ROMON28 and ROMON32 enable or disable the ROM module. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 ROM Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 ROM Go to: www ...
Page 134
... Freescale Semiconductor, Inc. ROM Advance Information 134 For More Information On This Product, ROM Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 135
... KWIEG or KWIEH bit are both set. All 15 bits/pins share the same interrupt vector. Key wake-ups can be used with the pins configured as inputs or outputs. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Section 11. I/O Ports with Key Wake-up Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Key Wake-up and Port Registers ...
Page 136
... PH3 — — — KWH5 KWH4 KWH3 KWH2 I/O Ports with Key Wake-up Go to: www.freescale.com Mapping Bit 0 PG1 PG0 — — — KWG1 KWG0 2 1 Bit 0 PH2 PH1 PH0 — — — KWH1 KWH0 68HC(9)12D60 — Rev 4.0 MOTOROLA $0028 $0029 ...
Page 137
... DDRH — Port H Data Direction Register Data direction register H is associated with port H and designates each pin as an input or output. Read and write anytime Associated pin is an input 1 = Associated pin is an output 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product DDG5 DDG4 ...
Page 138
... C Start condition detection on PG7 and PG6 2 C Start condition is defined as a high to low transition of the KWIEH5 KWIEH4 KWIEH3 KWIEH2 I/O Ports with Key Wake-up Go to: www.freescale.com 2 1 Bit 0 KWIEG1 KWIEG0 $002C 2 1 Bit 0 KWIEH1 KWIEH0 $002D 68HC(9)12D60 — Rev 4.0 MOTOROLA 2 C ...
Page 139
... Depending on WI2CE bit in KWIEG register, KWIFG6 flags either falling edge or I2C Start condition. KWIFG[5:0] — Key Wake-up Port G Flags 0 = Falling edge on the associated bit has not occurred 1 = Falling edge on the associated bit has occurred (an interrupt 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product KWIFG5 ...
Page 140
... For More Information On This Product KWIFH5 KWIFH4 KWIFH3 KWIFH2 will occur if the associated enable bit is set) in order to be considered as a single pulse by the filter. If KWSP I/O Ports with Key Wake-up Go to: www.freescale.com 2 1 Bit 0 KWIFH1 KWIFH0 $002F 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 141
... Valid STOP Wake-Up pulse t KWSTP Minimum time interval between pulses to be recognized as single pulses Figure 11-1. STOP Key Wake-up Filter (falling edge trigger) timing 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, , the majority voting logic may treat KWSP min. t max ...
Page 142
... Freescale Semiconductor, Inc. I/O Ports with Key Wake-up Advance Information 142 For More Information On This Product, I/O Ports with Key Wake-up Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 143
... CPU and on-chip peripherals. A clock monitor circuit, a computer operating properly (COP) watchdog circuit, and a periodic interrupt circuit are also incorporated into the 68HC(9)12D60. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Section 12. Clock Functions Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Clock Sources .144 Phase-Locked Loop (PLL) ...
Page 144
... COP clocks. The slow clock bus frequencies divide the crystal frequency in a programmable range 252, with steps of 4. Figure 12-1 Divider Chains Advance Information 144 For More Information On This Product, shows some of the timing relationships. See the section for further details. Clock Functions Go to: www.freescale.com Clock 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 145
... Refer to Signal 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Figure 12-6 for an overview of system clocks. Descriptions. Clock Functions Go to: www ...
Page 146
... For More Information On This Product, LOCK REFDV <2:0> DETECTOR REFERENCE PROGRAMMABLE REFCLK DIVIDER PDET PHASE DIVCLK DETECTOR LOOP PROGRAMMABLE LOOP DIVIDER FILTER SYN <5:0> XCLK XFC Clock Functions Go to: www.freescale.com LOCK UP CPUMP VCO DOWN VDDPLL XFC × 2 PAD PLLCLK description. 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 147
... PLL start-up, usually periodic intervals. In either case, when the LOCK bit is set, the PLLCLK clock is safe to use as the source 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO ...
Page 148
... PLL control register. This is to avoid switching to tracking mode too early while the XFC voltage level is still too far away from its quiescent value corresponding to the target frequency. This operation would be very detrimental to the stabilization time. Clock Functions Go to: www.freescale.com Chains. If the VCO is selected as 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 149
... With limp home mode enabled (NOLHM bit cleared) and the clock monitor enabled (CME or FCME bits set loss of clock, the PLL 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Limp-Home and Fast STOP Recovery modes During normal clock operation. ...
Page 150
... Advance Information 150 For More Information On This Product, ) and ECLK is also equal to f VCOMIN --> 4096 0 --> 4096 PLLCLK (Limp-Home) Clock Functions Go to: www.freescale.com is provided as the system , VCOMIN MSCAN clock . VCOMIN Restore BCSP Restore PLLCLK or EXTALi 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 151
... With the VDDPLL supply voltage at VDD level, any reset sets the Clock Monitor Enable bit (CME) and the PLLON bit and clears the NOLHM bit. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Limp-Home and Fast STOP Recovery modes ...
Page 152
... Internal reset SYSCLK PLLCLK (L.H.) SYSCLK PLLCLK (Software check of Limp-Home Flag) (Slow EXTALi) Figure 12-4. No Clock at Power-On Reset Advance Information 152 For More Information On This Product, (Slow EXTALi) 0 --> 4096 EXTALi Clock Functions Go to: www.freescale.com Reset: BCSP = 0 EXTALi 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 153
... MCU operation will execute only on EXTALi clock. NOTE: The external clock signal must stabilise within the initial 4096 reset counter cycles. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Limp-Home and Fast STOP Recovery modes Clock Functions Go to: www.freescale.com Clock Functions ...
Page 154
... EXTAL pin (e.g. an external square wave source). STOP mode is exited with an external reset, an external interrupt from IRQ or XIRQ, a Key Wake-Up interrupt from port J or port MSCAN Wake-Up interrupt. Advance Information 154 For More Information On This Product, Clock Functions Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 155
... NOTE: The external clock signal should stabilise within the 4096 reset counter cycles. Use of DLY=0 is not recommended due to this requirement. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Limp-Home and Fast STOP Recovery modes Restore BCSP Restore PLLCLK or EXTALi ...
Page 156
... Under these conditions, improper EXTALi clock cycles can occur on SYSCLK. This may lead to a code runaway. Advance Information 156 For More Information On This Product, Clock Functions Go to: www.freescale.com ), following a VCOMIN 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 157
... When using an external clock, i.e. a square wave source possible to exit STOP with the DLY bit cleared. In this case the LHOME flag is never set and STOP is de-asserted without delay. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Limp-Home and Fast STOP Recovery modes Clock Functions Go to: www ...
Page 158
... LHOME flag is cleared and the LHIF limp-home Advance Information 158 For More Information On This Product, Recovery. ) with both the LHOME flag set and the LHIF limp- VCOMIN Clock Functions Go to: www.freescale.com STOP Exit and 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 159
... In this mode, crystal activity is the only method by which the device may recover from Pseudo-STOP. The device will start execution with the EXTALi clock following 4096 XCLK cycles. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Limp-Home and Fast STOP Recovery modes Clock Functions Go to: www ...
Page 160
... Advance Information 160 For More Information On This Product, and Table 12-2 summarise the exit conditions from STOP =V ). The RESET wakeup pulse must be longer than the DDPLL DD Clock Functions Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 161
... Home mode, clock monitor disabled, with Delay Pseudo-STOP exit without Limp Home mode, clock monitor disabled, without Delay 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Limp-Home and Fast STOP Recovery modes Conditions NOLHM=1 Oscillator must be stable within 4096 XCLK cycles. XCLK CME=0 can be modified by SLOW divider register ...
Page 162
... SYN3 SYN2 REFDV2 TSTOUT4 TSTOUT3 TSTOUT2 Clock Functions Go to: www.freescale.com 2 1 Bit 0 SYN1 SYN0 $0038 2 1 Bit 0 REFDV1 REFDV0 $0039 2 1 Bit 0 TSTOUT1 TSTOUT0 $003A 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 163
... LHOME — Limp-Home Mode Status 0 = MCU is operating normally, with EXTALi clock available for 1 = Loss of reference clock. CGM delivers PLL VCO limp-home For Limp-Home mode, see 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Limp-Home and Fast STOP Recovery modes 5 4 ...
Page 164
... VCO is running. See Electrical Advance Information 164 For More Information On This Product AUTO ACQ 0 PSTP lock automatically. software control, using ACQ bit. Specifications. Clock Functions Go to: www.freescale.com 2 1 Bit 0 LHIE NOLHM 0 0 (2) — $003C 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 165
... Read anytime; Normal modes: write once; Special modes: write anytime. Forced to 1 when VDDPLL is at VSS level. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Limp-Home and Fast STOP Recovery modes frequency. The loop filter is in high bandwidth, acquisition mode ...
Page 166
... SCIs. In limp-home mode, the output of MCS is forced to 0, but the MCS bit reads the latched value. Advance Information 166 For More Information On This Product BCSS 0 0 MCS Clock Functions Go to: www.freescale.com 2 1 Bit $003D 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 167
... SLWCLK = EXTALi PLLCLK = 2 x EXTALi x (SYNR + 1) / (REFDV + 1) ECLK = SYSCLK / 2 XCLK = SLWCLK / 2 PCLK = SYSCLK / 2 BCLK Boolean equations SYSCLK is slower than EXTALi (BCSS=1, BCSP=0, SLOW>0), BCLK becomes ECLK. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product SLDV5 SLDV4 SLDV3 SLDV2 ...
Page 168
... During limp-home mode PCLK, ECLK, BCLK, MCLK and XCLK are supplied by VCO (PLLCLK). 12.8 Clock Divider Chains Figure clock divider chains for the various peripherals on the 68HC(9)12D60. Advance Information 168 For More Information On This Product, 12-6, Figure 12-7, Figure 12-8, and Clock Functions Go to: www.freescale.com Figure 12-9 summarize the 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 169
... Bus clock select bits BCSP and BCSS in the clock select register (CLKSEL) determine which clock drives SYSCLK for the main system including the CPU and buses. BCSS has no effect if BCSP is set. During 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, 1:x SYSCLK ÷ ...
Page 170
... TRANSMIT ÷ BAUD RATE (1x) 2 1:0:1 SCI1 ÷ 2 1:1:0 RECEIVE BAUD RATE (16x) ÷ 16 ÷ 2 1:1:1 SCI1 TRANSMIT BAUD RATE (1x) Clock Functions Go to: www.freescale.com 0:0:0 REGISTER: COPCTL BITS: CR2, CR1, CR0 0:0:1 ÷ 0:1:0 4 ÷ 0:1:1 4 ÷ 4 1:0:0 ÷ 4 1:0:1 ÷ 2 1:1:0 ÷ 2 1:1:1 TO RTI TO COP 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 171
... PORT T7 PAEN 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, REGISTER: MCCTL BITS: MCPR1, MCPR0 MCEN 0:0 ÷ 0:1 4 ÷ 1:0 2 ÷ 1:1 2 Prescaled MCLK PULSE ACC LOW BYTE PULSE ACC PACLK GATE HIGH BYTE LOGIC PAMOD Figure 12-8 ...
Page 172
... Transmit 1: Detect falling edge, count 6 ECLKs while output is high impedance, Drive out 1 E cycle pulse high, high imped- ance output again Transmit 0: Detect falling edge, Drive out low, count 9 ECLKs, Drive out 1 E cycle pulse high, high impedance output 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 173
... EXTALi clock. Clock monitor time-outs are shown in EXTALi clock period with an ideal 50% duty cycle is twice this time-out value. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Table Table 12-3. Clock Monitor Time-Outs Supply 5 V +/– 10% Clock Functions Go to: www ...
Page 174
... For More Information On This Product RSBCK Reserved RTBYP RTR2 Wait. background mode. mode. This is useful for emulation. chain is normally XCLK divided by 2 becomes XCLK divided by 4). Clock Functions Go to: www.freescale.com 2 1 Bit 0 RTR1 RTR0 $0014 13 , when bypassed 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 175
... This bit is cleared automatically by a write to this register with this bit set Time-out has not yet occurred Set when the time-out period is met. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Time-Out Period Time-Out Period X = 125 KHz X = 500 KHz ...
Page 176
... Home and Fast STOP Recovery CME VDDPLL is high CME VDDPLL is low. limp-home mode. Limp-Home and Fast STOP Recovery Clock Functions Go to: www.freescale.com 2 1 Bit 0 CR2 CR1 CR0 Normal Special Limp- modes. modes. 68HC(9)12D60 — Rev 4.0 MOTOROLA $0016 ...
Page 177
... COP rates. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, depending on the state of CME and if COP is enabled. COP enabled Forced reset ...
Page 178
... Clock Functions Go to: www.freescale.com Window COP enabled: Effective Window end (2) Window OFF OFF (3) 0.768 3.840 ms 18.8 % 16.128 ms 23.4 % 64.512 ms 23.4 % 261.120 ms 24.6 % 523.264 ms 24.8 % 1.047552 ms 24.9 % 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 179
... Writing anything other than $55 or $AA causes a COP reset to occur. Advance Information 179 For More Information On This Product Clock Functions Go to: www.freescale.com 1 Bit 0 1 Bit $0017 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 180
... Freescale Semiconductor, Inc. Clock Functions Advance Information 180 For More Information On This Product, Clock Functions Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 181
... This causes the counter to reset and the new duty and/or period values to be latched. In addition, since the counter is readable it is 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Section 13. Pulse Width Modulator Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 PWM Register Description ...
Page 182
... Figure 13-1. Block Diagram of PWM Left-Aligned Output Channel Advance Information 182 For More Information On This Product, CENTR = 0 UP/DOWN PWCNTx 8-BIT COMPARE = PWDTYx 8-BIT COMPARE = PWPERx PWDTY PWPER Pulse Width Modulator Go to: www.freescale.com FROM PORT P DATA REGISTER S Q MUX MUX Q TO PIN R DRIVER PPOLx 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 183
... Scaled ECLK) GATE (CLOCK EDGE SYNC) PWENx SYNC PPOL = 1 PPOL = 0 PWDTY Figure 13-2. Block Diagram of PWM Center-Aligned Output Channel 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, CENTR = 1 RESET PWCNTx (DUTY CYCLE) 8-BIT COMPARE = PWDTYx (PERIOD) 8-BIT COMPARE = PWPERx × ...
Page 184
... Figure 13-3. PWM Clock Sources PCKA2 PCKA1 PCKA0 PCKB2 Pulse Width Modulator Go to: www.freescale.com CLOCK TO PWM CHANNEL 0 PCLK0 CLOCK TO PWM CHANNEL 1 ÷ 2 PCLK1 CLOCK TO PWM CHANNEL 2 PCLK2 CLOCK TO PWM CHANNEL 3 ÷ 2 PCLK3 2 1 Bit 0 PCKB1 PCKB0 $0040 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 185
... PCKA2 – PCKA0 — Prescaler for Clock A Clock A is one of two clock sources which may be used for channels 0 and 1. These three bits determine the rate of clock A, as shown in Table 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, channel. channel. 13-1. ...
Page 186
... PCLK1 PCLK0 PPOL3 PPOL2 Pulse Width Modulator Go to: www.freescale.com Value of Clock A ( ÷ ÷ ÷ ÷ ÷ ÷ ÷ 128 Bit 0 PPOL1 PPOL0 $0041 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 187
... If the polarity bit is one, the duty registers contain a count of the high time. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, when the duty count is reached. when the duty count is reached. ...
Page 188
... Channel 1 is disabled Channel 1 is enabled. Advance Information 188 For More Information On This Product PWEN3 PWEN2 Pulse Width Modulator Go to: www.freescale.com 1 Bit 0 PWEN1 PWEN0 0 0 $0042 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 189
... PCLK0 and PCLK1 respectively. Clock S0 is generated by dividing clock A by the value in the PWSCAL0 register + 1 and dividing again by two. When PWSCAL0 = $FF, clock A is divided by 256 then divided by two to generate clock S0. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product ...
Page 190
... Pulse Width Modulator Go to: www.freescale.com 1 Bit 0 1 Bit $0045 1 Bit 0 1 Bit $0046 1 Bit 0 1 Bit $0047 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 191
... When a channel is enabled, the associated PWM counter starts at the count in the PWCNTx register using the clock selected for that channel. In special mode, when DISCP = 1 and configured for left-aligned output, a match of period does not reset the associated PWM counter. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product ...
Page 192
... Pulse Width Modulator Go to: www.freescale.com 1 Bit 0 1 Bit 0 $004C 1 Bit 0 $004D 1 Bit 0 $004E 1 Bit 0 $004F 1 1 (CENTR = 0) (CENTR = 1) 1 Bit 0 1 Bit 0 $0050 1 Bit 0 $0051 1 Bit 0 $0052 1 Bit 0 $0053 1 1 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 193
... CENTR — Center-Aligned Output Mode To avoid irregularities in the PWM output mode, write the CENTR bit only when PWM channels are disabled PWM channels operate in left-aligned output mode 1 = PWM channels operate in center-aligned output mode 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product ...
Page 194
... Write to PWSCAL0 and PWSCAL1 does not load scale Advance Information 194 For More Information On This Product DISCAL channel counter. associated PWM counter register. counters Pulse Width Modulator Go to: www.freescale.com 2 1 Bit $0055 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 195
... DDRP determines pin direction of port P when used for general-purpose I/O. Read and write anytime. DDRP[7:0] — Data Direction Port P pin 7 I/O pin configured as high impedance input 1 = I/O pin configured for output. 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product PP5 PP4 ...
Page 196
... Table 13-3. PWM Center-Aligned Boundary Conditions PWDTYx PWPERx >$00 $00 >$00 $00 ≥PWPERx – ≥PWPERx – – $00 – $00 Pulse Width Modulator Go to: www.freescale.com PPOLx Output 1 Low 0 High 1 High 0 Low 1 High 0 Low PPOLx Output 1 Low 0 High 1 High 0 Low 1 High 0 Low 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 197
... These additional features are: • • • • • 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, Section 14. Enhanced Capture Timer Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . 203 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Timer and Modulus Counter Operation in Different Modes . . 235 16-Bit Buffer Register for four Input Capture (IC) channels ...
Page 198
... Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word. Advance Information 198 For More Information On This Product, Enhanced Capture Timer Go to: www.freescale.com 68HC(9)12D60 — Rev 4.0 MOTOROLA ...
Page 199
... Pin logic EDG6 EDG2 PT7 Pin logic EDG7 EDG3 Figure 14-1. Timer Block Diagram in Latch Mode 68HC(9)12D60 — Rev 4.0 MOTOROLA For More Information On This Product, 16-bit Free-running 16 BIT MAIN TIMER main timer ÷ Prescaler M clock Comparator TC0 capture/compare register ...
Page 200
... PA0H hold register RESET 0 PAC1 PA1H hold register RESET 0 PAC2 PA2H hold register RESET 0 PAC3 PA3H hold register LATQ, BUFEN (queue mode) Read TC3H hold register Read TC2H hold register Read TC1H hold register Read TC0H hold register 68HC(9)12D60 — Rev 4.0 MOTOROLA ...