UPD70F3033BYGC-8EU NEC, UPD70F3033BYGC-8EU Datasheet

UPD70F3033BYGC-8EU

Manufacturer Part Number

UPD70F3033BYGC-8EU

Description

32-bit RISC single-chip microcontroller(V850/SB1:Low-noise Enhanced version)

Manufacturer

NEC

Datasheet

1.UPD70F3033BYGC-8EU.pdf (668 pages)

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User’s Manual

V850/SB1

32-Bit Single-Chip Microcontroller

Hardware

Document No. U13850EJ6V0UD00 (6th edition)

Date Published February 2003 N CP(K)

Printed in Japan

µ µ µ µ PD703031A

µ µ µ µ PD703031AY µ µ µ µ PD703030BY µ µ µ µ PD703034AY µ µ µ µ PD703034BY

µ µ µ µ PD703032A

µ µ µ µ PD703032AY µ µ µ µ PD703031BY µ µ µ µ PD703035AY µ µ µ µ PD703035BY

µ µ µ µ PD703033A

µ µ µ µ PD703033AY µ µ µ µ PD703032BY µ µ µ µ PD703037AY µ µ µ µ PD703036HY

µ µ µ µ PD70F3032A µ µ µ µ PD703033B

µ µ µ µ PD70F3032AY µ µ µ µ PD703033BY µ µ µ µ PD70F3035AY µ µ µ µ PD703037HY

µ µ µ µ PD70F3033A µ µ µ µ PD70F3030B µ µ µ µ PD70F3037A µ µ µ µ PD70F3035B

µ µ µ µ PD70F3033AY µ µ µ µ PD70F3030BY µ µ µ µ PD70F3037AY µ µ µ µ PD70F3035BY

1999, 2000, 2003

µ µ µ µ PD703030B

µ µ µ µ PD703031B

µ µ µ µ PD703032B

µ µ µ µ PD70F3032B

µ µ µ µ PD70F3032BY

µ µ µ µ PD70F3033B

µ µ µ µ PD70F3033BY

, V850/SB2

µ µ µ µ PD703034A

µ µ µ µ PD703035A

µ µ µ µ PD703037A

µ µ µ µ PD70F3035A µ µ µ µ PD703037H

µ µ µ µ PD703034B

µ µ µ µ PD703035B

µ µ µ µ PD703036H

µ µ µ µ PD70F3036H

µ µ µ µ PD70F3036HY

µ µ µ µ PD70F3037H

µ µ µ µ PD70F3037HY

Related parts for UPD70F3033BYGC-8EU

UPD70F3033BYGC-8EU Summary of contents

Page 1

User’s Manual V850/SB1 32-Bit Single-Chip Microcontroller Hardware µ µ µ µ PD703031A µ µ µ µ PD703030B µ µ µ µ PD703031AY µ µ µ µ PD703030BY µ µ µ µ PD703034AY µ µ µ µ PD703034BY µ µ µ ...

... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...

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... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • ...

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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • ...

Page 6

... Addition of description in 2.3 (9) (b) (i) LBEN p. 92 Modification of P23 I/O circuit type and description on P33 in 2.4 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins p. 96 Addition of description on minimum instruction execution time in 3.1 p. 100 Modification of description and addition of Note in 3.2.2 (2) Program status word (PSW) Addition of 3.4.5 (2) (a) V850/SB1 ( µ ...

Page 7

Pages p. 197 Addition of 6.6 (1) While an instruction is being executed on internal ROM p. 198 Addition of 6.6 (2) While an instruction is being executed on external ROM p. 206 Addition of description in Caution in 7.1.4 ...

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Pages p. 437 Addition of Caution in 11.3 (2) Analog input channel specification register (ADS) p. 447 Addition of 11.7 How to Read A/D Converter Characteristics Table p. 452 Addition of 12.3 Configuration Addition of 12.4 (2) (a) V850/SB1 ( ...

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Readers This manual is intended for users who wish to understand the functions of the V850/SB1 and V850/SB2 and design application systems using the V850/SB1 or V850/SB2. Purpose This manual is intended to give users to an understanding of the ...

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Conventions Data significance: Higher digits on the left and lower digits on the right Active low: xxx (overscore over pin or signal name) Memory map address: Higher addresses at the top and lower addresses at the bottom Note: Footnote for ...

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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Related documents for V850/SB1 and V850/SB2 V850 Series Architecture User’s Manual V850/SB1, V850/SB2 Hardware User’s Manual Related documents for ...

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... Pin configuration (top view) (V850/SB2 (B and H versions)).......................................................66 1.5.5 Function blocks (V850/SB2 (B and H versions)) .........................................................................69 CHAPTER 2 PIN FUNCTIONS ...............................................................................................................73 2.1 List of Pin Functions ................................................................................................................73 2.2 Pin States...................................................................................................................................80 2.3 Description of Pin Functions...................................................................................................81 2.4 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins...........92 2.5 Pin I/O Circuits ..........................................................................................................................94 CHAPTER 3 CPU FUNCTIONS..............................................................................................................96 3.1 Features .....................................................................................................................................96 3.2 CPU Register Set ......................................................................................................................97 3.2.1 Program register set....................................................................................................................98 3.2.2 System register set ...

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Image ........................................................................................................................................ 104 3.4.3 Wrap-around of CPU address space ........................................................................................ 105 3.4.4 Memory map ............................................................................................................................. 106 3.4.5 Area .......................................................................................................................................... 107 3.4.6 External expansion mode ......................................................................................................... 114 3.4.7 Recommended use of address space ...................................................................................... 117 3.4.8 Peripheral I/O registers ............................................................................................................. ...

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Interrupt control register (xxICn) ...............................................................................................162 5.3.5 In-service priority register (ISPR) ..............................................................................................165 5.3.6 ID flag........................................................................................................................................165 5.3.7 Watchdog timer mode register (WDTM)....................................................................................166 5.3.8 Noise elimination.......................................................................................................................166 5.3.9 Edge detection function.............................................................................................................168 5.4 Software Exceptions ..............................................................................................................169 5.4.1 Operation ..................................................................................................................................169 5.4.2 Restore......................................................................................................................................170 5.4.3 EP flag.......................................................................................................................................171 ...

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Operation as external event counter......................................................................................... 222 7.2.5 Operation to output square wave.............................................................................................. 223 7.2.6 Operation to output one-shot pulse........................................................................................... 225 7.2.7 Cautions.................................................................................................................................... 230 7.3 8-Bit Timer (TM2 to TM7)........................................................................................................234 7.3.1 Outline....................................................................................................................................... 234 7.3.2 Functions .................................................................................................................................. 234 7.3.3 Configuration............................................................................................................................. 235 ...

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I C bus definitions and control methods ....................................................................................292 2 10.3 interrupt requests (INTIICn) .................................................................................................299 10.3.6 Interrupt request (INTIICn) generation timing and wait control .................................................317 10.3.7 Address match detection method..............................................................................................318 10.3.8 Error detection...........................................................................................................................318 10.3.9 Extension code..........................................................................................................................318 10.3.10 ...

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Cautions ..................................................................................................................................443 11.7 How to Read A/D Converter Characteristics Table .............................................................447 CHAPTER 12 DMA FUNCTIONS .........................................................................................................451 12.1 Functions ................................................................................................................................451 12.2 Transfer Completion Interrupt Request ...............................................................................451 12.3 Configuration ..........................................................................................................................452 12.4 Control Registers ...................................................................................................................453 12.5 Operation.................................................................................................................................462 12.6 Cautions ..................................................................................................................................463 CHAPTER 13 ...

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... ROM Correction Peripheral I/O Registers ............................................................................519 CHAPTER 18 FLASH MEMORY ..........................................................................................................523 18.1 Features ...................................................................................................................................523 18.1.1 Erase unit ..................................................................................................................................524 18.1.2 Write/read time ..........................................................................................................................524 18.2 Writing with Flash Programmer ............................................................................................525 18.3 Programming Environment ...................................................................................................530 18.4 Communication Mode ............................................................................................................530 18.5 Pin Connection .......................................................................................................................533 18.5.1 V pin .......................................................................................................................................533 PP 18.5.2 Serial interface pin ....................................................................................................................533 18.5.3 RESET pin.................................................................................................................................536 18.5.4 Port pins (including NMI) ...........................................................................................................536 18 ...

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Interrupt Generation Timing and Main CPU Processing ....................................................588 19.5.1 Master transmission.................................................................................................................. 588 19.5.2 Master reception ....................................................................................................................... 590 19.5.3 Slave transmission.................................................................................................................... 592 19.5.4 Slave reception ......................................................................................................................... 594 19.5.5 Interval of occurrence of interrupt for IEBus control.................................................................. 596 CHAPTER 20 ELECTRICAL ...

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Figure No. 3-1 CPU Register Set ...........................................................................................................................................97 3-2 CPU Address Space.....................................................................................................................................103 3-3 Image on Address Space .............................................................................................................................104 3-4 Program Space.............................................................................................................................................105 3-5 Data Space ...................................................................................................................................................105 3-6 Memory Map.................................................................................................................................................106 3-7 Internal ROM Area (128 KB).........................................................................................................................107 3-8 Internal ROM/Flash Memory Area (256 KB) ...

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Figure No. 5-13 Pipeline Operation at Interrupt Request Acknowledgment........................................................................... 177 5-14 Pipeline Flow and Interrupt Request Signal Generation Timing................................................................... 179 5-15 Key Return Block Diagram ........................................................................................................................... 181 6-1 Clock Generator ........................................................................................................................................... 183 6-2 Oscillation Stabilization Time ....................................................................................................................... 196 7-1 Block ...

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... Square Wave Output Operation Timing........................................................................................................246 7-35 Timing of PWM Output .................................................................................................................................248 7-36 Timing of Operation Based on CRn0 Transitions .........................................................................................249 7-37 Cascade Connection Mode with 16-Bit Resolution.......................................................................................251 7-38 Start Timing of Timer n .................................................................................................................................252 7-39 Timing After Compare Register Changes During Timer Count Operation....................................................252 8-1 Block Diagram of Watch Timer .....................................................................................................................253 8-2 Operation Timing of Watch Timer/Interval Timer ...

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Figure No. 10-28 Address ........................................................................................................................................................ 354 10-29 Transfer Direction Specification ................................................................................................................... 355 10-30 ACK Signal ................................................................................................................................................... 356 10-31 Stop Condition .............................................................................................................................................. 357 10-32 Wait Signal ................................................................................................................................................... 358 10-33 Arbitration Timing Example .......................................................................................................................... 381 10-34 Communication Reservation Timing............................................................................................................. 384 10-35 Timing ...

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Figure No. 11-7 A/D Conversion End Interrupt Generation Timing ........................................................................................445 11-8 Handling of AV Pin ....................................................................................................................................446 DD 11-9 Overall Error .................................................................................................................................................447 11-10 Quantization Error.........................................................................................................................................448 11-11 Zero-Scale Error ...........................................................................................................................................448 11-12 Full-Scale Error.............................................................................................................................................449 11-13 Differential Linearity Error .............................................................................................................................449 11-14 Integral Linearity Error ...

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... Communication with Dedicated Flash Programmer (UART0) ...................................................................... 530 18-5 Communication with Dedicated Flash Programmer (CSI0) .......................................................................... 531 Communication with Dedicated Flash Programmer (CSI0 + HS) ................................................................. 531 18-6 18-7 V Pin Connection Example........................................................................................................................ 533 PP 18-8 Conflict of Signals (Serial Interface Input Pin) .............................................................................................. 534 18-9 Malfunction of Other Device ......................................................................................................................... 535 18-10 Conflict of Signals (RESET Pin) ................................................................................................................... 536 18-11 Procedure for Manipulating Flash Memory ...

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Table No. 1-1 Product Lineup of V850/SB1 ..........................................................................................................................30 1-2 Product Lineup of V850/SB2 ..........................................................................................................................31 2-1 Pin I/O Buffer Power Supplies ........................................................................................................................73 2-2 Differences in Pins Between V850/SB1 and V850/SB2 .................................................................................73 2-3 Operating States of Pins in Each Operating Mode .........................................................................................80 ...

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Table No. 10-4 INTIICn Generation Timing and Wait Control............................................................................................... 317 10-5 Extension Code Bit Definitions ..................................................................................................................... 319 10-6 Status During Arbitration and Interrupt Request Generation Timing ............................................................ 320 10-7 Wait Periods ................................................................................................................................................. 321 2 10-8 Configuration of I Cn..................................................................................................................................... 337 ...

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Table No. 18-7 Response Command ....................................................................................................................................540 19-1 Transfer Rate and Maximum Number of Transfer Bytes in Communication Mode 1....................................542 19-2 Contents of Control Bits................................................................................................................................547 19-3 Control Field for Locked Slave Unit ..............................................................................................................548 19-4 Control Field for Unlocked Slave Unit...........................................................................................................548 19-5 ...

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... The V850/SB1 and V850/SB2 are products in the NEC Electronics V850 Series of single-chip microcontrollers designed for low power operation. 1.1 General The V850/SB1 and V850/SB2 are 32-bit single-chip microcontrollers that include the V850 Series CPU core, and peripheral functions such as ROM/RAM, a timer/counter, a serial interface, an A/D converter, a timer, and DMA controller. Based on the V850/SA1™ ...

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Product Name On-Chip Commercial Name Part Number µ PD703031A V850/SB1 µ PD703031AY µ PD703033A µ PD70F3033A µ PD703033AY µ PD70F3033AY µ PD703032A µ PD70F3032A µ PD703032AY µ PD70F3032AY µ PD703031B µ PD703031BY µ PD703033B µ PD70F3033B µ PD703033BY µ PD70F3033BY ...

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Product Name On-Chip Commercial Name Part Number µ PD703034A V850/SB2 No µ PD703034AY Yes µ PD703035A No µ PD70F3035A µ PD703035AY Yes µ PD70F3035AY µ PD703037A No µ PD70F3037A µ PD703037AY Yes µ PD70F3037AY µ PD703034B No µ PD703034BY Yes ...

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Flash memory versions Flash memory versions of the V850/SB1: Flash memory versions of the V850/SB2: µ PD70F3035A, 70F3035AY, 70F3035B, 70F3035BY, 70F3036H, • Mask ROM versions Mask ROM versions of the V850/SB1: µ PD703030B, 703030BY, 703031A, 703031AY, 703031B, 703031BY, Mask ...

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... Total: 83 (12 input ports and 71 I/O ports interface enabled Timer/counter 16-bit timer: 2 channels (PWM output) 8-bit timer: 6 channels (4 PWM outputs, cascade connection enabled) Watch timer When operating under subclock or main clock: 1 channel Operation using the subclock or main clock is also possible in the IDLE mode. ...

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Serial interface (SIO) Asynchronous serial interface (UART) Clocked serial interface (CSI bus interface (I and 70F3033AY) 8-/16-bit variable-length serial interface CSI/UART: CSI/I CSI (8-/16-bit valuable): Dedicated baud rate generator: 3 channels A/D converter 10-bit resolution: 12 channels ...

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Ordering information (V850/SB1 (A versions)) Part Number µ PD703031AGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) µ PD703031AGF-xxx-3BA 100-pin plastic QFP (14 × 20) µ PD703031AYGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) µ PD703031AYGF-xxx-3BA 100-pin plastic ...

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... P102/RTP2/KR2/A7 21 P103/RTP3/KR3/A8 22 P104/RTP4/KR4/A9 23 P105/RTP5/KR5/A10 24 P106/RTP6/KR6/A11 µ PD703031A, 703031AY, 703033A, 703033AY): Connect directly to V Notes 1. ( µ PD70F3033A, 70F3033AY): Connect SCL0, SCL1, SDA0, and SDA1 are available only in the µ PD703031AY, 703033AY, and 70F3033AY CHAPTER 1 INTRODUCTION • µ PD70F3033AGC-8EU • ...

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... P105/RTP5/KR5/A10 27 P106/RTP6/KR6/A11 28 P107/RTP7/KR7/A12 29 P110/WAIT/ µ PD703031A, 703031AY, 703032A, 703032AY, 703033A, 703033AY): Notes 1. Connect directly µ PD70F3032A, 70F3032AY, 70F3033A, 70F3033AY Connect normal operation mode. SS SCL0, SCL1, SDA0, and SDA1 are available only in the µ PD703031AY, 703032AY, 703033AY, 2. 70F3032AY, and 70F3033AY. ...

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... Data strobe EV : Power supply for port Ground for port SS HLDAK: Hold acknowledge HLDRQ: Hold request IC: Internally connected INTP0 to INTP6: Interrupt request from peripherals KR0 to KR7 Key return : LBEN: Lower byte enable NMI: Non-maskable interrupt request P00 to P07: Port 0 P10 to P15: Port 1 ...

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Function blocks (V850/SB1 (A versions)) (1) Internal block diagram NMI INTC INTP0 to INTP6 TI00,TI01, TI10,TI11 Timer/counter TO0,TO1 16-bit timer: TM0, TM1 TI2/TO2 8-bit timer: TI3/TO3 TM2 to TM7 TI4/TO4 TI5/TO5 SIO SO0 2 CSI0/I C0 Note 3 SI0/SDA0 ...

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Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits × ...

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... The two-channel 8-bit timer/event counter can be connected via a cascade to enable use as a 16-bit timer. The two-channel 8-bit interval timer can be connected via a cascade to enable to be used as a 16-bit timer. (h) Watch timer This timer counts the reference time period (0.5 seconds) for counting the clock (the 32.768 kHz subclock or the main clock) ...

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Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port I/O Port 0 8-bit I/O Port 1 6-bit I/O Port 2 8-bit I/O Port 3 8-bit I/O Port 4 8-bit I/O Port 5 ...

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Serial interface (SIO) Asynchronous serial interface (UART) Clocked serial interface (CSI bus interface (I 70F3030BY, 70F3032BY, and 70F3033BY) 8-/16-bit variable-length serial interface CSI/UART: CSI/I CSI (8-/16-bit valuable): Dedicated baud rate generator: 3 channels A/D converter 10-bit resolution: ...

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Ordering information (V850/SB1 (B versions)) Part Number µ PD703031BGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) µ PD703031BGF-xxx-3BA 100-pin plastic QFP (14 × 20) µ PD703031BYGC-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) µ PD703031BYGF-xxx-3BA 100-pin plastic ...

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... P103/RTP3/KR3/A8 22 P104/RTP4/KR4/A9 23 P105/RTP5/KR5/A10 24 P106/RTP6/KR6/A11 µ PD703030B, 703030BY, 703031B, 703031BY, 703033B, 703033BY): Connect directly to V Notes 1. ( µ PD70F3030B, 70F3030BY, 70F3033B, 70F3033BY): Connect SCL0, SCL1, SDA0, and SDA1 are available only in the 703030BY, µ PD703031BY, 703033BY, 2. 70F3030BY, and 70F3033BY. 46 CHAPTER 1 INTRODUCTION • ...

Page 47

... P106/RTP6/KR6/A11 28 P107/RTP7/KR7/A12 29 P110/WAIT/ µ PD703030B, 703030BY, 703031B, 703031BY, 703032B, 703032BY, 703033B, 703033BY): Notes 1. Connect directly µ PD70F3030B, 70F3030BY, 70F3032B, 70F3032BY, 70F3033B, 70F3033BY Connect normal operation mode. SS SCL0, SCL1, SDA0, and SDA1 are available only in the µ PD703030BY, 703031BY, 703032BY, 2 ...

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Function blocks (V850/SB1 (B versions)) (1) Internal block diagram NMI INTC INTP0 to INTP6 TI00,TI01, TI10,TI11 Timer/counter TO0,TO1 16-bit timer: TM0, TM1 TI2/TO2 8-bit timer: TI3/TO3 TM2 to TM7 TI4/TO4 TI5/TO5 SIO SO0 2 CSI0/I C0 Note 3 SI0/SDA0 ...

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Real-time output port (RTP) The RTP is a real-time output function that transfers preset 8-bit data to an output latch when an external trigger signal occurs or when there is a match signal in a timer compare register. It ...

Page 53

... Total: 83 (12 input ports and 71 I/O ports interface enabled Timer/counter 16-bit timer: 2 channels (PWM output) 8-bit timer: 6 channels (four PWM outputs, cascade connection enabled) Watch timer When operating under subclock or main clock: 1 channel Operation using the subclock or main clock is also possible in the IDLE mode. ...

Page 54

I C bus interface (I (only for µ PD703034AY, 703035AY, 703037AY, 70F3035AY, and 70F3037AY) 8-/16-bit variable-length serial interface CSI/UART: CSI/I CSI (8-/16-bit valuable): Dedicated baud rate generator: 3 channels A/D converter 10-bit resolution: 12 channels Internal RAM ←→ on-chip ...

Page 55

Ordering information (V850/SB2 (A versions)) Part Number µ 100-pin plastic LQFP (fine pitch) (14 × 14) PD703034AGC-xxx-8EU µ 100-pin plastic QFP (14 × 20) PD703034AGF-xxx-3BA µ 100-pin plastic LQFP (fine pitch) (14 × 14) PD703034AYGC-xxx-8EU µ 100-pin plastic QFP ...

Page 56

... P102/RTP2/KR2/A7 21 P103/RTP3/KR3/A8 22 P104/RTP4/KR4/A9/IERX 23 P105/RTP5/KR5/A10/IETX 24 P106/RTP6/KR6/A11 µ PD703034A, 703034AY, 703035A, 703035AY): Connect directly to V Notes 1. ( µ PD70F3035A, 70F3035AY): Connect SCL0, SCL1, SDA0, and SDA1 are available only in the µ PD703034AY, 703035AY, and 70F3035AY CHAPTER 1 INTRODUCTION • µ PD70F3035AGC-8EU • ...

Page 57

... P104/RTP4/KR4/A9/IERX 26 P105/RTP5/KR5/A10/IETX 27 P106/RTP6/KR6/A11 28 P107/RTP7/KR7/A12 29 P110/WAIT/ µ PD703034A, 703034AY, 703035A, 703035AY, 703037A, 703037AY): Connect directly to V Notes 1. ( µ PD70F3035A, 70F3035AY, 70F3037A, 70F3037AY Connect normal operation mode. SS SCL0, SCL1, SDA0, and SDA1 are available only in the µ PD703034AY, 703035AY, 703037AY, 2. ...

Page 58

... EV : Power supply for port Ground for port SS HLDAK: Hold acknowledge HLDRQ: Hold request IC: Internally connected IERX: IEBus receive data IETX: IEBus transmit data INTP0 to INTP6: Interrupt request from peripherals KR0 to KR7 Key return : LBEN: Lower byte enable NMI: Non-maskable interrupt request ...

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Function blocks (V850/SB2 (A versions)) (1) Internal block diagram NMI INTC INTP0 to INTP6 TI00,TI01, TI10,TI11 Timer/counter TO0,TO1 16-bit timer: TM0, TM1 TI2/TO2 8-bit timer: TI3/TO3 TM2 to TM7 TI4/TO4 TI5/TO5 SIO SO0 2 CSI0/I C0 Note 3 SI0/SDA0 ...

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Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port I/O Port Function Port 0 8-bit I/O General- purpose port Port 1 6-bit I/O Port 2 8-bit I/O Port 3 8-bit I/O Port ...

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... I/O lines Total: 83 (12 input ports and 71 I/O ports interface enabled Timer/counter 16-bit timer: 2 channels (PWM output) 8-bit timer: 6 channels (four PWM outputs, cascade connection enabled) CHAPTER 1 INTRODUCTION 39 sources ( µ PD703034B, 703035B, 703036H, 703037H, 70F3035B, 70F3036H, 70F3037H) 40 sources ( µ PD703034BY, 703035BY, 703036HY, ...

Page 64

Watch timer When operating under subclock or main clock: 1 channel Operation using the subclock or main clock is also possible in the IDLE mode. Watchdog timer 1 channel Serial interface (SIO) Asynchronous serial interface (UART) Clocked serial interface (CSI) ...

Page 65

Ordering information (V850/SB2 (B and H versions)) Part Number µ 100-pin plastic LQFP (fine pitch) (14 × 14) PD703034BGC-xxx-8EU µ 100-pin plastic QFP (14 × 20) PD703034BGF-xxx-3BA µ 100-pin plastic LQFP (fine pitch) (14 × 14) PD703034BYGC-xxx-8EU µ 100-pin ...

Page 66

... P103/RTP3/KR3/A8 22 P104/RTP4/KR4/A9/IERX 23 P105/RTP5/KR5/A10/IETX 24 P106/RTP6/KR6/A11 µ PD703034B, 703034BY, 703035B, 703035BY, 703036H, 703036HY): Connect directly to V Notes 1. ( µ PD70F3035B, 70F3035BY, 70F3036H, 70F3036HY): Connect SCL0, SCL1, SDA0, and SDA1 are available only in the µ PD703034BY, 703035BY, 703036HY, 2. 70F3035BY, and 70F3036HY. ...

Page 67

... P106/RTP6/KR6/A11 28 P107/RTP7/KR7/A12 29 P110/WAIT/ µ PD703034B, 703034BY, 703035B, 703035BY, 703036H, 703036HY, 703037H, 703037HY): Notes 1. Connect directly µ PD70F3035B, 70F3035BY, 70F3036H, 70F3036HY, 70F3037H, 70F3037HY Connect normal operation mode. SS SCL0, SCL1, SDA0, and SDA1 are available only in the µ PD703034BY, 703035BY, 703036HY, 2 ...

Page 68

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Function blocks (V850/SB2 (B and H versions)) (1) Internal block diagram NMI INTC INTP0 to INTP6 TI00,TI01, TI10,TI11 Timer/counter TO0,TO1 16-bit timer: TM0, TM1 TI2/TO2 8-bit timer: TI3/TO3 TM2 to TM7 TI4/TO4 TI5/TO5 SIO SO0 2 CSI0/I C0 Note ...

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List of Pin Functions The names and functions of the pins of the V850/SB1 and V850/SB2 are described below divided into port pins and non-port pins. There are three types of power supplies for the pin I/O buffers: AV ...

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Port pins Pin Name I/O PULL P00 I/O Yes Port 0 P01 P02 P03 P04 P05 P06 P07 P10 I/O Yes Port 1 P11 P12 P13 P14 P15 P20 I/O Yes Port 2 P21 P22 P23 P24 P25 P26 ...

Page 75

Pin Name I/O PULL P30 I/O Yes Port 3 P31 P32 P33 P34 P35 P36 P37 P40 I/O No Port 4 P41 P42 P43 P44 P45 P46 P47 P50 I/O No Port 5 P51 P52 P53 P54 P55 P56 P57 ...

Page 76

Pin Name I/O PULL P70 Input No Port 7 P71 P72 P73 P74 P75 P76 P77 P80 Input No Port 8 P81 P82 P83 P90 I/O No Port 9 P91 P92 P93 P94 P95 P96 P100 I/O Yes Port 10 ...

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Non-port pins Pin Name I/O PULL A1 Output Yes Lower address bus used for external memory expansion A10 A11, A12 A13 A14 A15 A16 to A21 Output No Higher address bus used ...

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... NMI Input Yes Non-maskable interrupt request input (analog noise elimination) RD Output No Read strobe signal output − − REGC Capacitor connection for regulator output stabilization − RESET Input System reset input RTP0 to RTP3 Output Yes Real-time output port RTP4 RTP5 RTP6, RTP7 ...

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... WRH Output No Higher byte write strobe signal output for external data bus WRL Lower byte write strobe signal output for external data bus X1 Input No Resonator connection for main clock − X2 XT1 Input No Resonator connection for subclock − XT2 Remark PULL: On-chip pull-up resistor ...

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Pin States The operating states of various pins are described below with reference to their operating modes. Table 2-3. Operating States of Pins in Each Operating Mode Operating State Reset Pin AD0 to AD15 Hi A15 Hi-Z ...

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Description of Pin Functions (1) P00 to P07 (Port 0) ··· 3-state I/O P00 to P07 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P00 to P07 can also function as ...

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P10 to P15 (Port 1) ··· 3-state I/O P10 to P15 constitute a 6-bit I/O port that can be set to input or output in 1-bit units. P10 to P15 can also function as input or output pins for ...

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P20 to P27 (Port 2) ··· 3-state I/O P20 to P27 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P20 to P27 can also function as input or output pins for ...

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P30 to P37 (Port 3) ··· 3-state I/O P30 to P37 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P30 to P37 can also function as input or output pins for ...

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P40 to P47 (Port 4) ··· 3-state I/O P40 to P47 constitute an 8-bit I/O port that can be set to input or output pins in 1-bit units. P40 to P47 can also function as a time division address/data ...

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... ANI0 to ANI11 (Analog input 0 to 11) ··· input These are analog input pins for the A/D converter. Connect a capacitor between these pins and AV not apply voltage that is outside the range for AV the A/D converter possible for noise above the AV these pins using a diode that has a small V ...

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P90 to P96 (Port 9) ··· 3-state I/O P90 to P96 constitute a 7-bit I/O port that can be set to input or output pins in 1-bit units. P90 to P96 can also function as control signal output pins ...

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ASTB (Address strobe) ··· output This is an output pin for the external address bus’s latch strobe signal. Output becomes active (low level) in synchronization with the falling edge of the clock during the T1 state of the bus ...

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P100 to P107 (Port 10) ··· 3-state I/O P100 to P107 constitute an 8-bit I/O port that can be set to input or output in 1-bit units. P100 to P107 can also function as a real-time output port, an ...

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... CLKOUT (Clock out) … output This pin outputs the bus clock generated internally. (15) X1, X2 (Crystal) These pins are used to connect the resonator that generates the main clock. (16) XT1, XT2 (Crystal for subclock) These pins are used to connect the resonator that generates the subclock. ...

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... This is the positive power supply pin used for flash memory programming mode. This pin is used in the flash memory versions. In normal operation mode, connect directly to V (27) IC (Internally connected) This is an internally connected pin used in the mask ROM versions. Be sure to connect directly to V CHAPTER 2 PIN FUNCTIONS pins should be connected to a positive power supply ...

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... Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins Pin Alternate Function Supply P00 NMI P01 to P04 INTP0 to INTP3 P05 INTP4/ADTRG P06 INTP5/RTPTRG P07 INTP6 P10 SI0/SDA0 P11 SO0 P12 SCK0/SCL0 P13 SI1/RXD0 P14 SO1/TXD0 P15 SCK1/ASCK0 P20 SI2/SDA1 P21 ...

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... Connect to V via a resistor SS − 16 Leave open − − Connect − − Connect directly to V − − − − − − − − − − − − − − User’s Manual U13850EJ6V0UD (2/ via a resistor ...

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Pin I/O Circuits Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 4 Data Output disable Push-pull output that can be set for high impedance output (both P-ch and N-ch off). Type 5 Data Output disable Input enable 94 ...

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Type 10-A Pullup enable Data P-ch Open drain N-ch Output disable Type 16 Feedback cut-off P-ch XT2 XT1 CHAPTER 2 PIN FUNCTIONS Type Pullup P-ch enable V DD Data IN/OUT Open drain Output disable User’s Manual U13850EJ6V0UD ...

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The CPU of the V850/SB1 and V850/SB2 is based on RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline. 3.1 Features • Minimum instruction execution time V850/SB1 (A version, B version (@20 ...

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CPU Register Set The CPU registers of the V850/SB1 and V850/SB2 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers are 32 bits wide. For details, refer to ...

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Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers r31, are available. Any of these registers can be used as a data variable or address variable. ...

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System register set System registers control the status of the CPU and hold interrupt information. No. System Register Name 0 EIPC Interrupt status saving registers 1 EIPSW 2 FEPC NMI status saving registers 3 FEPSW 4 ECR Interrupt source ...

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Program status word (PSW) After reset: 00000020H 31 PSW RFU Reserved field (fixed to 0 NMI servicing not under execution. 1 NMI servicing under execution. This flag is set (1) when an NMI is acknowledged, and disables ...

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Note S 0 The operation result was positive The operation result was negative The operation result was not 0. 1 The operation result was 0. Note The result of a saturation-processed operation is determined by ...

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... ROM, and instruction processing written in the internal ROM is started. However, external expansion mode that connects external device to external memory area is enabled by setting in the memory expansion mode register (MM) by instruction. (2) Flash memory programming mode This mode is provided only in the flash memory versions ...

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Address Space 3.4.1 CPU address space The CPUs of the V850/SB1 and V850/SB2 are of 32-bit architecture and support linear address space (data space) during operand addressing (data access). When referencing instruction addresses, linear ...

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Image The core CPU supports “virtual” addressing space, or 256 memory blocks, each containing 16 MB memory locations. In actuality, the same 16 MB block is accessed regardless of the values of bits ...

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Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid. Even if a carry or borrow ...

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Memory map The V850/SB1 and V850/SB2 reserve areas as shown below. xxFFFFFFH xxFFF000H xxFFEFFFH xxFF8000H xxFF7FFFH xx100000H xx0FFFFFH xx000000H 106 CHAPTER 3 CPU FUNCTIONS Figure 3-6. Memory Map Single-chip mode Single-chip mode (external expansion mode) On-chip peripheral On-chip peripheral ...

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Area (1) Internal ROM/flash memory area An area maximum is reserved for the internal ROM/flash memory area. (a) V850/SB1 ( µ µ µ µ PD703031A, 703031AY, 703031B, 703031BY) V850/SB2 ( µ µ µ µ PD703034A, 703034AY, ...

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V850/SB1 ( µ µ µ µ PD703030B, 703030BY, 70F3030B, 70F3030BY) V850/SB2 ( µ µ µ µ PD703036H, 703036HY, 70F3036H, 70F3036HY) 384 KB are available for the addresses xx000000H to xx05FFFFH. Addresses xx060000H to xx0FFFFFH are an access-prohibited area Figure ...

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Interrupt/exception table The V850/SB1 and V850/SB2 increase the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. The collection of these handler addresses is called an interrupt/exception table, which is located in the internal ROM area. When an interrupt/exception ...

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Internal RAM area An area maximum is reserved for the internal RAM area. (a) V850/SB1 ( µ µ µ µ PD703031B, 703031BY), V850/SB2 ( µ µ µ µ PD703034B, 703034BY are available for the ...

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V850/SB1 ( µ µ µ µ PD703033A, 703033AY, 70F3033A, 70F3033AY, 703033B, 703033BY, 70F3033B, 70F3033BY) V850/SB2 ( µ µ µ µ PD703035A, 703035AY, 70F3035A, 70F3035AY, 703035B, 703035BY, 70F3035B, 70F3035BY are available for the addresses xxFFB000H to xxFFEFFFH. Addresses ...

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On-chip peripheral I/O area area of addresses FFF000H to FFFFFFH is reserved as an on-chip peripheral I/O area. The V850/SB1 and V850/SB2 are provided with area of addresses FFF000H to FFF3FFH as a ...

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External memory The V850/SB1 and V850/SB2 can use an area (xx100000H to xxFF7FFFH) for external memory accesses (in single-chip mode: external expansion 256 physical external ...

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... External expansion mode The V850/SB1 and V850/SB2 allow external devices to be connected to the external memory space by using the pins of ports and 9. To connect an external device, the port pins must be set in the external expansion mode by using the memory expansion mode register (MM). ...

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... This register sets the mode of each pin of ports and 9. In the external expansion mode, an external device can be connected to the external memory area MB. However, the external device cannot be connected to the internal RAM area, on-chip peripheral I/O area, and internal ROM area in the single-chip mode (and even if the external device is connected physically, it cannot be accessed) ...

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Memory address output mode register (MAM) Sets the mode of ports 3, 10, and 11. Separate output can be set for the address bus (A1 to A15) in the external expansion mode. The MAM register can be written in ...

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... To enhance the efficiency of using the pointer in connection with the memory maps of the V850/SB1 and V850/SB2, the following points are recommended: (1) Program space Of the 32 bits of the PC (program counter), the higher 8 bits are fixed to 0, and only the lower 24 bits are valid ...

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Figure 3-19. Recommended Memory Map (Flash Memory Version) Program space FFFFFFFFH FFFFF400H FFFFF3FFH FFFFF000H FFFFEFFFH FFFF8000H FFFF7FFFH FF800000H FF7FFFFFH 01000000H 00FFFFFFH 00FFF000H 00FFEFFFH 00FF8000H 00FF7FFFH 16 MB 00800000H 007FFFFFH 00100000H 8 MB 000FFFFFH 00040000H 0003FFFFH 00000000H Note This area cannot ...

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Peripheral I/O registers Address Function Register Name FFFFF000H Port 0 FFFFF002H Port 1 FFFFF004H Port 2 FFFFF006H Port 3 FFFFF008H Port 4 FFFFF00AH Port 5 FFFFF00CH Port 6 FFFFF00EH Port 7 FFFFF010H Port 8 FFFFF012H Port 9 FFFFF014H Port ...

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Address Function Register Name FFFFF096H Pull-up resistor option register 11 FFFFF0A2H Port 1 function register FFFFF0A4H Port 2 function register FFFFF0A6H Port 3 function register FFFFF0B4H Port 10 function register FFFFF0C0H Rising edge specification register 0 FFFFF0C2H Falling edge specification ...

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Address Function Register Name FFFFF140H Interrupt control register Note FFFFF142H Interrupt control register Note FFFFF144H Interrupt control register FFFFF146H Interrupt control register FFFFF148H Interrupt control register FFFFF14AH Interrupt control register FFFFF14CH Interrupt control register FFFFF14EH Interrupt control register FFFFF150H Interrupt ...

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... FFFFF240H 8-bit counter 2 FFFFF242H 8-bit compare register 2 FFFFF244H Timer clock selection register 20 FFFFF246H 8-bit timer mode control register 2 FFFFF24AH 16-bit counter 23 (during cascade connection only) FFFFF24CH 16-bit compare register 23 (during cascade connection only) FFFFF24EH Timer clock selection register 21 FFFFF250H 8-bit counter 3 ...

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... FFFFF280H 8-bit counter 6 FFFFF282H 8-bit compare register 6 FFFFF284H Timer clock selection register 60 FFFFF286H 8-bit timer mode control register 6 FFFFF28AH 16-bit counter 67 (during cascade connection only) FFFFF28CH 16-bit compare register 67 (during cascade connection only) FFFFF28EH Timer clock selection register 61 FFFFF290H 8-bit counter 7 ...

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Address Function Register Name FFFFF2E2H Variable-length serial control register 4 FFFFF2E4H Variable-length serial setting register 4 FFFFF2E6H Baud rate generator source clock selection register 4 FFFFF2E8H Baud rate generator output clock selection register 4 FFFFF300H Asynchronous serial interface mode register ...

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Address Function Register Name FFFFF366H Watch timer high-speed clock selection Note 1 register FFFFF36CH Correction control register FFFFF36EH Correction request register FFFFF370H Correction address register 0 FFFFF374H Correction address register 1 FFFFF378H Correction address register 2 FFFFF37CH Correction address register ...

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... Bit manipulation instruction (SET1/CLR1/NOT1 instruction) <5> Return the PSW NP bit to 0 (interrupt disable canceled). <6> Insert the NOP instructions (5 instructions). <7> If necessary, enable DMA operation. No special sequence is required when reading the specific registers. Cautions interrupt request or a DMA request is accepted between the time PRCMD is generated (< ...

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Command register (PRCMD) The command register (PRCMD register used when write-accessing the specific register to prevent incorrect writing to the specific registers due to the erroneous program execution. This register can be written in 8-bit units. It ...

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... Address bus (capable of separate output) • 16-bit data bus • Able to be connected to external devices via the pins that have alternate functions as ports • Wait function • Programmable wait function, capable of inserting wait states per 2 blocks • External wait control through WAIT pin input • ...

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... Caution In the V850/SB1 and V850/SB2, when using port I/O port, set the BIC bit of the system control register (SYC Note that the BIC bit is 0 after system reset. 4.3 Bus Access 4.3.1 Number of access clocks The number of basic clocks necessary for accessing each resource is as follows. Bus Cycle Type Internal ROM (32 Bits) ...

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Bus width The CPU carries out peripheral I/O access and external memory access in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each access. (1) Byte access (8 bits) Byte access is divided into two types, ...

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Memory Block Function The 16 MB memory space is divided into memory blocks units. The programmable wait function and bus cycle operation mode can be independently controlled for every two memory blocks. FFFFFFH F00000H EFFFFFH E00000H ...

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Wait Function 4.5.1 Programmable wait function To facilitate interfacing with low-speed memories and I/O devices data waits can be inserted in a bus cycle that starts every two memory blocks. The number of waits can be ...

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... External wait function When an extremely slow device, I/O, or asynchronous system is connected, any number of wait states can be inserted in the bus cycle by sampling the external wait pin (WAIT) to synchronize with the external device. The external wait signal is data wait only, and does not affect the access times of the internal ROM, internal RAM, and on-chip peripheral I/O areas, similar to programmable wait ...

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Idle State Insertion Function To facilitate interfacing with low-speed memory devices and meeting the data output float delay time on memory read accesses every two blocks, one idle state (TI) can be inserted into the current bus cycle after ...

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... The bus hold status can be recognized by the HLDAK pin becoming active (low). This feature can be used to design a system where two or more bus masters exist, such as when a multi- processor configuration is used and when a DMA controller is connected. A bus hold request is not acknowledged between the first and the second word access, and between the read access and write access of the read-modify-write access executed using a bit manipulation instruction ...

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Bus hold procedure The procedure of the bus hold function is illustrated below. <1>HLDRQ = 0 acknowledged <2>All bus cycle start requests held pending <3>End of current bus cycle <4>Bus idle status <5>HLDAK = 0 <6>HLDRQ = 1 acknowledged ...

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Bus Timing The V850/SB1 and V850/SB2 can execute read/write control for an external device using the following two modes. • Mode using DSTB, R/W, LBEN, UBEN, and ASTB signals • Mode using RD, WRL, WRH, and ASTB signals Set ...

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CLKOUT (output) A16 to A21 (output A15 (output) AD0 to AD15 (I/O) ASTB (output) R/W (output) H WRH, WRL (output) DSTB, RD (output) UBEN, LBEN (output) WAIT (input) Remarks 1. indicates the sampling timing when the number of ...

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CHAPTER 4 CLKOUT (output) A16 to A21 (output A15 (output) Address AD0 to AD15 (I/O) ASTB (output) R/W (output) H WRH, WRL (output) DSTB, RD (output) UBEN, LBEN (output) WAIT (input) Remarks 1. indicates the sampling timing when ...

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CLKOUT (output) A16 to A21 (output A15 (output) AD0 to AD15 (I/O) Address ASTB (output) R/W (output) H WRH, WRL (output) DSTB, RD (output) UBEN, LBEN (output) WAIT (input) Remarks 1. indicates the sampling timing when the number ...

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CHAPTER 4 Figure 4-9. Memory Write (1/2) CLKOUT (output) A16 to A21 (output A15 (output) AD0 to AD15 (I/O) ASTB (output) R/W (output) RD (output) DSTB (output) WRH, WRL (output) UBEN, LBEN (output) WAIT (input) Note AD0 to ...

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CLKOUT (output) A16 to A21 (output A15 (output) AD0 to AD15 (I/O) ASTB (output) R/W (output (output) DSTB (output) WRH, WRL (output) UBEN, LBEN (output) WAIT (input) Note AD0 to AD7 output invalid data when odd-address ...

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T2 CLKOUT (output) HLDRQ (input) HLDAK (output) A16 to A21 (output) Address A1 to A15 (output) AD0 to AD15 (I/O) Address ASTB (output) R/W (output) DSTB, RD, WRH, WRL (output) UBEN, LBEN (output) WAIT (input) Notes 1. If the HLDRQ ...

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Bus Priority There are four external bus cycles: bus hold, memory access, instruction fetch (branch), and instruction fetch (continuous). The bus hold cycle is given the highest priority, followed by memory access, instruction fetch (branch), and instruction fetch (continuous) ...

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Memory Boundary Operation Conditions 4.10.1 Program space (1) Do not execute a branch to the on-chip peripheral I/O area or continuous fetch from the internal RAM area to the peripheral I/O area branch or instruction fetch is ...

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CHAPTER 5 5.1 Outline The V850/SB1 and V850/SB2 are provided with a dedicated interrupt controller (INTC) for interrupt servicing and realize a high-powered interrupt function that can service interrupt requests from a total sources. An interrupt ...

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CHAPTER 5 Type Classifi- Default Name cation Priority − Reset Interrupt RESET − Non- Interrupt NMI maskable − Interrupt INTWDT − Note 1 Software Exception TRAP0n exception − Note 1 Exception TRAP1n − Exception Exception ILGOP trap Maskable Interrupt 0 ...

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CHAPTER 5 Type Classifi- Default Name cation Priority Maskable Interrupt 23 INTCSI2 24 INTIIC1 25 INTSER1 26 INTSR1/ INTCSI3 27 INTST1 28 INTCSI4 Note 2 29 INTIE1 Note 2 30 INTIE2 31 INTAD 32 INTDMA0 33 INTDMA1 34 INTDMA2 35 ...

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CHAPTER 5 5.2 Non-Maskable Interrupt A non-maskable interrupt is acknowledged unconditionally, even when interrupts are disabled (DI state). An NMI is not subject to priority control and takes precedence over all other interrupts. The following two non-maskable interrupt requests are ...

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CHAPTER 5 5.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes exception ...

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CHAPTER 5 Figure 5-2. Acknowledging Non-Maskable Interrupt Request ( new NMI request is generated while an NMI service routine is being executed: Main routine NMI request ( new NMI request is generated twice while an NMI ...

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... Caution When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during non- maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by the RETI instruction necessary to set PSW.EP back to 0 and PSW.NP back to 1 using the LDSR instruction immediately before the RETI instruction. ...

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CHAPTER 5 5.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt (NMI) servicing is under execution. This flag is set when an NMI interrupt request has been acknowledged, and masks all interrupt requests to ...

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CHAPTER 5 5.2.5 Edge detection function of NMI pin The NMI pin valid edge can be selected from the following four types: falling edge, rising edge, both edges, or neither edge. Rising edge specification register 0 (EGP0) and falling edge ...

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... To use multiple interrupts necessary to save EIPC and EIPSW to memory or a register before executing the EI instruction, and restore EIPC and EIPSW to the original values by executing the DI instruction before the RETI instruction ...

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CHAPTER 5 INTC accepted CPU processing 156 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-4. Maskable Interrupt Servicing INT input Yes Mask PSW Interrupt enable mode? Yes Priority higher than No that of interrupt currently serviced? Yes Priority ...

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... Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by the RETI instruction necessary to set PSW.EP back to 0 and PSW.NP back to 0 using the LDSR instruction immediately before the RETI instruction. ...

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CHAPTER 5 5.3.3 Priorities of maskable interrupts The V850/SB1 and V850/SB2 provide multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of ...

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CHAPTER 5 Figure 5-6. Example of Multiple Interrupt Servicing (1/2) Main routine EI Interrupt Interrupt request a request b (level 3) (level 2) Interrupt request c Interrupt request d (level 3) (level 2) Interrupt request e Interrupt request f (level ...

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CHAPTER 5 Figure 5-6. Example of Multiple Interrupt Servicing (2/2) Main routine EI Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request k (level 1) Interrupt request m (level 3) Interrupt request l Interrupt request n (level ...

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CHAPTER 5 Figure 5-7. Example of Servicing Interrupt Requests Generated Simultaneously Main routine EI Interrupt request a (level 2) Note 1 Interrupt request b (level 1) Note 2 Interrupt request c (level 1) Notes 1. Higher default priority 2. Lower ...

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CHAPTER 5 5.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. The interrupt control register can be read/written in 8-bit or 1-bit units. Cautions ...

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CHAPTER 5 After reset: 47H R/W Symbol <7> <6> xxICn xxIFn xxMKn xxIFn 0 Interrupt request not generated 1 Interrupt request generated xxMKn 0 Interrupt servicing enabled 1 Interrupt servicing disabled (pending) xxPRn2 xxPRn1 xxPRn0 ...

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CHAPTER 5 The address and bits of each interrupt control register are as follows. Table 5-2. Interrupt Control Register (xxICn) Address Register <7> FFFFF100H WDTIC WDTIF FFFFF102H PIC0 PIF0 FFFFF104H PIC1 PIF1 FFFFF106H PIC2 PIF2 FFFFF108H PIC3 PIF3 FFFFF10AH PIC4 ...

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CHAPTER 5 5.3.5 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt is set ...

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CHAPTER 5 5.3.7 Watchdog timer mode register (WDTM) This register can be read/written in 8-bit or 1-bit units (for details, refer to CHAPTER 9 WATCHDOG TIMER). After reset: 00H R/W Symbol <7> 6 WDTM RUN 0 RUN 0 Count operation ...

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CHAPTER 5 (3) Noise elimination of INTP6 pin The INTP6 pin incorporates a digital noise eliminator. The sampling clock for digital sampling can be selected from among /64, f /128 (a) Noise ...

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CHAPTER 5 5.3.9 Edge detection function The valid edges of the INTP0 to INTP6 pins can be selected for each pin from the following four types. • Rising edge • Falling edge • Both rising and falling edges • Neither ...

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CHAPTER 5 5.4 Software Exceptions A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. • TRAP instruction format: TRAP vector (where vector 1FH) For details of the instruction function, ...

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... Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during the software exception process, in order to restore the PC and PSW correctly during recovery by the RETI instruction necessary to set PSW.EP back to 1 using the LDSR instruction immediately before the RETI instruction. ...

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CHAPTER 5 5.4.3 EP flag The EP flag in the PSW is a status flag used to indicate that exception processing is in progress set when an exception occurs, and interrupts are disabled. After reset: 00000020H Symbol 31 ...

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CHAPTER 5 How the exception trap is processed is shown below. CPU processing 172 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-11. Exception Trap Processing Exception trap (ILGOP) occurs EIPC Restored PC EIPSW PSW ECR.EICC Exception code PSW.EP 1 PSW. 00000060H ...

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... Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during the exception trap process, in order to restore the PC and PSW correctly during recovery by the RETI instruction necessary to set PSW.EP back to 1 using the LDSR instruction immediately before the RETI instruction. ...

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CHAPTER 5 5.6 Priority Control 5.6.1 Priorities of interrupts and exceptions Table 5-3. Priorities of Interrupts and Exceptions RESET NMI INT TRAP ILGOP RESET: Reset NMI: Non-maskable interrupt INT: Maskable interrupt TRAP: Software exception ILGOP: Illegal opcode exception *: The ...

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CHAPTER 5 (1) To acknowledge maskable interrupts in service program Service program of maskable interrupt or exception ... ... • Save EIPC to memory or register • Save EIPSW to memory or register • EI instruction (enables interrupt acknowledgment) ... ...

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CHAPTER 5 Priorities the highest) can be programmed for each maskable interrupt request for multiple interrupt servicing control. To set a priority level, write values to the xxPRn0 to xxPRn2 bits of the interrupt request ...

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... MEM IFX IDX IFX INT1 INT2 INT3 External interrupt Time to eliminate noise (2 system clocks) is also necessary 13 for external interrupts, except when: 20 • In IDLE/STOP mode • External bus is accessed • Two or more interrupt request non-sample instructions are executed in succession • ...

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CHAPTER 5 5.8.1 Interrupt request valid timing after EI instruction When an interrupt request signal is generated (IF flag = 1) in the status in which the DI instruction is executed (interrupts disabled) and interrupts are not masked (MK flag ...

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... DI instruction before manipulation and EI instruction after manipulation. Alternatively, clear (0) the xxIF bit at the start of the interrupt servicing routine. When not using the DMA function, these manipulations are not necessary. Remark xx: Peripheral unit identification name (see Table 5-2) N: Peripheral unit number (see Table 5-2) ...

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CHAPTER 5 5.10 Key Interrupt Function Key interrupts can be generated by inputting a falling edge to the key input pins (KR0 to KR7) by setting the key return mode register (KRM). The key return mode register (KRM) includes 5 ...

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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-15. Key Return Block Diagram KR7 KR6 KR5 KR4 KR3 KR2 KR1 KR0 KRM7 KRM6 KRM5 KRM4 0 0 Key return mode register (KRM) User’s Manual U13850EJ6V0UD 0 KRM0 INTKR 181 ...

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CHAPTER 6 6.1 Outline The clock generator is a circuit that generates the clock pulses that are supplied to the CPU and peripheral hardware. There are two types of clock oscillators. (1) Main clock oscillator The oscillator of V850/SB1 has ...

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CHAPTER 6 6.2 Configuration FRC XT1 f Subclock XT oscillator XT2 X1 IDLE Main clock control oscillator X2 STP, MCK CLKOUT 6.3 Clock Output Function This function outputs the CPU clock via the CLKOUT pin. When clock output is enabled, ...

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CHAPTER 6 6.3.1 Control registers (1) Processor clock control register (PCC) This is a specific register. It can be written to only when a specified combination of sequences is used (see 3.4.9 Specific registers). This register can be read/written in ...

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CHAPTER 6 (a) Example of main clock operation → → → → subclock operation setup <1> CK2 ← 1: Bit manipulation instructions are recommended. Do not change CK1 and CK0. <2> Subclock operation: The maximum number of the following instructions ...

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CHAPTER 6 (2) Power save control register (PSC) This is a specific register. It can be written to only when a specified combination of sequences is used. For details, see 3.4.9 Specific registers. This register can be read/written in 8-bit ...

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CHAPTER 6 (3) Oscillation stabilization time selection register (OSTS) This register can be read/written in 8-bit units. After reset: 04H R OSTS 0 0 OSTS2 OSTS1 Other than ...

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CHAPTER 6 6.4 Power Save Functions 6.4.1 Outline This product provides the following power saving functions. These modes can be combined and switched to suit the target application, which enables effective implementation of low-power systems. (1) HALT mode When in ...

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CHAPTER 6 6.4.2 HALT mode (1) Settings and operating states In this mode, the clock’s oscillator continues to operate but the CPU’s operating clock is stopped. A clock continues to be supplied for other on-chip peripheral functions to maintain operation ...

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CHAPTER 6 Table 6-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting Item CPU Stopped ROM correction Stopped Clock generator Oscillation for main clock and subclock Clock supply to CPU is stopped 16-bit timer (TM0) Operating 16-bit timer (TM1) ...

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CHAPTER 6 Table 6-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting Item When Subclock Does Not Exist Port function Held External bus interface Only bus hold function operates External NMI Operating interrupt INTP0 to INTP3 Operating request INTP4 ...

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CHAPTER 6 6.4.3 IDLE mode (1) Settings and operating states This mode stops the entire system except the watch timer by stopping the on-chip main clock supply while the clock oscillator is still operating. Supply to the subclock continues. When ...

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CHAPTER 6 Table 6-2. Operating Statuses in IDLE Mode (2/2) IDLE Mode Settings Item External bus interface Stopped External NMI Operating interrupt INTP0 to INTP3 Operating request INTP4 and INTP5 Stopped INTP6 Operates when f clock Key return Operating In ...

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CHAPTER 6 6.4.4 Software STOP mode (1) Settings and operating states This mode stops the entire system by stopping the main clock oscillator to stop supplying the internal main clock. The subclock oscillator continues operating and the on-chip subclock supply ...

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CHAPTER 6 Table 6-3. Operating Statuses in Software STOP Mode (2/2) Mode Settings Item DMA0 to DMA5 Stopped Real-time output Operates when INTTM4 or INTTM5 has been selected (when TM4 or TM5 is operating) Port function Held External bus interface ...

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CHAPTER 6 6.5 Oscillation Stabilization Time The following shows the methods for specifying the length of the oscillation stabilization time required to stabilize the oscillator following release of STOP mode. (1) Release by non-maskable interrupt or by unmasked interrupt request ...

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... Clear the interrupt disabled state (re-set the NP bit of the PSW register to 0). <6> Insert NOP instructions ( instructions). <7> If DMA operation is necessary, enable DMA operation. Cautions 1. Insert two NOP instructions if the ID bit value of the PSW is not changed by the execution of the instruction that clears the NP bit to 0 (<5>), and insert five NOP instructions (<6> changed. ...

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CHAPTER 6 (2) While an instruction is being executed on external ROM If the V850/SB1 or V850/SB2 is used under the following conditions, the address indicated by the program counter (PC) differs from the address that actually reads an instruction ...

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CHAPTER 6 [Example of prevention program] LDSR rx, 5 ST.B r0, PRCMD[r0] ST.B rD, PSC[r0] LDSR rY, 5 NOP NOP NOP NOP NOP BR $+2 Remark It is assumed that the following values have already been set: rD: PSC set ...

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CHAPTER 7 7.1 16-Bit Timer (TM0, TM1) 7.1.1 Outline • 16-bit capture/compare registers: 2 (CRn0, CRn1) • Independent capture/trigger inputs: 2 (TIn0, TIn1) • Support of output of capture/match interrupt request signals (INTTMn0, INTTMn1) • Event input (shared with TIn0) ...

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