HD64F3064BF25 Renesas Electronics Corporation., HD64F3064BF25 Datasheet
HD64F3064BF25
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HD64F3064BF25 Summary of contents
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REJ09B0215-0600 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 Rev. 6.00 Revision Date: Mar ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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The H8/3062 Group is a high-performance single-chip microcomputer that integrates peripheral functions necessary for system configuration with an H8/300H CPU featuring a 32-bit internal architecture as its core. The on-chip peripheral functions include ROM, RAM, 16-bit timers, 8-bit timers, a ...
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User's Manuals on the H8/3062: Document Title H8/3062 Hardware Manual H8/300H Series Software Manual Users manuals for development tools: Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor Compiler Package User’s Manual H8S, H8/300 Series High-performance Embedded Workshop ...
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Comparison of H8/3062 Group Product Specifications There are 11 members of the H8/3062 Group: the H8/3062F-ZTAT R-mask version, H8/3062F-ZTAT B-mask version, and H8/3064F-ZTAT B-mask version (all with on-chip flash memory), and the H8/3062 masked ROM version, H8/3061 masked ROM version, ...
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H8/3062 Masked ROM Version, H8/3062F-ZTAT H8/3061 Masked R-Mask Version ROM Version, H8/3060 Masked ROM Version ROM size 128 kbytes H8/3062: 128 kbytes H8/3061: 96 kbytes H8/3060: 64 kbytes Address Address update mode selectable output See section 6.3.5, ...
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Main Revisions for this Edition Item Page All 22 1.4.2 Differences between H8/3062F- ZTAT R-Mask Version and H8/3064F-ZTAT B- Mask Version Table 1.5 Differences between H8/3062F-ZTAT, H8/3062F-ZTAT R- Mask Version, and On-Chip Masked ROM Versions Table 1.6 24 Differences in ...
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Rev. 6.00 Mar 18, 2005 page x of xlviii ...
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Section 1 Overview ............................................................................................................. 1.1 Overview........................................................................................................................... 1.2 Block Diagram.................................................................................................................. 1.3 Pin Description ................................................................................................................. 1.3.1 Pin Arrangement.................................................................................................. 1.3.2 Pin Functions ....................................................................................................... 13 1.3.3 Pin Assignments in Each Mode ........................................................................... 18 1.4 Notes on H8/3062F-ZTAT R-Mask Version .................................................................... 22 1.4.1 Pin Arrangement.................................................................................................. ...
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Instruction Set Overview ..................................................................................... 40 2.6.2 Instructions and Addressing Modes..................................................................... 41 2.6.3 Tables of Instructions Classified by Function...................................................... 42 2.6.4 Basic Instruction Formats .................................................................................... 51 2.6.5 Notes on Use of Bit Manipulation Instructions ................................................... 52 2.7 Addressing Modes and ...
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Section 4 Exception Handling 4.1 Overview........................................................................................................................... 87 4.1.1 Exception Handling Types and Priority............................................................... 87 4.1.2 Exception Handling Operation ............................................................................ 87 4.1.3 Exception Vector Table ....................................................................................... 88 4.2 Reset90 4.2.1 Overview.............................................................................................................. 90 4.2.2 Reset Sequence .................................................................................................... 90 4.2.3 Interrupts after Reset............................................................................................ ...
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Section 6 Bus Controller 6.1 Overview........................................................................................................................... 125 6.1.1 Features................................................................................................................ 125 6.1.2 Block Diagram..................................................................................................... 126 6.1.3 Pin Configuration ................................................................................................ 127 6.1.4 Register Configuration......................................................................................... 128 6.2 Register Descriptions........................................................................................................ 129 6.2.1 Bus Width Control Register (ABWCR)............................................................... 129 6.2.2 Access State Control Register (ASTCR) ...
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Register Descriptions........................................................................................... 174 7.3 Port 2................................................................................................................................. 176 7.3.1 Overview.............................................................................................................. 176 7.3.2 Register Descriptions........................................................................................... 177 7.4 Port 3................................................................................................................................. 180 7.4.1 Overview.............................................................................................................. 180 7.4.2 Register Descriptions........................................................................................... 180 7.5 Port 4................................................................................................................................. 182 7.5.1 Overview.............................................................................................................. 182 7.5.2 Register Descriptions........................................................................................... 183 7.6 Port 5................................................................................................................................. ...
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Timer Synchro Register (TSNC) ......................................................................... 235 8.2.3 Timer Mode Register (TMDR)............................................................................ 237 8.2.4 Timer Interrupt Status Register A (TISRA)......................................................... 240 8.2.5 Timer Interrupt Status Register B (TISRB) ......................................................... 243 8.2.6 Timer Interrupt Status Register C (TISRC) ......................................................... 246 8.2.7 ...
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Operation .......................................................................................................................... 311 9.4.1 8TCNT Count Timing ......................................................................................... 311 9.4.2 Compare Match Timing....................................................................................... 312 9.4.3 Input Capture Signal Timing ............................................................................... 313 9.4.4 Timing of Status Flag Setting .............................................................................. 314 9.4.5 Operation with Cascaded Connection.................................................................. 316 9.4.6 Input Capture Setting........................................................................................... ...
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Operation .......................................................................................................................... 350 10.3.1 Overview.............................................................................................................. 350 10.3.2 Output Timing ..................................................................................................... 351 10.3.3 Normal TPC Output............................................................................................. 352 10.3.4 Non-Overlapping TPC Output............................................................................. 354 10.3.5 TPC Output Triggering by Input Capture............................................................ 356 10.4 Usage Notes ...................................................................................................................... 357 10.4.1 Operation of TPC Output ...
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Serial Mode Register (SMR) ............................................................................... 380 12.2.6 Serial Control Register (SCR) ............................................................................. 384 12.2.7 Serial Status Register (SSR) ................................................................................ 389 12.2.8 Bit Rate Register (BRR) ...................................................................................... 395 12.3 Operation .......................................................................................................................... 403 12.3.1 Overview.............................................................................................................. 403 12.3.2 Operation in Asynchronous Mode ...
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A/D Data Registers (ADDRA to ADDRD) ............................................. 469 14.2.2 A/D Control/Status Register (ADCSR) ............................................................... 470 14.2.3 A/D Control Register (ADCR) ............................................................................ 472 14.3 CPU Interface ................................................................................................................... 473 14.4 Operation .......................................................................................................................... 475 14.4.1 Single Mode (SCAN = ...
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Flash Memory Register Descriptions................................................................................ 503 17.3.1 Flash Memory Control Register (FLMCR) ......................................................... 503 17.3.2 Erase Block Register (EBR) ................................................................................ 507 17.3.3 RAM Control Register (RAMCR)....................................................................... 508 17.3.4 Flash Memory Status Register (FLMSR) ............................................................ 510 17.4 On-Board Programming Mode ......................................................................................... ...
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Register Descriptions........................................................................................................ 552 18.3.1 Flash Memory Control Register 1 (FLMCR1) .................................................... 552 18.3.2 Flash Memory Control Register 2 (FLMCR2) .................................................... 556 18.3.3 Erase Block Register 1 (EBR1) ........................................................................... 557 18.3.4 Erase Block Register 2 (EBR2) ........................................................................... 557 18.3.5 RAM ...
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Differences from H8/3062F-ZTAT R-Mask Version and H8/3062F-ZTAT B-Mask Version................................................................................................... 602 19.2 Features............................................................................................................................. 603 19.2.1 Block Diagram..................................................................................................... 604 19.2.2 Pin Configuration ................................................................................................ 605 19.2.3 Register Configuration......................................................................................... 605 19.3 Register Descriptions........................................................................................................ 606 19.3.1 Flash Memory Control Register 1 (FLMCR1) .................................................... 606 ...
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Section 20 Clock Pulse Generator 20.1 Overview........................................................................................................................... 655 20.1.1 Block Diagram..................................................................................................... 656 20.2 Oscillator Circuit .............................................................................................................. 656 20.2.1 Connecting a Crystal Resonator .......................................................................... 656 20.2.2 External Clock Input............................................................................................ 659 20.3 Duty Adjustment Circuit................................................................................................... 662 20.4 Prescalers .......................................................................................................................... 662 20.5 Frequency ...
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Section 22 Electrical Characteristics 22.1 Electrical Characteristics of H8/3062 Masked ROM Version, H8/3061 Masked ROM Version, and H8/3060 Masked ROM Version ........................... 682 22.1.1 Absolute Maximum Ratings ................................................................................ 682 22.1.2 DC Characteristics ............................................................................................... 683 22.1.3 AC Characteristics ............................................................................................... 694 22.1.4 ...
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A/D Conversion Characteristics .......................................................................... 781 22.6.5 D/A Conversion Characteristics .......................................................................... 782 22.7 Operational Timing........................................................................................................... 783 22.7.1 Clock Timing ....................................................................................................... 783 22.7.2 Control Signal Timing ......................................................................................... 784 22.7.3 Bus Timing .......................................................................................................... 785 22.7.4 TPC and I/O Port Timing..................................................................................... 789 22.7.5 ...
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Appendix D Pin States ........................................................................................................ 949 D.1 Port States in Each Mode.................................................................................................. 949 D.2 Pin States at Reset............................................................................................................. 954 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix F Product Code Lineup Appendix G Package Dimensions ...
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Section 1 Overview Figure 1.1 Block Diagram..................................................................................................... Figure 1.2 Pin Arrangement of H8/3062F-ZTAT R-Mask Version, H8/3062 Masked ROM Version, H8/3061 Masked ROM Version, and H8/3060 Masked ROM Version (FP-100B or TFP-100B Package, Top View)............................................................................................................ Figure 1.3 Pin Arrangement of H8/3062F-ZTAT ...
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Figure 2.15 On-Chip Memory Access Cycle .......................................................................... 65 Figure 2.16 Pin States during On-Chip Memory Access (Address Update Mode 1).............. 66 Figure 2.17 Access Cycle for On-Chip Supporting Modules.................................................. 66 Figure 2.18 Pin States during Access to On-Chip Supporting Modules ...
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Figure 6.3 Memory Map in 16-Mbyte Mode (H8/3062F-ZTAT R-Mask Version, H8/3062F-ZTAT B-Mask Version, H8/3062 Masked ROM Version, H8/3061 Masked ROM Version, H8/3062 Masked ROM B-Mask Version, H8/3061 Masked ROM B-Mask Version) (1) ..................................................... 142 Figure 6.3 Memory Map in 16-Mbyte ...
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Figure 7.3 Port 3 Pin Configuration...................................................................................... 180 Figure 7.4 Port 4 Pin Configuration...................................................................................... 182 Figure 7.5 Port 5 Pin Configuration...................................................................................... 186 Figure 7.6 Port 6 Pin Configuration...................................................................................... 190 Figure 7.7 Port 7 Pin Configuration...................................................................................... 194 Figure 7.8 Port 8 Pin ...
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Figure 8.30 Operation in Phase Counting Mode (Example) ................................................... 274 Figure 8.31 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode............... 274 Figure 8.32 Timing for Setting 16-Bit Timer Output Level by Writing to TOLR .................. 275 Figure 8.33 ...
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Figure 9.22 Contention between Counter Clearing by Input Capture and Counter Increment ............................................................................................................. 326 Figure 9.23 Contention between TCOR Write and Input Capture .......................................... 327 Figure 9.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode . 328 ...
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Figure 12.9 Example of Communication among Processors using Multiprocessor Format (Sending Data H'AA to Receiving Processor A) ................................................. 416 Figure 12.10 Sample Flowchart for Transmitting Multiprocessor Serial Data ......................... 417 Figure 12.11 Example of SCI Transmit Operation (8-Bit Data with ...
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Figure 14.4 Example of A/D Converter Operation (Scan Mode, Channels AN Selected) .............................................................................................................. 478 Figure 14.5 A/D Conversion Timing ...................................................................................... 479 Figure 14.6 External Trigger Input Timing............................................................................. 480 Figure 14.7 Example of Analog Input Protection Circuit ....................................................... 482 Figure 14.8 ...
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Section 18 H8/3064 Internal Voltage Step-Down Version ROM [H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version] Figure 18.1 Block Diagram of Flash Memory ........................................................................ 550 Figure 18.2 Flash Memory Related State Transitions............................................................. 561 Figure 18.3 Reading Overlap RAM Data in ...
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Figure 19.13 Flash Memory State Transitions (When High Level is Applied to FWE Pin in Mode (On-Chip ROM Enabled))........................................................... 640 Figure 19.14 Example of RAM Overlap Operation .................................................................. 641 Figure 19.15 Memory Map in PROM Mode............................................................................. 644 ...
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Figure 22.15 Output Load Circuit............................................................................................. 765 Figure 22.16 Darlington Pair Drive Circuit (Example)............................................................. 774 Figure 22.17 Sample LED Circuit ............................................................................................ 774 Figure 22.18 Output Load Circuit............................................................................................. 780 Figure 22.19 Oscillator Settling Timing.................................................................................... 783 Figure 22.20 Reset Input Timing .............................................................................................. 784 ...
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Figure C.9 (f) Port 9 Block Diagram (Pin P9 Figure C.10 (a) Port A Block Diagram (Pins PA Figure C.10 (b) Port A Block Diagram (Pins PA Figure C.10 (c) Port A Block Diagram (Pins PA Figure C.11 (a) Port ...
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Section 1 Overview Table 1.1 Features................................................................................................................ Table 1.2 Comparison of H8/3062 Group Pin Arrangements.............................................. Table 1.3 Pin Functions ....................................................................................................... 13 Table 1.4 Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A) .................. 18 Table 1.5 Differences between H8/3062F-ZTAT R-Mask Version ...
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Section 5 Interrupt Controller Table 5.1 Interrupt Pins ....................................................................................................... 101 Table 5.2 Interrupt Controller Registers .............................................................................. 101 Table 5.3 Interrupt Sources, Vector Addresses, and Priority............................................... 113 Table 5.4 UE, I, and UI Bit Settings and Interrupt Handling............................................... 116 Table 5.5 ...
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Section 8 16-Bit Timer Table 8.1 16-bit timer Functions.......................................................................................... 228 Table 8.2 16-bit timer Pins .................................................................................................. 232 Table 8.3 16-bit timer Registers .......................................................................................... 233 Table 8.4 PWM Output Pins and Registers ......................................................................... 270 Table 8.5 Up/Down Counting Conditions ........................................................................... 274 ...
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Table 12.9 SMR and SCR Settings and SCI Clock Source Selection.................................... 405 Table 12.10 Serial Communication Formats (Asynchronous Mode) ...................................... 407 Table 12.11 Receive Error Conditions .................................................................................... 414 Table 12.12 SCI Interrupt Sources .......................................................................................... 431 Table 12.13 SSR Status Flags ...
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Table 17.8 Hardware Protection ............................................................................................ 528 Table 17.9 Software Protection ............................................................................................. 530 Table 17.10 H8/3062F-ZTAT R-Mask Version Socket Adapter Product Codes .................... 536 Section 18 H8/3064 Internal Voltage Step-Down Version ROM [H8/3064F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version] Table ...
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Table 20.2 Crystal Resonator Parameters.............................................................................. 658 Table 20.3 (1) Clock Timing for On-Chip Flash Memory Versions ........................................... 660 Table 20.3 (2) Clock Timing for On-Chip Masked ROM Versions............................................ 661 Table 20.4 Frequency Division Register ............................................................................... 663 Table 20.5 Comparison of ...
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Table 22.24 Clock Timing ....................................................................................................... 731 Table 22.25 Control Signal Timing ......................................................................................... 732 Table 22.26 Bus Timing .......................................................................................................... 733 Table 22.27 Timing of On-Chip Supporting Modules............................................................. 735 Table 22.28 A/D Conversion Characteristics .......................................................................... 737 Table 22.29 D/A Conversion Characteristics .......................................................................... ...
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Table A.2 Operation Code Map (3)...................................................................................... 808 Table A.3 Number of States per Cycle ................................................................................. 810 Table A.4 Number of Cycles per Instruction........................................................................ 811 Appendix B Internal I/O Registers Table B.1 Comparison of H8/3062 Group Internal I/O Register Specifications .................. ...
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Rev. 6.00 Mar 18, 2005 page xlviii of xlviii ...
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Overview The H8/3062 Group is a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Renesas architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, ...
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Section 1 Overview Table 1.1 Features Feature Description CPU Upward-compatible with the H8/300 CPU at the object-code level General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers plus eight 16-bit registers eight 32-bit registers) High-speed ...
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Feature Description Memory H8/3062F-ZTAT R-mask version H8/3062F-ZTAT B-mask version H8/3062 (masked ROM version) H8/3062 masked ROM B-mask version H8/3061 (masked ROM version) H8/3061 masked ROM B-mask version H8/3060 (masked ROM version) H8/3060 masked ROM B-mask version H8/3064F-ZTAT B-mask version H8/3064 ...
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Section 1 Overview Feature Description 8-bit timer, 8-bit up-counter (external event count capability) 4 channels Two time constant registers Two channels can be connected Programmable Maximum 16-bit pulse output, using 16-bit timer as time base timing pattern Up to four ...
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Feature Description Operating Seven MCU operating modes modes Mode Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 On-chip ROM is disabled in modes the versions with on-chip flash memory, an ...
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Section 1 Overview Feature Description Product lineup Product Type H8/3062F-ZTAT R-mask version H8/3062 masked ROM version H8/3061 masked ROM version H8/3060 masked ROM version H8/3064F-ZTAT B-mask version H8/3064 masked ROM B-mask version H8/3062F-ZTAT B-mask version H8/3062 masked ROM B-mask version ...
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Block Diagram Figure 1.1 shows an internal block diagram EXTAL XTAL STBY RES *1 RESO/FWE NMI /P6 7 LWR/P6 6 HWR/P6 5 RD/P6 4 AS/P6 3 BACK/P6 2 BREQ/P6 1 WAIT/ ...
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Section 1 Overview 1.3 Pin Description 1.3.1 Pin Arrangement The pin arrangement of the H8/3062 Group is shown in figures 1.2 to 1.5. Differences in the H8/3062 Group pin arrangements are shown in table 1.2. The H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT ...
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REF /AN /DA 84 ...
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Section 1 Overview /AN / /AN /DA 1 ...
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REF /AN /DA 84 ...
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Section 1 Overview /AN / /AN /DA 1 ...
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Pin Functions Table 1.3 summarizes the pin functions. The H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 masked ROM B-mask version, H8/3062 masked ROM B-mask version, H8/3061 masked ROM B-mask version, and H8/3060 masked ROM B-mask version have a V ...
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Section 1 Overview Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Operating mode MD 0 control System control FWE ...
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Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Data bus 23 Bus control ...
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Section 1 Overview Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Program mable TP 100 timing pattern controller (TPC) Serial TxD , 13 communi- TxD 0 cation RxD , ...
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Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O I/O ports 23, 7 ...
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Section 1 Overview 1.3.3 Pin Assignments in Each Mode Table 1.4 lists the pin assignments in each mode. Table 1.4 Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A) Pin No. FP-100B TFP-100B FP-100A Mode ...
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Pin No. FP-100B TFP-100B FP-100A Mode ...
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Section 1 Overview Pin No. FP-100B TFP-100B FP-100A Mode ...
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Pin No. FP-100B TFP-100B FP-100A Mode ...
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Section 1 Overview 1.4 Notes on H8/3062F-ZTAT R-Mask Version Points to be noted when using the H8/3062F-ZTAT R-mask version are given below. 1.4.1 Pin Arrangement The H8/3062F-ZTAT R-mask version has the same pin arrangement as the H8/3062 masked ROM version, ...
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Notes on H8/3064F-ZTAT B-Mask Version, H8/3062F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version, H8/3062 Masked ROM B-Mask Version, H8/3061 Masked ROM B-Mask Version, and H8/3060 Masked ROM B-Mask Version The H8/3062 Group includes one model with 128-kbyte on-chip flash ...
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Section 1 Overview 1.5.2 Product Type Names and Markings Table 1.6 shows the product type names and differences in sample markings for the H8/3062F- ZTAT R-mask version, H8/3062F-ZTAT B-mask version, and H8/3064F-ZTAT B-mask version. Table 1.6 Differences in H8/3062F-ZTAT R-Mask ...
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V Pin CL The H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, and on-chip masked ROM B-mask versions have a V stabilization capacitor must be connected. The method of connecting the external capacitor is shown in figure 1.6. Do not connect ...
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Section 1 Overview 1.5.4 Notes on Changeover to On-Chip Masked ROM Versions and On-Chip Masked ROM B-Mask Versions (1) Care is required when changing from the H8/3062F-ZTAT B-mask version with on-chip flash memory to a model with on-chip masked ROM. ...
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Setting Oscillation Settling Wait Time When software standby mode is used, after exiting software standby mode a wait period must be provided to allow the clock to stabilize. Select the length of time for which the CPU and peripheral ...
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Section 1 Overview Rev. 6.00 Mar 18, 2005 page 28 of 970 REJ09B0215-0600 ...
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Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Section 2 CPU 25 MHz (H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 masked ROM B-mask version, H8/3062 masked ROM B-mask version, H8/3061 masked ROM B-mask version, and H8/3060 masked ROM B-mask version) 8/16/32-bit register-register add/subtract: 100 ns@20 MHz (80 ns@25 ...
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CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports Mbytes. CPU operating modes Normal mode Advanced mode Figure 2.1 CPU Operating ...
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Section 2 CPU 2.3 Address Space Figure 2.2 shows a simple memory map for the H8/3062 Group. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in ...
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Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 Control ...
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Section 2 CPU 2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as ...
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SP (ER7) 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR). Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length ...
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Section 2 CPU Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Stores the value of the most significant bit of data, regarded as the ...
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Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
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Section 2 CPU General Data Type Register Data Format Word data Rn 15 Word data En MSB 31 Longword data ERn MSB Legend: ERn : General register En : General register General register R MSB : Most ...
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Data Type 1-bit data Byte data Word data Longword data When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size. Address 7 Address Address ...
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Section 2 CPU 2.6 Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 64 types of instructions, which are classified in table 2.1. Table 2.1 Instruction Classification Function Instruction MOV, PUSH * Data transfer Arithmetic operations ADD, SUB, ADDX, ...
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Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Function Instruction Data MOV BWL BWL transfer POP, PUSH — — MOVFPE, — — MOVTPE Arithmetic ADD, CMP BWL ...
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Section 2 CPU 2.6.3 Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation General register (destination General register ...
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Table 2.3 Data Transfer Instructions Size * Instruction Function MOV B/W/L (EAs) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) Cannot be used in ...
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Section 2 CPU Table 2.4 Arithmetic Operation Instructions Size * Instruction Function ADD,SUB B/W/L Rd ± Rs Performs addition or subtraction on data in two general registers immediate data and data in a general register. (Immediate byte data ...
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Size * Instruction Function DIVXU B/W Rd ÷ Rs Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits quotient and 16-bit remainder DIVXS B/W Rd ÷ Rs Performs signed division on data in two ...
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Section 2 CPU Table 2.5 Logic Operation Instructions Size * Instruction Function AND B/W/L Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Performs a logical OR operation on ...
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Table 2.7 Bit Manipulation Instructions Size * Instruction Function BSET B 1 Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of ...
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Section 2 CPU Size * Instruction Function BOR B C (<bit-No.> of <EAd>) ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is ...
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Table 2.8 Branching Instructions Instruction Size Function Bcc — Branches to a specified address if address specified condition is met. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS Bcc (BHS) BCS (BLO) BNE BEQ BVC ...
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Section 2 CPU Table 2.9 System Control Instructions Size * Instruction Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to the power-down state. LDC B/W (EAs) Moves the source ...
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Table 2.10 Block Transfer Instruction Instruction Size Function EEPMOV.B — if R4L repeat until else next; EEPMOV.W — repeat until else next; Block transfer instruction. This instruction transfers the number of data bytes specified by R4L or R4, ...
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Section 2 CPU Operation field only Operation field and register fields op Operation field, register fields, and effective address extension op Operation field, effective address extension, and condition field op cc 2.6.5 Notes on Use of Bit Manipulation Instructions The ...
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Before Execution of BCLR Instruction Input/output Input Input DDR 0 0 Execution of BCLR Instruction BCLR #0, P4DDR ; Execute BCLR instruction on DDR After Execution of BCLR Instruction Input/output Output Output ...
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Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation 2.7.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use ...
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Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the ...
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Section 2 CPU 7. Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign- extended to 24 bits and added to the ...
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Section 2 CPU 2.8 Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby ...
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Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and ...
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Section 2 CPU End of bus release Bus-released state End of exception handling Exception-handling state RES = "High" *1 Reset state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes ...
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CPU sets both the I bit and the UI bit in the condition code register to 1. Then the CPU fetches a start address from the exception vector table and execution branches to that address. ...
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Section 2 CPU 2.8.6 Reset State When the input goes low all current processing stops and the CPU enters the reset state. The bit in the condition code register is set reset. ...
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Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock ( ). The interval from one rise of the system clock to the next rise is referred “state.” A memory cycle or ...
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Section 2 CPU Address bus AS RD HWR LWR , , , Figure 2.16 Pin States during On-Chip Memory Access (Address Update Mode 1) 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are ...
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Address bus AS RD HWR LWR , , , Figure 2.18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas ...
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Section 2 CPU Rev. 6.00 Mar 18, 2005 page 68 of 970 REJ09B0215-0600 ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8/3062 Group has seven operating modes (modes that are selected by the mode pins ( indicated in table 3.1. The input ...
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Section 3 MCU Operating Modes Mode externally expanded mode that enables access to external memory and peripheral devices and also enables access to the on-chip ROM. Mode 5 supports a maximum address space of 16 Mbytes. Modes ...
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Mode Control Register (MDCR) MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3062 Group. Bit 7 — Initial value 1 Read/Write — Note: * Determined by pins MD Bits 7 and 6—Reserved: These ...
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Section 3 MCU Operating Modes 3.3 System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3062 Group. Bit 7 SSBY STS2 Initial value 0 Read/Write R/W R/W Standby timer select These ...
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Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further information about software standby mode see section 21, Power-Down State.) When software standby mode is exited by an external interrupt, and a transition is made to normal operation, ...
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Section 3 MCU Operating Modes Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a user bit or an interrupt mask bit. Bit 3 UE Description 0 UI bit in CCR ...
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Operating Mode Descriptions 3.4.1 Mode 1 Ports 1, 2, and 5 function as address pins A address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas least one area ...
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Section 3 MCU Operating Modes reset is 8 bits, with 8-bit access to all areas least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits. 3.4.6 Mode 6 This mode operates ...
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Memory Map in Each Operating Mode Figures 3.1 to 3.4 show memory maps of the H8/3062 Group. In the expanded modes, the address space is divided into eight areas. The initial bus mode differs between modes 1 and 2, ...
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Section 3 MCU Operating Modes 3.6.2 Reserved Areas The H8/3062 Group memory map includes reserved areas to which access (reading or writing) is prohibited. Normal operation cannot be guaranteed if the following reserved areas are accessed. Reserved Area in Internal ...
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Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 External address Area 3 space H'7FFFF H'80000 Area 4 H'9FFFF H'A0000 Area ...
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Section 3 MCU Operating Modes Mode 5 (16-Mbyte expanded mode with on-chip ROM enabled) H'000000 Vector area H'0000FF On-chip ROM H'007FFF H'01FFFF H'020000 Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 Area 2 H'5FFFFF H'600000 External address Area 3 space ...
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Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 External address Area 3 space H'7FFFF H'80000 Area 4 H'9FFFF H'A0000 Area ...
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Section 3 MCU Operating Modes Mode 5 (16-Mbyte expanded mode with on-chip ROM enabled) H'000000 Vector area H'0000FF On-chip ROM (mask ROM) H'007FFF H'017FFF H'018000 *1 Reserved H'01FFFF H'020000 Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 Area 2 H'5FFFFF ...
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Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 External address Area 3 space H'7FFFF H'80000 Area 4 H'9FFFF H'A0000 Area ...
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Section 3 MCU Operating Modes Mode 5 (16-Mbyte expanded mode with on-chip ROM enabled) H'000000 Vector area H'0000FF On-chip ROM (mask ROM) H'007FFF H'00FFFF H'010000 *1 Reserved H'01FFFF H'020000 Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 Area 2 H'5FFFFF ...
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Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address H'7FFFF space H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'EE000 Internal I/O registers (1) H'EE0FF External ...
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Section 3 MCU Operating Modes Mode 5 (16-Mbyte expanded mode with on-chip ROM enabled) H'000000 Vector area H'0000FF On-chip ROM (flash memory) H'007FFF H'03FFFF H'040000 Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 Area 2 H'5FFFFF H'600000 External address Area ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. • Reset Exception • ...
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Table 4.2 Exception Vector Table Exception Source Reset Reserved for system use External interrupt (NMI) Trap instruction (4 sources) External interrupt IRQ 0 External interrupt IRQ 1 External interrupt IRQ 2 External interrupt IRQ 3 External interrupt IRQ 4 External ...
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Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset is the highest-priority exception. When the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules. Reset exception ...
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Figure 4.2 Reset Sequence (Modes 1 and 3) Section 4 Exception Handling Rev. 6.00 Mar 18, 2005 page 91 of 970 REJ09B0215-0600 ...
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Section 4 Exception Handling RES Address bus RD HWR , LWR High (1), (3) : Address of reset exception handling vector: (1) = H'000000, (3) = H'000002 (2), (4) : Start address (contents of reset ...
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RES Internal address bus Internal read signal Internal write signal High Internal data bus (16 bits wide) (1) : Address of reset exception handling vector (H'0000) (2) : Start address (contents of reset exception handling vector address) (3) : First ...
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Section 4 Exception Handling 4.3 Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ 27 internal sources in the on-chip supporting modules. Figure 4.5 classifies the interrupt sources and indicates the number of interrupts of each ...
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Stack Status after Exception Handling Figure 4.6 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP–4 SP–3 SP–2 SP–1 SP (ER7) Stack area Before exception handling SP–4 SP–3 SP–2 SP–1 SP (ER7) Stack ...
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Section 4 Exception Handling 4.6 Notes on Stack Usage When accessing word data or longword data, the H8/3062 Group regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the ...
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SP TRAPA instruction executed SP set to H'FFFEFF Legend: CCR : Condition code register PC : Program counter R1L : General register R1L SP : Stack pointer Note: The diagram illustrates modes Figure 4.7 Operation when SP ...
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Section 4 Exception Handling Rev. 6.00 Mar 18, 2005 page 98 of 970 REJ09B0215-0600 ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt ...
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Section 5 Interrupt Controller 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. ISCR NMI input IRQ input section ISR OVF TME . . . . . . . . . . TEI TEIE Interrupt controller ...
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Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Interrupt Pins Name Nonmaskable interrupt External interrupt request Note the versions with on-chip flash memory, NMI input is sometimes disabled. For details see 17.6.4, ...
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Section 5 Interrupt Controller SYSCR is initialized to H' reset and in hardware standby mode not initialized in software standby mode. Bit 7 SSBY STS2 Initial value 0 Read/Write R/W Software standby Bit 3—User Bit Enable ...
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Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRA7 IPRA6 Initial value 0 Read/Write R/W R/W Priority level A6 Selects the priority level of IRQ interrupt requests ...
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Section 5 Interrupt Controller Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ Bit 7 IPRA7 Description 0 IRQ interrupt requests have priority level 0 (low priority IRQ interrupt requests have priority level 1 (high priority) ...
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Bit 2—Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt requests. Bit 2 IPRA2 Description 0 16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (Initial value) 1 16-bit timer channel 0 ...
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Section 5 Interrupt Controller Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRB7 IPRB6 Initial value 0 Read/Write R/W R/W Priority level B6 Selects the priority level ...
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Bit 6—Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt requests. Bit 6 IPRB6 Description 0 8-bit timer channel 2 and 3 interrupt requests have priority level 0 (low priority) 1 8-bit timer channel ...
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Section 5 Interrupt Controller 5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ requests. Bit 7 — Initial value 0 Read/Write — Reserved bits Note: * Only 0 can be written, to ...
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IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ Bit 7 — — Initial value 0 Read/Write R/W R/W Reserved bits IER is initialized to H' reset and in hardware standby ...
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Section 5 Interrupt Controller 5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins Bit 7 ...
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Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ IRQ can be used to exit software standby mode. 2 NMI: NMI is the highest-priority interrupt and is ...
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Section 5 Interrupt Controller Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). IRQn input pin IRQnF Note Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector ...
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Table 5.3 Interrupt Sources, Vector Addresses, and Priority Interrupt Source Origin NMI External pins IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 Reserved — WOVI Watchdog (interval timer) timer Reserved — ADI (A/D end) A/D IMIA0 ...
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Section 5 Interrupt Controller Interrupt Source Origin IMIA2 16-bit timer (compare match/ channel 2 input capture A2) IMIB2 (compare match/ input capture B2) OVI2 (overflow 2) Reserved — CMIA0 8-bit timer channel 0/1 (compare match A0) CMIB0 (compare match B0) ...
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Interrupt Source Origin ERI0 SCI (receive error 0) channel 0 RXI0 (receive data full 0) TXI0 (transmit data empty 0) TEI0 (transmit end 0) ERI1 SCI (receive error 1) channel 1 RXI1 (receive data full 1) TXI1 (transmit data empty ...
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Section 5 Interrupt Controller 5.4 Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3062 Group handles interrupts differently depending on the setting of the UE bit. When interrupts are controlled by the I bit. When ...
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Program execution state Interrupt requested? Yes No Priority level 1? Yes No IRQ 0 Yes No IRQ 1 Yes TEI1 Yes Save PC and CCR Read vector address Branch to interrupt service routine Figure 5.4 Process Up to Interrupt Acceptance ...
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Section 5 Interrupt Controller If an interrupt condition occurs and the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. When the interrupt controller receives one or more interrupt requests, it selects ...
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All interrupts are unmasked I 0 Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5 flowchart showing how interrupts are accepted when interrupt condition occurs and the corresponding interrupt enable bit is ...
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Section 5 Interrupt Controller Priority level 1? IRQ 0 Yes IRQ Figure 5.6 Process Up to Interrupt Acceptance when Rev. 6.00 Mar 18, 2005 page 120 of 970 REJ09B0215-0600 Program execution state Interrupt requested? ...
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Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5.7 Interrupt Exception ...
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Section 5 Interrupt Controller 5.4.3 Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time No. Item ...
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Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed interrupt ...
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Section 5 Interrupt Controller 5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing ...
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Section 6 Bus Controller 6.1 Overview The H8/3062 Group has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set ...
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Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. Area Internal address bus decoder WAIT Internal signals CPU bus request signal CPU bus acknowledge signal Legend: ABWCR : Bus width control register ...
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Pin Configuration Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1 Bus Controller Pins Name Abbreviation Chip select Address strobe A S Read R D High write ...
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Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the bus controller’s registers. Table 6.2 Bus Controller Registers 1 Address * Name H'EE020 Bus width control register H'EE021 Access state control register H'EE022 Wait control register H H'EE023 Wait ...
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Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area. Bit 7 ABW7 Modes Initial value and 7 Read/Write R/W Initial ...
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Section 6 Bus Controller 6.2.2 Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states Bit AST7 AST6 Initial value 1 1 Read/Write R/W ...
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Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. On-chip memory and registers are accessed in a fixed number of states that ...
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Section 6 Bus Controller Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is ...
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WCRL 7 6 Bit W31 W30 Initial value 1 1 Read/Write R/W R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space ...
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Section 6 Bus Controller Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is ...
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Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A enables or disables release of the bus to an external device. Bit 7 A23E Modes Initial value ...
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Section 6 Bus Controller Bit 6—Address 22 Enable (A22E): Enables PA Writing 0 in this bit enables A be modified and PA has its ordinary port functions. 5 Bit 6 A22E Description the ...
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Bus Control Register (BCR Bit ICIS1 ICIS0 Initial value 1 1 Read/Write R/W R/W Note must not be written in bits BCR is an 8-bit readable/writable register that enables or disables idle ...
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Section 6 Bus Controller Bit 1—Area Division Unit Select (RDEA): Selects the memory map area division units. This bit is valid in modes 3, 4, and 5, and is invalid in modes and 7. Bit 1 RDEA ...
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Chip Select Control Register (CSCR) CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals ( output of a chip select signal corresponding pin functions ...
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Section 6 Bus Controller 6.2.7 Address Control Register (ADRCR) ADRCR is an 8-bit readable/writable register that selects either address update mode 1 or address update mode 2 as the address output method. Bit 7 6 — — Initial value 1 ...
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Operation 6.3.1 Area Division The external address space is divided into areas Each area has a size of 128 kbytes in the 1- Mbyte modes Mbytes in the 16-Mbyte modes. Figure 6.2 shows a ...
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Section 6 Bus Controller H'000000 H'1FFFFF H'200000 H'3FFFFF H'400000 H'5FFFFF H'600000 H'7FFFFF H'800000 H'9FFFFF H'A00000 H'BFFFFF H'C00000 H'DFFFFF H'E00000 H'FEE000 Internal I/O registers (1) H'FEE0FF H'FEE100 H'FF7FFF H'FF8000 H'FF8FFF H'FF9000 H'FFEF1F H'FFEF20 H'FFFEFF H'FFFF00 H'FFFF1F H'FFFF20 Internal I/O registers (2) ...
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H'000000 Area 0 2 Mbytes H'1FFFFF H'200000 Area 1 2 Mbytes H'3FFFFF H'400000 Area 2 2 Mbytes H'5FFFFF H'600000 Area 3 2 Mbytes H'7FFFFF H'800000 Area 4 2 Mbytes H'9FFFFF H'A00000 Area 5 2 Mbytes H'BFFFFF H'C00000 Area 6 2 ...
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Section 6 Bus Controller H'000000 H'1FFFFF H'200000 H'3FFFFF H'400000 H'5FFFFF H'600000 H'7FFFFF H'800000 H'9FFFFF H'A00000 H'BFFFFF H'C00000 H'DFFFFF H'E00000 H'FEE000 Internal I/O registers (1) H'FEE0FF H'FEE100 H'FF7FFF H'FF8000 H'FF8FFF H'FF9000 H'FFDF1F H'FFDF20 H'FFFEFF H'FFFF00 H'FFFF1F H'FFFF20 Internal I/O registers (2) ...
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Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and registers are fixed, and ...
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Section 6 Bus Controller Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH/WCRL ABWn ASTn Wn1 0 0 — — Note 6.3.3 Memory ...
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Chip Select Signals For each of areas the H8/3062 Group can output a chip select signal ( low when the corresponding area is selected in expanded mode. Figure 6.4 shows the output timing ...
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Section 6 Bus Controller 6.3.5 Address Output Method The H8/3062F-ZTAT R-mask version, H8/3062F-ZTAT B-mask version, H8/3062 masked ROM version, H8/3061 masked ROM version, H8/3060 masked ROM version, and H8/3064F-ZTAT B- mask version, H8/3064 masked ROM B-mask version, H8/3062 masked ROM ...
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When address update mode 2 is selected, the address in an internal space (on-chip memory or internal I/O) access cycle is not output externally. In order to secure address holding with respect to the rise of is used an external ...
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Section 6 Bus Controller 6.4 Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data ...
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Access Areas: Figure 6.8 illustrates data alignment control for 16-bit access areas. With 16-bit access areas, the upper data bus (D accesses. The amount of data that can be accessed at one time is one byte or one word, ...
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Section 6 Bus Controller Table 6.4 Data Buses Used and Valid Strobes Access Read/ Area Size Write Byte Read 8-bit access area Write Byte Read 16-bit access area Write Word Read Write Notes: 1. Undetermined data means that unpredictable data ...