UDA1341TS/N1 Motorola, UDA1341TS/N1 Datasheet
UDA1341TS/N1
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... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. " ...
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... Freescale Semiconductor, Inc. ii MC68302 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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... Internet: This access is provided by telneting to pirs.aus.sps.mot.com [129.38.233.1] or through the World Wide Web at http://pirs.aus.sps.mot.com. For questions or comments pertaining to technical information, questions, and applications, please contact one of the following sales offices nearest you. MOTOROLA For More Information On This Product, PREFACE — Sales Offices — ...
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... FULL LINE REPRESENTATIVES (303) 243-9658 (316) 838 0190 (702) 746 0642 (505) 298-7177 (801) 561-5099 (509) 924-2322 (541) 343-1787 (818) 768-7400 (512) 834-2022 (310) 594-4631 MOTOROLA ...
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... Byte Count Register (BCR) ..................................................................... 3-7 3.1.2.6 Channel Status Register (CSR) .............................................................. 3-7 3.1.3 Interface Signals ..................................................................................... 3-8 3.1.3.1 DREQ and DACK.................................................................................... 3-8 3.1.3.2 DONE...................................................................................................... 3-8 3.1.4 IDMA Operational Description................................................................. 3-9 3.1.4.1 Channel Initialization ............................................................................... 3-9 3.1.4.2 Data Transfer .......................................................................................... 3-9 MOTOROLA For More Information On This Product, Title Section 1 General Description Section 2 MC68000/MC68008 Core Section 3 MC68302 USER’S MANUAL Go to: www.freescale.com Page Number v ...
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... Timer Capture Registers (TCR1, TCR2)................................................3-39 3.5.2.4 Timer Counter (TCN1, TCN2)................................................................3-39 3.5.2.5 Timer Event Registers (TER1, TER2)....................................................3-39 3.5.2.6 General Purpose Timer Example...........................................................3-40 3.5.2.6.1 Timer Example 1....................................................................................3-40 3.5.2.6.2 Timer Example 2....................................................................................3-40 3.5.3 Timer 3 - Software Watchdog Timer ......................................................3-41 vi For More Information On This Product, Title MC68302 USER’S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... SDMA Channels...................................................................................... 4-3 4.3 Command Set ......................................................................................... 4-5 4.3.1 Command Execution Latency ................................................................. 4-7 4.4 Serial Channels Physical Interface.......................................................... 4-7 4.4.1 IDL Interface.......................................................................................... 4-11 4.4.2 GCI Interface ......................................................................................... 4-14 4.4.3 PCM Highway Mode.............................................................................. 4-16 4.4.4 Nonmultiplexed Serial Interface (NMSI) ................................................ 4-19 MOTOROLA For More Information On This Product, Title Section 4 MC68302 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number vii ...
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... Fractional Stop Bits................................................................................4-55 4.5.11.13 UART Mode Register.............................................................................4-56 4.5.11.14 UART Receive Buffer Descriptor (Rx BD) .............................................4-57 4.5.11.15 UART Transmit Buffer Descriptor (Tx BD).............................................4-61 4.5.11.16 UART Event Register.............................................................................4-63 4.5.11.17 UART MASK Register............................................................................4-65 4.5.11.18 S-Records Programming Example ........................................................4-65 4.5.12 HDLC Controller.....................................................................................4-66 viii For More Information On This Product, Title MC68302 USER’S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... DDCMP Transmit Buffer Descriptor (Tx BD)....................................... 4-112 4.5.14.12 DDCMP Event Register....................................................................... 4-114 4.5.14.13 DDCMP Mask Register ....................................................................... 4-115 4.5.15 V.110 Controller .................................................................................. 4-115 4.5.15.1 Bit Rate Adaption of Synchronous Data Signaling Rates up to 19.2 kbps.................................................................................... 4-116 MOTOROLA For More Information On This Product, Title MC68302 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number ix ...
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... SMC2 Receive Buffer Descriptor .........................................................4-142 4.7.4.4 SMC2 Transmit Buffer Descriptor ........................................................4-143 4.7.5 SMC Interrupt Requests ......................................................................4-143 5.1 Functional Groups....................................................................................5-1 5.2 Power Pins...............................................................................................5-2 5.3 Clocks ......................................................................................................5-4 5.4 System Control ........................................................................................5-5 5.5 Address Bus Pins (A23–A1) ....................................................................5-7 x For More Information On This Product, Title Section 5 Signal Description MC68302 USER’S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... AC Electrical Specifications—Serial Communications Port . ................ 6-29 6.19 AC Electrical Specifications—IDL Timing.............................................. 6-30 6.20 AC Electrical Specifications—GCI Timing............................................. 6-32 6.21 AC Electrical Specifications—PCM Timing ........................................... 6-34 6.22 AC Electrical Specifications—NMSI Timing .......................................... 6-36 MOTOROLA For More Information On This Product, Title Section 6 Electrical Characteristics MC68302 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number ...
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... Pin Grid Array (PGA) ...............................................................................7-4 7.2.2 Plastic Surface Mount (PQFP).................................................................7-5 7.2.3 Thin Surface Mount (TQFP).....................................................................7-6 7.3 Ordering Information ................................................................................7-7 Development Tools and Support B.1 Motorola Software Overview................................................................... B-1 B.2 Motorola Software Modules .................................................................... B-1 B.3 Third-Party Software Support ................................................................. B-6 B.4 In-Circuit Emulation Support ................................................................... B-6 B.5 302 Family ADS System ......................................................................... B-6 C.1 SS7 Protocol Support ............................................................................. C-2 C.2 Centronics Transmission Controller........................................................ C-2 C.3 Centronics Reception Controller ............................................................. C-3 C ...
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... MC145554 CODEC Filter......................................................................D-41 D.7 Interfacing a Master MC68302 to One or More Slave MC68302s ........D-41 D.7.1 Synchronous vs. Asynchronous Accesses............................................D-43 D.7.2 Clocking.................................................................................................D-43 D.7.3 Programming the Base Address Registers (BARs)...............................D-43 D.7.4 Dealing with Interrupts...........................................................................D-44 D.7.5 Arbitration ..............................................................................................D-44 MOTOROLA For More Information On This Product, Title MC68302 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number xiii ...
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... RFCR/TFCR—Rx Function Code/Tx Function Code.............................. E-9 E.1.1.3.2 MRBLR—Maximum Rx Buffer Length. ................................................. E-10 E.1.1.3.3 CRC Mask_L and CRC Mask_H........................................................... E-10 E.1.1.3.4 DISFC—Discard Frame Counter. ......................................................... E-10 E.1.1.3.5 CRCEC—CRC Error Counter. .............................................................. E-10 xiv For More Information On This Product, Title Appendix E SCC Programming Reference MC68302 USER’S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... PAREC—Receive Parity Error Counter. ...............................................E-24 E.2.1.3.6 FRMEC—Receive Framing Error Counter. ...........................................E-24 E.2.1.3.7 NOSEC—Receive Noise Counter. ........................................................E-24 E.2.1.3.8 BRKEC—Receive Break Condition Counter. ........................................ E-24 E.2.1.3.9 UADDR1 and UADDR2.........................................................................E-24 E.2.1.4 Receive Buffer Descriptors....................................................................E-25 E.2.1.4.1 Receive BD Control/Status Word. ......................................................... E-26 MOTOROLA For More Information On This Product, Title MC68302 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number xv ...
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... Transmit Buffer Pointer ......................................................................... E-40 E.3.2 Programming the SCC for Transparent ................................................ E-40 E.3.2.1 CP Initialization ..................................................................................... E-40 E.3.2.2 General and Transparent Protocol-Specific RAM Initialization ............. E-41 E.3.2.3 SCC Initialization................................................................................... E-41 E.3.2.4 SCC Operation...................................................................................... E-41 E.3.2.5 SCC Interrupt Handling......................................................................... E-41 xvi For More Information On This Product, Title Appendix F Design Checklist MC68302 USER’S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... Communications Processor (CP) Figure 4-1. Simplified CP Architecture.......................................................................... 4-2 Figure 4-2. Three Serial Data Flow Paths .................................................................... 4-4 Figure 4-3. NMSI Physical Interface ............................................................................. 4-8 Figure 4-4. Multiplexed Mode on SCC1 Opens Additional Configuration Possibilities................................................................................................. 4-9 MOTOROLA For More Information On This Product, LIST OF FIGURES Title Section 1 General Description Section 2 MC68000/MC68008 Core Section 3 Section 4 MC68302 USER’S MANUAL Go to: www ...
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... Figure 4-42. Transparent Receive Buffer Descriptor.................................................. 4-130 Figure 4-43. Transparent Transmit Buffer Descriptor................................................. 4-131 Figure 4-44. SCP Timing ............................................................................................ 4-135 Figure 4-45. SCP vs. SCC Pin Multiplexing ............................................................... 4-137 Figure 5-1. Functional Signal Groups........................................................................... 5-3 xviii For More Information On This Product, Title Section 5 Signal Description MC68302 USER’S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... Figure 6-20. IDL Timing Diagram ................................................................................. 6-31 Figure 6-21. GCI Timing Diagram................................................................................. 6-33 Figure 6-22. PCM Timing Diagram (SYNC Envelopes Data) ....................................... 6-35 Figure 6-23. PCM Timing Diagram (SYNC Prior to 8-Bit Data) .................................... 6-35 Figure 6-24. NMSI Timing Diagram .............................................................................. 6-37 MOTOROLA For More Information On This Product, Title Section 6 Electrical Characteristics MC68302 USER’S MANUAL Go to: www ...
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... Figure D-29. Routing Channels in PCM Envelope Mode..............................................D-61 Figure D-30. PCM Transmission Timing Technique .....................................................D-63 Figure D-31. SCP Timing ..............................................................................................D-69 Figure D-32. Local Talk Adaptor Board ........................................................................D-71 xx For More Information On This Product, Title Appendix B Appendix C RISC Microcode from RAM Appendix D MC68302 Applications MC68302 USER’S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... Table 4-6. SCC Parameter RAM Memory Map............................................................4-35 Table 4-7. UART Specific Parameter RAM..................................................................4-46 Table 4-8. HDLC-Specific Parameter RAM..................................................................4-69 Table 4-9. BISYNC Specific Parameter RAM ..............................................................4-86 Table 4-10. DDCMP Specific Parameter RAM ............................................................4-104 Table 4-11. Transparent-Specific Parameter RAM ......................................................4-125 MOTOROLA For More Information On This Product, LIST OF TABLES Title Section 2 MC68000/MC68008 Core ...
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... Transparent Protocol-Specific RAM for SCCx ..............................E-31 Table E-3 (c). SCCx Register Set ...............................................................................E-32 Table E-3 (d). General Registers (Only One Set) .......................................................E-32 xxii For More Information On This Product, Title Section 5 Signal Description Appendix D MC68302 Applications Appendix E SCC Programming Reference MC68302 USER’S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... SDLC is a trademark of International Business Machines. 2. DDCMP is a trademark of Digital Equipment Corporation. MOTOROLA For More Information On This Product V.110, or transparent operation. The IMP pro- MC68302 USER’S MANUAL Go to: www.freescale.com ...
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... STATIC RAM STATE LOGIC 3 TIMERS PARALLEL I/O PERIPHERAL BUS SMC (2) SCC1 SCC2 SERIAL CHANNELS PHYSICAL INTERFACE I/O PORTS AND PIN ASSIGNMENTS MC68302 USER’S MANUAL Go to: www.freescale.com MC68000 / MC68008 CORE SYSTEM AND WAIT- CONTROL CLOCK GENERATOR SYSTEM INTEGRATION BLOCK SCC3 SCP COMMUNICATIONS PROCESSOR MOTOROLA ...
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... Transparent Modes V.110 Rate Adaption —Six Serial DMA Channels for the Three SCCs —Flexible Physical Interface Accessible by SCCs Including: Motorola Interchip Digital Link (IDL) General Circuit Interface (GCI, also known as IOM Pulse Code Modulation (PCM) Highway Interface 3. IOM is a trademark of Siemens AG ...
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... RAM. If data resides in the dual-port RAM, then the CP accesses the RAM with one clock cycle and no arbitration delays. 1-4 For More Information On This Product, ROM DMA AND/ CPU I/F OR FIFOs SERIAL TIMERS CHANNELS MC68302 USER’S MANUAL Go to: www.freescale.com RAM ADDITIONAL DEVICES MOTOROLA ...
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... MC68302 can be programmed into the nonmultiplexed serial inter- face (NMSI) mode. This mode, which is available for one, two, or all three SCC ports, can be selected while the other ports use one of the multiplexed interface modes (IDL, GCI, or PCM highway). MOTOROLA For More Information On This Product, 1 GENERAL- 3 TIMERS ...
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... Other peripherals are also accessed and controlled through internal registers: the IDMA controller, the three timers, I/O ports, and the interrupt controller. 1-6 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... Freescale Semiconductor, Inc. Figure 1-4. NMSI Communications-Oriented Board Design MOTOROLA For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com General Description 1-7 ...
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... Freescale Semiconductor, Inc. General Description Figure 1-5. Basic Rate IDL Voice/Data Terminal in ISDN 1-8 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... In addition, the address registers may be used for word and long-word operations. All 16 registers may be used as index registers. MOTOROLA For More Information On This Product, NOTE MC68302 USER’ ...
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... CCR MC68302 USER’S MANUAL Go to: www.freescale.com DATA REGISTERS ADDRESS A3 REGISTERS USER STACK (USP) POINTER PROGRAM USER PC COUNTER MODE CONDITION CCR CODE REGISTER SUPERVISOR A7' STACK (SSP) POINTER SUPERVISOR MODE STATUS SR REGISTER MOTOROLA ...
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... The M68000 instruction set is shown in Table 2-2. Some basic instructions also have variations as shown in Table 2-3. Special emphasis has been placed on the instruction set to simplify programming and to support structured high-level languages. With a few exceptions, each instruction operates MOTOROLA For More Information On This Product, SYSTEM BYTE ...
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... For More Information On This Product, Mode (Next Word (Next Two Words (PC (PC (An (An (An (An) + (Xn DATA = Next Word(s) Inherent Data EA = SR, USP, SSP, PC MC68302 USER’S MANUAL Go to: www.freescale.com Generation (An) MOTOROLA ...
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... EXT Sign Extend JMP Jump JSR Jump to Subroutine LEA Load Effective Address LINK Link Stack LSL Logical Shift Left LSR Logical Shift Right MOTOROLA For More Information On This Product, Mnemonic MOVE MULS MULU NBCD NEG NOP NOT OR PEA RESET ROL ROR ...
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... Move from Status Register Move to Status Register Move to Condition Codes Move User Stack Pointer Negate Negate with Extend Logical OR OR Immediate OR Immediate to Condition Codes OR Immediate to Status Register Subtract Subtract Address Subtract Immediate Subtract Quick Subtract with Extend MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... The bus cycles generated by instructions executed in the supervisor state are classified as supervisor references. While the processor is in the supervisor privi- lege state, those instructions using either the system stack pointer implicitly or address reg- ister seven explicitly access the SSP. MOTOROLA For More Information On This Product, FC1 FC0 ...
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... Reset: Initial SSP 004 SP Reset: Initial PC 008 SD Bus Error 00C SD Address Error 010 SD Illegal Instruction 014 SD Zero Divide 018 SD CHK Instruction 01C SD TRAPV Instruction 020 SD Privilege Violation 024 SD Trace 028 SD Line 1010 Emulator MC68302 USER’S MANUAL Go to: www.freescale.com 2 2 MOTOROLA ...
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... NOTES: 1. Vector numbers 12–14, 16–23, and 48–63 are reserved for future enhancements by Motorola (with vectors 60–63 being used by the M68302 (see 2.7 MC68302 IMP Configuration and Control)). No user peripheral devices should be assigned these numbers. 2. Unlike the other vectors which only require two words, reset vector (0) requires four words and is located in the supervisor program space ...
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... ACCESS ADDRESS HIGH ACCESS ADDRESS LOW INSTRUCTION REGISTER STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW EVEN BYTE ODD BYTE 0 7 STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW NOTE MC68302 USER’S MANUAL Go to: www.freescale.com I HIGHER ADDRESS MOTOROLA ...
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... Two M6800 signals are omitted from the MC68302: valid memory address (VMA) and en- able (E). The valid peripheral address (VPA) signal is retained, but is only used on the MC68302 as AVEC to direct the core to use an autovector during interrupt acknowledge cy- cles. MOTOROLA For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com ...
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... For More Information On This Product, BAR ENTRY $3FF SCR ENTRY CKCR ENTRY RESERVED BAR POINTS TO THE BASE 4K BLOCK SYSTEM RAM (DUAL-PORT) $xxx000 = BASE (DUAL-PORT) INTERNAL REGISTERS $FFFFFF MC68302 USER’S MANUAL Go to: www.freescale.com SYSTEM MEMORY MAP $0 EXCEPTION VECTOR TABLE 256 VECTOR ENTRIES 4K BLOCK MOTOROLA ...
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... The address compare logic uses these bits, dependent upon the CFC bit, to cause an address match within its address space. Do not assign this field to the M68000 core interrupt acknowl- edge space (FC2–FC0 = 7). MOTOROLA For More Information On This Product, NOTE NOTE BASE ADDRESS ...
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... For More Information On This Product, Width Description 16 Reserved 16 Base Address Register 32 System Control Register 16 Reserved 16 Clock Control Register 32 Reserved Table 2-7. System RAM Width Block RAM User Data Memory MC68302 USER’S MANUAL Go to: www.freescale.com Reset Value BFFF 0000 0F00 0000 Description Reserved (Not Implemented) MOTOROLA ...
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... Base + 520 Base + 528 Base + 530 Base + 538 Base + 540 Base + 548 Base + 550 Base + 558 Base + 560 Base + 568 Base + 570 Base + 578 MOTOROLA For More Information On This Product, Table 2-8. Parameter RAM Width Block 4 Word SCC1 4 Word SCC1 4 Word SCC1 4 Word ...
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... MC68302 Revision Number SCC3 Specific Protocol Parameters SCC3 MC68302 USER’S MANUAL Go to: www.freescale.com Reserved (Not Implemented) RxBD0 RxBD1 RxBD2 RxBD3 RxBD4 RxBD5 RxBD6 RxBD7 TxBD0 TxBD1 TxBD2 TxBD3 ## Reserved RxBD TxBD RxBD TxBD Internal Use Rx/TxBD Reserved (Not Implemented) MOTOROLA ...
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... Base + 836 # OR1 16 Base + 838 # BR2 16 Base + 83A # OR2 16 Base + 83C # BR3 16 Base + 83E # OR3 16 MOTOROLA For More Information On This Product, NOTE Table 2-9. Internal Registers Block Description IDMA Reserved IDMA Channel Mode Register Source Address Pointer IDMA IDMA Destination Address Pointer IDMA ...
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... Reserved 8 8 SCC2 SCC2 Mask Register 8 SCC2 Reserved 8 SCC2 SCC2 Status Register 8 SCC2 Reserved SCC2 MC68302 USER’S MANUAL Go to: www.freescale.com 0000 FFFF 0000 0000 00 FFFF 0000 0000 FFFF 0000 0000 00 00 0004 0000 7E7E 0004 0000 7E7E MOTOROLA ...
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... This RST bit will reset that entire block, including any event registers contained therein. Examples clear bit 0 of SCCE1, execute "MOVE.B #$01,SCCE1" MOTOROLA For More Information On This Product, Table 2-9. Internal Registers SCC3 ...
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... Thus bit is a one when read, it will be written back with a one, clearing that bit. For example, the in- struction “BSET.B #0,SCCE1” will actually clear ALL bits in SCCE1, not just bit 0. 2-20 For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... Watchdog for Monitoring Bus Activity —Low-Power (Standby) Modes —Freeze Control for Debugging • Clock Control —Adjustable CLKO Drive —Three-state RCLK1 and TCLK1 —Disable BRG1 • DRAM Refresh Controller MOTOROLA For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com 3-1 ...
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... If the IMP frequency is 16.0 MHz and zero wait state memory is used, then the maximum transfer rate is 4M byte/sec. This assumes that the operand size is 16-bits, the source and destination addresses are even, and the bus width is selected to be 16-bits. 3-2 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... Figure 3-1. IDMA Controller Block Diagram 3.1.2 IDMA Registers (Independent DMA Controller) The IDMA has six registers that define its specific operation. These registers include a 32- bit source address pointer register (SAPR), a 32-bit destination address pointer register MOTOROLA For More Information On This Product, 2 bytes x 16M clocks/sec = ...
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... If a bus error occurs during an operand transfer either on BES or BED, the channel generates an interrupt to the IMP interrupt controller and sets the appropriate bit (BES or BED) in the CSR. 3-4 For More Information On This Product SAPI DAPI SSIZE NOTE MC68302 USER’S MANUAL Go to: www.freescale.com DSIZE BT RST STR MOTOROLA ...
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... IDMA gets up to 75% of the bus bandwidth IDMA gets up to 50% of the bus bandwidth IDMA gets up to 25% of the bus bandwidth IDMA gets up to 12.5% of the bus bandwidth. MOTOROLA For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www.freescale.com ...
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... This register can be incremented by one or two, depending on the SSIZE bit and the starting address in this register. 3.1.2.3 Destination Address Pointer Register (DAPR) The DAPR is a 32-bit register RESERVED 3-6 For More Information On This Product, NOTE NOTE SOURCE ADDRESS POINTER DESTINATION ADDRESS POINTER MC68302 USER’S MANUAL Go to: www.freescale.com 0 0 MOTOROLA ...
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... INTE and INTN bits in the CMR). The CSR is a memory-mapped register which may be read at any time. A bit is cleared by writing a one and is left unchanged by writing a zero. More than one bit may be cleared at a time, and the register is cleared at reset. 7 Bits 7–4—These bits are reserved for future use. MOTOROLA For More Information On This Product ...
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... DONE may be used as an input to the IDMA controller indicating that the device being serviced requires no more transfers and that the transmission ter- minated. DONE is an output if the transfer count is exhausted. 3-8 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... When the complete operand is written, the DAPR is incremented by one or two, and the BCR is decremented by the number of bytes transferred. See 3.1.2.3 Desti- nation Address Pointer Register (DAPR) and 3.1.2.5 Byte Count Register (BCR) for more details. MOTOROLA For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www ...
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... Packing Is Not Possible Read Byte—Write Byte +1 +1 Packing Is Not Desired Read Byte, Read Byte —Write Word +4 +2 Operand Packing Read Word—Write Byte, Write Byte +2 +4 Operand Unpacking +2 +2 Read Word—Write Word MC68302 USER’S MANUAL Go to: www.freescale.com Transfer Description MOTOROLA ...
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... External Burst Mode For external devices requiring very high data transfer rates, the external burst mode al- lows the IDMA to use all the bus bandwidth to service the device. In the burst mode, the MOTOROLA For More Information On This Product, Table 3-2. IDMA Bus Cycles ...
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... STR is cleared, and an interrupt is generated if INTN is set. The SAPR and/or DAPR are also incremented in the normal fashion. If the channel is started with BCR value set to zero, the channel will transfer 64K bytes. 3-12 For More Information On This Product, NOTE: NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... IDMA status changes, status bits are set in the CSR but not in the IPR. When either INTN or INTE is set and the corresponding event occurs, the appropriate bit is set in the IPR, and, if this bit is not masked, the interrupt controller will interrupt the M68000 core. MOTOROLA For More Information On This Product, MC68302 USER’S MANUAL Go to: www ...
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... M68000 core: reset, bus error, halt, and retry. These exceptions also apply to the SDMA channels except that the bus error reporting method is different. See 4.5.8.4 Bus Error on SDMA Access for further details. 3-14 For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... Eighteen Prioritized Interrupt Sources (Internal and External) • A Fully Nested Interrupt Environment • Unique Vector Number for Each Internal/External Source Generated • Three Interrupt Request and Interrupt Acknowledge Pairs MOTOROLA For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www ...
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... The M68000 responds to the interrupt request by executing an interrupt acknowledge 3-16 For More Information On This Product, M68000 CORE DATA BUS MC68302 USER’S MANUAL Go to: www.freescale.com IRQ7/ IRQ6/ IRQ1/ IPL2 IPL1 IPL0 INTERRUPT PRIORITY RESOLVER IPL2–IPL0 TO M68000 CORE IACK1 VECTOR IACK6 GENERATION LOGIC IACK7 MOTOROLA ...
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... In this mode, the three external interrupt request pins are configured as IPL2–IPL0 as in the original MC68000 seven levels of interrupt priority may be encoded. Level 4 is reserved for IMP INRQ interrupts and may not be generated by an external device. MOTOROLA For More Information On This Product, MC68302 USER’S MANUAL Go to: www ...
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... INRQ interrupts are assigned to level 4 (fixed). EXRQ interrupts are assigned by the user to any of the remaining six priority levels in normal mode. In dedi- cated mode, EXRQ interrupts may be assigned to priority levels 7, 6, and 1. 3-18 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... M68000 core for servicing. After the vector number corresponding to this interrupt is passed to the core during an interrupt acknowledge cycle, an INRQ interrupt request is cleared in IPR. (EXRQ requests must be cleared externally.) The remaining interrupt MOTOROLA For More Information On This Product, Normal Mode Dedicated Mode IPL2– ...
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... By clearing all unmasked bits in the event register, the IPR bit is also cleared. 3-20 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... The IMP can generate vectors for up to seven external peripherals by connecting the exter- nal request lines to IRQ7, IRQ6, IRQ1, PB11, PB10, PB9, and PB8. PB11, PB10, PB9, and PB8 are prioritized within level 4. MOTOROLA For More Information On This Product, IPR 8-INPUT ...
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... When the core initiates an interrupt acknowledge cycle for level 4 and there is no internal interrupt pending, the interrupt controller encodes the error code 00000 onto the five low-order bits of the interrupt vector. 3-22 For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
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... V7– MULTIPLY GET ADDRESS $2B4 3. READ 32-BIT VALUE AT $2B4 AND JUMP $2B4 $2B6 Figure 3-4. SCC1 Vector Calculation Example MOTOROLA For More Information On This Product, 5-Bit Interrupt Source Vector 10111 External Device 10110 External Device ...
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... Internal vector. The interrupt controller will provide the vector number for a level 1 interrupt acknowledge cycle External vector. The interrupt controller will not provide the vector number for a lev interrupt. 3-24 For More Information On This Product ET7 ET6 ET1 V7–V5 MC68302 USER’S MANUAL Go to: www.freescale.com 4 0 RESERVED MOTOROLA ...
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... Edge-triggered. An interrupt is made pending when IRQ6 changes from one to zero (falling edge). ET1—IRQ1 Edge-/Level-Triggered This bit is valid only in the dedicated mode Level-triggered. An interrupt is made pending when IRQ1 is low. MOTOROLA For More Information On This Product, NOTE NOTE MC68302 USER’S MANUAL Go to: www ...
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... INRQ interrupt is pending PB11 PB10 SCC1 PB9 TIMER2 SCP 3-26 For More Information On This Product, NOTE Note: NOTE SDMA IDMA SCC2 TIMER3 SMC1 SMC2 MC68302 USER’S MANUAL Go to: www.freescale.com 9 8 TIMER1 SCC3 1 0 PB8 ERR MOTOROLA ...
Page 77
... To clear bits that were set by multiple interrupt events, the user should clear all the unmasked events in the corresponding on- chip peripheral's event register PB11 PB10 SCC1 PB9 TIMER2 SCP MOTOROLA For More Information On This Product, NOTE NOTE SDMA IDMA SCC2 TIMER3 SMC1 SMC2 MC68302 USER’ ...
Page 78
... Clear the TIMER3 bit in the ISR. 4. Execute RTE instruction. Example 2— SCC1 Interrupt Handler 1. Vector to interrupt handler. 3-28 For More Information On This Product SDMA IDMA SCC2 TIMER3 SMC1 SMC2 MC68302 USER’S MANUAL Go to: www.freescale.com 9 8 TIMER1 SCC3 1 0 PB8 0 MOTOROLA ...
Page 79
... Each of the 16 port A pins are independently configured as a general-purpose I/O pin if the corresponding port A control register (PACNT) bit is cleared. Port A pins are configured as dedicated on-chip peripheral pins if the corresponding PACNT bit is set. An example block diagram of PA0 is given in Figure 3-5 MOTOROLA For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com ...
Page 80
... TCLK2, CD2, CTS2, and RTS2) may dedicate the data lines (RXD2 and TXD2) to SCC2 and configure the others as general-purpose I/O pins. What the peripheral 3-30 For More Information On This Product MUX BITS PADDR 16 BITS PACNT MC68302 USER’S MANUAL Go to: www.freescale.com MUX EN RXD2/PA0 PIN MOTOROLA ...
Page 81
... PB7–PB0 functions exactly like PA15–PA0, except that PB7–PB0 is controlled by the port B control register (PBCNT), the port B data direction register (PBDDR), and the port B data register (PBDAT), and PB7 is configured as an open-drain output (WDOG) upon total system reset. MOTOROLA For More Information On This Product, NOTE PACNT Bit = 0 ...
Page 82
... The reserved bits are read as zeros. 3-32 For More Information On This Product, PBCNT Bit = 0 Input to Interrupt Pin Function Control and Timers PB0 — PB1 — PB2 — PB3 GND PB4 — PB5 GND PB6 — PB7 — MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 83
... The CP has 1152 bytes of static RAM configured as a dual-port memory. The dual-port RAM can be accessed by the CP main controller or by one of three bus masters: the M68000 core, the IDMA external master. The M68000 core and the IDMA access the RAM synchro- MOTOROLA For More Information On This Product, 10 ...
Page 84
... As CP microcode RAM used exclusively to store microcode for the CP main con- troller, allowing the development of special protocols or protocol enhancements, under spe- cial arrangement with Motorola. Appendix C discusses available offerings. The RAM block diagram is shown in Figure 3-7. The M68000 core, the IDMA, and the ex- ternal master access the RAM through the IMP bus interface unit (BIU) using the M68000 bus ...
Page 85
... The TMR contains the prescaler value programmed by the user. The software watch- dog timer, which has a watchdog reference register (WRR) and a watchdog counter (WCN), uses a fixed prescaler value. The timer block diagram is shown in Figure 3-8. MOTOROLA For More Information On This Product, SYSTEM RAM 576 BYTES CP µ ...
Page 86
... Free Run and Restart Modes 3-36 For More Information On This Product, 0 EVENT REGISTER TIMER CLOCK 0 GENERATOR MODE BITS CLOCK 0 CAPTURE DETECTION DIVIDE BY 256 0 MC68302 USER’S MANUAL Go to: www.freescale.com INTERNAL MASTER CLOCK/16 OR MASTER CLOCK/1 TIN1 TOUT1 INTERNAL MASTER CLOCK/16 WDOG MOTOROLA ...
Page 87
... The timer registers may be modified at any time by the user. 3.5.2.1 Timer Mode Register (TMR1, TMR2) TMR1 and TMR2 are identical 16-bit registers. TMR1 and TMR2, which are memory- mapped read-write registers to the user, are cleared by reset. 15 PRESCALER VALUE (PS) MOTOROLA For More Information On This Product ...
Page 88
... General Purpose Timer Example). 3.5.2.2 Timer Reference Registers (TRR1, TRR2) Each TRR is a 16-bit register containing the reference value for the timeout. TRR1 and TRR2 are memory-mapped read-write registers. 3-38 For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 89
... INRQ to the interrupt controller. This register is cleared at reset. 7 CAP—Capture Event The counter value has been latched into the TCR. The CE bits in the TMR are used to enable the interrupt request caused by this event. MOTOROLA For More Information On This Product RESERVED REF MC68302 USER’ ...
Page 90
... Program the TRR to $61A8 ( = 50000/2). 3. Program the TMR to $321B (prescaler = toggle TOUT, FRR = 1 to restart 3-40 For More Information On This Product Count = ------------------- - = = 200 000 1 ------------------- - 20 MHz Count ----------------- = Divider = 3.05176 65536 Tout ----------------------- - = 50 000 MC68302 USER’S MANUAL Go to: www.freescale.com , MOTOROLA ...
Page 91
... Reset initializes the register to $FFFF, enabling the watchdog timer and setting it to the max- imum timeout period. This causes a timeout to occur if there is an error in the boot program. MOTOROLA For More Information On This Product, MC68302 USER’S MANUAL Go to: www ...
Page 92
... DTACK should be automatically generated for this chip-select block, and after how many wait states. 3-42 For More Information On This Product, REFERENCE VALUE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 93
... A priority structure exists within the chip-select block. For a given address, the priority is as follows: 1. Access to any IMP internal address (BAR, dual-port RAM, etc.) No chip select asserted. 2. Chip Select 0 3. Chip Select 1 4. Chip Select 2 5. Chip Select 3 MOTOROLA For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com System Integration Block (SIB) 3-43 ...
Page 94
... RESET and HALT). Accesses to the internal RAM and registers, including the system configuration registers (BAR and 3-44 For More Information On This Product, BASE REGISTER 0 (BR0) COMPARE LOGIC OPTION REGISTER 0 (OR0) CS2 CS3 DTACK GENERATION NOTE MC68302 USER’S MANUAL Go to: www.freescale.com CS0 CS1 CS2 CS3 DTACK MOTOROLA ...
Page 95
... FC2–FC0 —Function Code Field This field is contained in bits 15–13 of each BR. These bits are used to set the address space function code. The address compare logic uses these bits to determine whether an MOTOROLA For More Information On This Product, NOTE BASE ADDRESS (A23–A13) MC68302 USER’ ...
Page 96
... On write protect violation cycles ( and MRW = 1), BERR will be generated if WPVE is set, and WPV will be set. If the write protect mechanism is used by an external master, the R/W low to AS asserted timing should minimum. 3-46 For More Information On This Product, NOTE NOTE NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 97
... The CS lines are asserted slightly earlier for internal IMP master memory cycles than for an external master using the CS lines. Set external master wait state (EMWS) in the SCR whenever these timing differences require an extra memory wait state for external masters. MOTOROLA For More Information On This Product, BASE ADDRESS MASK (M23–M13) ...
Page 98
... Set up chip select 2 to assert for a 1 Megabyte block of external RAM beginning at $200000 with 1 wait state. Note that the address must block boundary (i.e. the starting ad- dress Megabyte block could not be $210000). 3-48 For More Information On This Product, NOTE NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 99
... Typical crystal parameters are Co < and The equivalent load capacitance ( this circuit is 20 pF, calculated as ( )/2, where and maximum on the EXTAL pin Figure 3-10. Using an External Crystal MOTOROLA For More Information On This Product, NOTE using a parallel resonant crystal. MC68302 EXTAL ...
Page 100
... Figure 3-11. System Control Register 3-50 For More Information On This Product IPA HWT WPV VGE WPVE RMCST EMWS ADCE FRZ1 SAM HWDEN HWDCN2–HWDCN0 5 4 LPEN LOW-POWER CLOCK DIVIDER MC68302 USER’S MANUAL Go to: www.freescale.com 24 ADC 16 BCLM 8 0 MOTOROLA ...
Page 101
... In the case of nested interrupts, the user may wish to clear the IPA bit only at the end of the original lower priority interrupt rou- tine to keep BCLR asserted until it completes. To guarantee that MOTOROLA For More Information On This Product, Table 3-9. SCR Register Bits Name NOTE MC68302 USER’ ...
Page 102
... The system control logic uses six control bits in the SCR. WPVE—Write Protect Violation Enable 0 = BERR is not asserted when a write protect violation occurs BERR is asserted when a write protect violation occurs. After system reset, this bit defaults to zero. 3-52 For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 103
... The arbiter does not use the M68000 core internal IPEND signal to assert the in- ternal and external bus clear signals The arbiter uses the M68000 core internal IPEND signal to assert the internal and external bus clear signals. MOTOROLA For More Information On This Product, NOTE NOTE MC68302 USER’ ...
Page 104
... The following pins change their functionality in this mode will be an output from the IDMA and SDMA to the external M68000 bus, rather than being an input to the MC68302. 3-54 For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 105
... All MC68302 functionality not expressly mentioned in this section is retained in disable CPU mode and operates identically as before. Even without the use of the disable CPU logic, another proces- sor can be granted access to the IMP on-chip peripherals by re- MOTOROLA For More Information On This Product, NOTE NOTE MC68302 USER’ ...
Page 106
... The MC68302 provides several options for changing the preceding bus master priority list. The options are configured by setting the BCLM bit in the SCR and deciding whether or not the BCLR pin is used externally to cause external bus masters to relinquish the bus (see Table 3-10). 3-56 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 107
... Freescale Semiconductor, Inc. M68000 CORE INDEPENDENT DMA SERIAL DMA BGACK (IR & ER IDLE IR & CG & & & CG MOTOROLA For More Information On This Product, RMC CBR CBG IPEND IDBR IDBG IBCLR ARBITER SDBG SDBR BR BG EXTERNAL BUS MASTER IG IR & ...
Page 108
... Chip selects and system control functions, such as the hardware watch- dog, continue to operate. 3-58 For More Information On This Product, BCLR Used BCLR Ignored BCLM = 0 BCLM = 1 BR Pin SDMA M68000 Interrupts 4 IDMA M68000 MC68302 USER’S MANUAL Go to: www.freescale.com BCLR Used BCLM = 1 SDMA M68000 Interrupts 4 IDMA BR Pin M68000 MOTOROLA ...
Page 109
... The hardware watchdog logic uses four bits in the SCR. HWDEN—Hardware Watchdog Enable 0 = The hardware watchdog is disabled The hardware watchdog is enabled. After system reset, this bit defaults to one to enable the hardware watchdog. MOTOROLA For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www.freescale.com ...
Page 110
... M68000 core and when it is desirable to reduce system power consumption to its minimum value. All low-power modes are entered by first setting the low-power enable (LPEN) bit, and then executing the M68000 STOP in- struction. 3-60 For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 111
... When a timer interrupt occurs, the M68000 resumes execution with the timer interrupt handler. After the RTE instruction, execution continues with the instruc- tion following the STOP instruction in step 4 above. All IMP state information is re- tained. MOTOROLA For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com ...
Page 112
... The use of external clocks with the SCCs allows the original se- rial rates to be maintained; however, before attempting this, the SCC performance data should be carefully reviewed (see Ap- 3-62 For More Information On This Product, NOTE NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 113
... LPCD0 0 to 31) can be selected. After a system reset, these bits default to zero. LPEN—Low-power Enable 0 = The low-power modes are disabled The low-power modes are enabled. After a system reset, this bit defaults to zero to disable the low-power modes. MOTOROLA For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com System Integration Block (SIB) ...
Page 114
... SCC1 baud rate generator at high speed (for instance in a high speed UART application), but the TCLK1 output is not needed, and it is desired to 3-64 For More Information On This Product RESERVED MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 115
... FRZ remains asserted. Regardless of whether or not the freeze logic is used, FRZ must be negated during system reset. MOTOROLA For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www.freescale.com ...
Page 116
... A block diagram of an MC68302 DRAM system is shown in Figure 3-13. The MC68302 gen- erates standard M68000 read and write cycles that must be converted to DRAM read and write cycles. The address buffers provide the multiplexing of the row and column addresses 3-66 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 117
... PB8 pin should see a high-to-low transition every 15.625 s. This is once every 260 cycles for a 16.67-MHz clock. Note that one refresh per request minimizes the speed loss on the SCC channels. MOTOROLA For More Information On This Product, CONTROL ...
Page 118
... Increment Step (number of bytes/row) Word RAM Refresh Cycle Count (number of rows) Word Temporary Refresh High Address and FC Word Temporary Refresh Low Address Word Temporary Refresh Cycles Count Word Reserved HIGH START ADDRESS NOTE MC68302 USER’S MANUAL Go to: www.freescale.com 0 MOTOROLA ...
Page 119
... Programming Example An example of programming the DRAM parameters is given for the Motorola MC514256 DRAM. This 1M-bit DRAM is organized in a 256K 4 arrangement. There are 512 rows and 512 columns on this device. A bank these DRAMs is assumed in this example, giving 512K-bytes of memory ...
Page 120
... Freescale Semiconductor, Inc. System Integration Block (SIB) 3-70 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 121
... Six Serial Direct Memory Access (SDMA) Channels • A Command Set Register • Serial Channels Physical Interface Including: —Motorola Interchip Digital Link (IDL) —General Circuit Interface (GCI), also known as IOM-2 —Pulse Code Modulation (PCM) Highway Interface —Nonmultiplexed Serial Interface (NMSI) Implementing Standard — ...
Page 122
... For More Information On This Product, M68000 DATA BUS MICROCODE ROM PERIPHERAL BUS FIFO FIFO FIFO FIFO SCC1 SCC2 SERIAL CHANNELS PHYSICAL INTERFACE MC68302 USER’S MANUAL Go to: www.freescale.com DUAL-PORT RAM SYSTEM PARAMETER RAM RAM FIFO FIFO SCC H/W SCC3 REGISTERS PHYSICAL I/F REGISTERS MOTOROLA ...
Page 123
... RAM as shown in path 1. In path 2, data is sent over the peripheral bus to the in- ternal dual-port RAM. The SMCs and SCP, shown in path 3, always route their data to the dual-port RAM since they only receive and transmit a byte at a time. MOTOROLA For More Information On This Product, Communications Processor (CP) MC68302 USER’ ...
Page 124
... For More Information On This Product, 1 GENERAL- 3 TIMERS PURPOSE AND DMA ADDITIONAL CHANNEL FEATURES 68000 SYSTEM BUS 1 1152 BYTES 6 DMA DUAL-PORT CHANNELS RAM 3 PERIPHERAL BUS 2 OTHER 3 SERIAL SERIAL CHANNELS CHANNELS NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MC68302 IMP RAM / ROM OTHER PERIPHERALS MOTOROLA ...
Page 125
... SCON registers). Note that this operation does not clear IPR bits in the in- terrupt controller. GCI-OPCODE—GCI Commands and Command Opcodes 0 = When the GCI bit is zero, the commands are as follows: MOTOROLA For More Information On This Product, Communications Processor (CP ...
Page 126
... Bit 3—Reserved bit; should be set to zero. CH. NUM.—Channel Number These bits are set by the M68000 core to define the specific SCC channel that the com- mand is to operate upon SCC1 01 = SCC2 10 = SCC3 11 = Reserved 4-6 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 127
... BRG pins as shown. All NMSI2 pins are multiplexed with parallel I/O pins. The user may choose which NMSI2 pins are used by the SCC2 and which are used as parallel I/O. On NMSI3, the TXD, TCLK, RXD, and RCLK pins are multiplexed with parallel I/O lines; MOTOROLA For More Information On This Product, Communications Processor (CP) MC68302 USER’ ...
Page 128
... SCC. 4-8 For More Information On This Product, BRG SCC2 BRG BRG MC68302 USER’S MANUAL Go to: www.freescale.com NMSI1 TCLK TXD (TX DATA READY) RTS CTS (GATES TRANSMITTER) RCLK RXD CD (GATES RECEIVER) NMSI2 (same as above) NMSI3 (same as above) MOTOROLA ...
Page 129
... The IDL and GCI (IOM-2) interfaces are used to connect to semiconductor devices that sup- port the Integrated Services Digital Network (ISDN). IDL and GCI allow the MC68302 to communicate over any of the ISDN basic rate channels. MOTOROLA For More Information On This Product, MC68302 ...
Page 130
... LAYER-1 BUS INTERFACE ISDN INTERFACE OR SCC1 Figure 4-5. Serial Channels Physical Interface Block Diagram 4-10 For More Information On This Product, M68000 DATA BUS TO SCC1 TO SMC2 MUX TIME-SLOT ASSIGNER MC68302 USER’S MANUAL Go to: www.freescale.com SIMODE MODE REGISTER TO SCC2 TO SCC3 MUX MUX SCC2 SCC3 MOTOROLA ...
Page 131
... IDL Interface The IDL interface is a full-duplex ISDN interface used to interconnect a physical layer device (such as the Motorola ISDN S/T transceiver MC145474) to the integrated multiprotocol pro- cessor (IMP). Data on five channels (B1, B2 and M) is transferred in a 20-bit frame every 125 s, providing 160-kbps full-duplex bandwidth. The IMP is an IDL slave device that is clocked by the IDL bus master (physical layer device) ...
Page 132
... The IDL signals are as follows: 4-12 For More Information On This Product, EPROM M68000 BUS B1 M68000/DMA/CS SCP MC68302 IMP IDL (DATA) ICL SCC (CONTROL) SCC B2+D B1+B2+D MC68302 USER’S MANUAL Go to: www.freescale.com MC145554 PCM CODEC/FILTER MONOCIRCUIT POTS MC145474 S/T FOUR WIRE TRANSCEIVER MOTOROLA ...
Page 133
... D channel collision is detected on the D channel, the physical layer device ne- gates L1GR. The IMP then stops its transmission and retransmits the frame when L1GR is asserted again. This is handled automatically for the first two buffers of the frame. MOTOROLA For More Information On This Product, NOTE ...
Page 134
... These signals are used for interfacing devices that do not support the GCI bus. They are configured with the SIMASK register and are active only for bits that are not masked. 4-14 For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 135
... Bearer Channel (8 bits) M 64-kbps Monitor Channel (8 bits) D 16-kbps Signaling Channel (2 bits) C/ 48-kbps Command/Indication Channel (6 bits) In addition to the 144-kbps ISDN channels, GCI provides two channels for mainte- nance and control functions. MOTOROLA For More Information On This Product, B2 MONITOR MONITOR SMC1 Figure 4-8 ...
Page 136
... CEPT interfaces as well as user-defined interfaces. In this mode, the NMSI1 pins have new names and functions (see Table 4-2). 4-16 For More Information On This Product, Serial Controllers D SCC1, SCC2, SCC3 B1 SCC1, SCC2, SCC3 B2 SCC1, SCC2, SCC3 M SMC1 C/I SMC2 MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 137
... An example of the use of the L1SY1 and L1SY0 sync signals in the envelope mode is shown in Figure 4-10. The three PCM channels defined in the figure show some of the flexibility available in the PCM highway envelope mode. As shown, PCM channel time slots do not MOTOROLA For More Information On This Product, Communications Processor (CP) ...
Page 138
... PCM highway operation. If the RTS signals are not needed, they can be ignored or reassigned as parallel I/O. 1 CLOCK CYCLE SYNC PRIOR L1SY0 L1SY1 8-BIT ENVELOPE L1SY0 L1SY1 DATA ROUTING CH-1 CH-2 CH-3 Figure 4-9. Two PCM Sync Methods 4-18 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 139
... B1 and B2 channels of ISDN. 4.4.5.1 Serial Interface Mode Register (SIMODE) If the IDL or GCI mode is used, this register allows the user to support any or all of the ISDN channels independently. Any extra SCC channel can then be used for other purposes in MOTOROLA For More Information On This Product ...
Page 140
... It also prevents an SCC's indi- vidual loopback (configured in the SCM) from affecting the pins of its associated NMSI interface. 4-20 For More Information On This Product SDIAG0 SDC2 SDC1 DRA MSC3 MSC2 MC68302 USER’S MANUAL Go to: www.freescale.com 9 8 B2RB B2RA 1 0 MS1 MS0 MOTOROLA ...
Page 141
... TXD1, RCLK1, TCLK1, CD1, CTS1, and RTS1). SCC2 functions can be routed to port A as NMSI functions or configured instead as PA6–PA0. Four of the SCC3 functions can be routed to port A or retained as PA11–PA8. The other MOTOROLA For More Information On This Product, Communications Processor (CP) MC68302 USER’ ...
Page 142
... This configuration provides the user with options for controlling up to three independent full-duplex lines implementing bridges or gateway functions or multiplexing up to three SCCs onto the same physical layer interface to implement ISDN basic rate channel or 4-22 For More Information On This Product NOTE MC68302 USER’S MANUAL Go to: www.freescale.com 0 B1 MOTOROLA ...
Page 143
... B pins as inputs in the port B data direction register. When a change in the state of the pin occurs, the interrupt handler may assert or negate the extra outputs to sup- port the hand-shaking protocol. (See 3.3 Parallel I/O Ports for related details.) MOTOROLA For More Information On This Product, Communications Processor (CP) MC68302 USER’ ...
Page 144
... SCC MODE REGISTER REGISTER SCC MASK REGISTER PERIPHERAL BUS DATA DATA REGISTERS REGISTERS TRANSMITTER CONTROL UNIT SHIFTER SHIFTER TXD MC68302 USER’S MANUAL Go to: www.freescale.com SCC CONFIGURATION REGISTER MAIN CLOCK BAUD RATE TIN1 GENERATOR TCLK CLOCK RCLK GENERATOR INTERNAL CLOCKS MOTOROLA ...
Page 145
... RCLK pin. This bit should be programmed to one if a multiplexed mode is chosen for the SCC. After system reset, SCC hardware causes the RCLK to default to an input and stay an input until a zero is written to RCS. MOTOROLA For More Information On This Product, NOTE 10 ...
Page 146
... UART clock rate of 5.56 MHz and a baud rate of 347 kbaud. Assuming again a 16.67-MHz 4-26 For More Information On This Product, NOTE DIV 4 CD10–CD0 BIT BITS 11-BIT PRESCALER COUNTER DIVIDE BY 1-2048 RCLK TCS MUX PIN BIT INTERNAL T CLOCK MC68302 USER’S MANUAL Go to: www.freescale.com EXTERNAL PIN TCLK PIN MOTOROLA ...
Page 147
... DIAG1–DIAG0—Diagnostic Mode 00 = Normal operation (CTS, CD lines under automatic control) In this mode, the CTS and CD lines are monitored by the SCC controller. The SCC controller uses these lines to automatically enable/disable reception and transmission. MOTOROLA For More Information On This Product, 16.0 Actual Actual ...
Page 148
... For the NMSI2 and NMSI3 pins, the TXD pin may be programmed to either show the transmitted data or not show the data by programming port A par- 4-28 For More Information On This Product, From RTS Low 0 1 NOTE MC68302 USER’S MANUAL Go to: www.freescale.com From CTS Low 48 3.5 MOTOROLA ...
Page 149
... SDIAG1–SDIAG0 bits need be set. When using loopback mode, the clock source for the transmitter and the receiver (as set in the TCS and RCS bits in the SCON register), must be the same. Thus, MOTOROLA For More Information On This Product, Communications Processor (CP) ...
Page 150
... For the receiver, the tools are 1) the empty bit in the receive buffer descriptor, 2) the ENR bit, and 3) the ENTER HUNT MODE command. For the transmitter, the 4-30 For More Information On This Product, NOTE NOTE NOTE NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 151
... Note that for the DDCMP, SYN1 must equal SYN2 must equal DSYN1 for proper operation. 15 SYN2 The DSR register has no relationship to the RS-232 signal “data set ready,” which is also abbreviated DSR. MOTOROLA For More Information On This Product, Communications Processor (CP NOTE MC68302 USER’ ...
Page 152
... Figure 4-15. Memory Structure 4-32 For More Information On This Product, TX BUFFER DESCRIPTORS (8) FRAME STATUS DATA LENGTH DATA POINTER RX BUFFER DESCRIPTORS (8) FRAME STATUS DATA COUNT DATA POINTER D DATA E TX DATA R RX DATA MC68302 USER’S MANUAL Go to: www.freescale.com EXTERNAL MEMORY TX DATA BUFFER RX DATA BUFFER MOTOROLA ...
Page 153
... CP moves on to the next BD, again waiting for that BD's “ready” bit to be set. Thus, the CP does no look-ahead BD processing, nor does it skip over BDs that are not ready. When the CP sees the “wrap” bit set in a BD, it goes back to the beginning of the BD MOTOROLA For More Information On This Product, Communications Processor (CP) ...
Page 154
... RAM areas. Part of each SCC parameter RAM (offset $80–$9A), which is iden- tical for each protocol chosen, is shown in Table 4-6. Offsets $9C–$BF comprise the proto- col-specific portion of the SCC parameter RAM and are discussed relative to the particular protocol chosen. 4-34 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 155
... The value of the function code register for any channel may be equal to that of any other, but do not initialize FC2–FC0 with the value “111” which causes a conflict with the interrupt acknowl- edge cycle to occur MOTOROLA For More Information On This Product, Width Byte Rx Function Code Byte ...
Page 156
... TBD# = $48, etc. Upon reset, the CP main controller sets this register to $40. The user can change this register only after the STOP TRANSMIT command has been issued. In most applications, this parameter will never need to be modified by the user. 4-36 For More Information On This Product, NOTE NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 157
... If SCC2 or SCC3 is used, write the parallel port A and B control registers (PACNT and PBCNT) to configure pins as parallel I/O lines or peripheral functions as needed (see 3.3 Parallel I/O Ports). 2. Write SIMODE to configure the serial channels physical interface for the three SCCs MOTOROLA For More Information On This Product, Communications Processor (CP) NOTE MC68302 USER’ ...
Page 158
... SCC mask register). The SCC event register is a memory- mapped register that may be read at any time. A bit is cleared by writing a one (writing a zero does not affect a bit's value). 4-38 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 159
... Furthermore, in the event registers (SCCE) for each protocol, a maskable interrupt bit is provided to allow the detection of any change in signal status. After power-on reset, when the SCC is enabled for the first time, the SCCE register will show that a change of status occurred, re- MOTOROLA For More Information On This Product, Communications Processor (CP) NOTE ...
Page 160
... Interrupt Controller). The interrupt service routine should read the bus error channel number from the parameter RAM at BASE + 67C as follows: 0—SCC1 Tx Channel 1—SCC1 Rx Channel or DRAM Refresh Cycle 2—SCC2 Tx Channel 3—SCC2 Rx Channel 4-40 For More Information On This Product RESERVED ID CD MC68302 USER’S MANUAL Go to: www.freescale.com 0 CTS MOTOROLA ...
Page 161
... If EXSYN in the BISYNC mode register is set, then the BISYNC controller transfers all characters that follow the external SYNC pulse to the receive buffers. The BISYNC controller can reverse the bit order in both modes. MOTOROLA For More Information On This Product, Communications Processor (CP) NOTE MC68302 USER’ ...
Page 162
... SCC to its initial state, the RX internal state, the TX internal state, the TBD#, and the RBD# can be written to their values after reset. The user can read these values for each SCC after a reset. 4-42 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 163
... The character format of the UART protocol is shown in Figure 4-17. START UART TXD BIT UART TCLK 16 Figure 4-17. UART Frame Format MOTOROLA For More Information On This Product, Communications Processor (CP DATA BITS WITH THE LEAST SIGNIFICANT BIT FIRST MC68302 USER’S MANUAL Go to: www.freescale.com OPTIONAL ADDR ...
Page 164
... TXD line and receives data from the RXD line into memory. The seven dedicated serial interface pins are transmit data (TXD), receive data (RXD), receive clock (RCLK), transmit clock (TCLK), carrier detect (CD), clear to send (CTS), and request to send 4-44 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 165
... When a complete character has been clocked in, the contents of the shift register are transferred to the UART receive data register. If there is an error in this character, then the appropriate error bits will be set by the IMP. MOTOROLA For More Information On This Product, Communications Processor (CP) MC68302 USER’ ...
Page 166
... Word UART ADDRESS Character 2 Word Receive Control Character Register Word CONTROL Character 1 Word CONTROL Character 2 Word CONTROL Character 3 Word CONTROL Character 4 Word CONTROL Character 5 Word CONTROL Character 6 Word CONTROL Character 7 Word CONTROL Character 8 MC68302 USER’S MANUAL Go to: www.freescale.com Description MOTOROLA ...
Page 167
... In the multidrop mode, the UART controller can provide automatic address recognition of two addresses. In this case, the lower order byte of UADDR1 and UADDR2 are pro- grammed by the user with the two desired addresses. See 4.5.11.6 UART Address Rec- ognition for more details. MOTOROLA For More Information On This Product, Communications Processor (CP) NOTE MC68302 USER’ ...
Page 168
... Flow-control characters may also be transmitted at any time. In the message-oriented environment, the data stream is divided into buffers. However, the physical format of each character (stop bits, parity, etc.) is not altered. 4-48 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 169
... If an enabled receiver has been disabled by clearing ENR in the SCC mode register, the ENTER HUNT MODE command must be given to the channel before setting ENR again. Reception will then begin with the next BD. MOTOROLA For More Information On This Product, Communications Processor (CP) MC68302 USER’ ...
Page 170
... Figure 4-18. Two Configurations of UART Multidrop Operation 4-50 For More Information On This Product, NOTE SLAVE 2 SLAVE SCON REGISTER 1 WOMS MC68302 USER’S MANUAL Go to: www.freescale.com +V +V WIRED-OR MODE SELECT ALLOWS MULTIPLE TRANSMIT PINS TO BE DIRECTLY CONNECTED. MOTOROLA ...
Page 171
... REA I 10 Figure 4-19. UART Control Characters Table CHARACTER7–CHARACTER1—Control Character Value These fields define control characters that should be compared to the incoming character. For 7-bit characters, the eighth bit (bit 7) should be zero. MOTOROLA For More Information On This Product, NOTE • ...
Page 172
... The CP clears this bit after transmis- sion. I—Interrupt If set, the M68000 core will be interrupted when this character has been transmitted. (The TX bit will be set in the UART event register.) 4-52 For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 173
... If the UART is still in the process of receiving a message that the user has already decided to discard, the message may be aborted by issuing the ENTER HUNT MODE command. The UART receiver will be re-enabled when the message is finished by detecting one idle MOTOROLA For More Information On This Product, Communications Processor (CP) NOTE MC68302 USER’ ...
Page 174
... Noise Error. Noise error is detected by the UART controller when the three samples taken on every bit are not identical. When this error occurs, the channel writes the re- ceived character to the buffer and proceeds normally but increments the noise error 4-54 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 175
... The UART receiver can always receive fractional stop bits. The next character's start bit may begin anytime after the 11th internal clock of the previous character's first stop bit (the UART uses a 16x clock). MOTOROLA For More Information On This Product, Communications Processor (CP) ...
Page 176
... In the multidrop mode, an additional address/data bit is transmitted with each character. The multidrop asynchronous modes are compatible with the Motorola MC68681 DUART, the Motorola MC68HC11 SCI interface, and the Motorola DSP56000 SCI interface. UM0 is also used to select the wakeup mode before en- abling the receiver or issuing the ENTER HUNT MODE command ...
Page 177
... Reception of a user-defined control character (when reject (R) bit = 0) 2. Detection of an error during message processing 3. Detection of a full receive buffer 4. Reception of a programmable number of consecutive IDLE characters MOTOROLA For More Information On This Product, Communications Processor (CP) MC68302 USER’S MANUAL Go to: www.freescale.com ...
Page 178
... BDs; otherwise, errant behavior may occur. 4-58 For More Information On This Product — — DATA LENGTH RX BUFFER POINTER (24-bits used, upper 8 bits must be 0) NOTE NOTE MC68302 USER’S MANUAL Go to: www.freescale.com — MOTOROLA ...
Page 179
... STATUS 1 LENGTH XXXX 32-BIT BUFFER POINTER POINTER (24-BITS USED) 10 CHARS CHARACTERS RECEIVED BY UART TIME Figure 4-21. UART Rx BD Example MOTOROLA For More Information On This Product, Communications Processor (CP) MRBLR = 8 BYTES FOR THIS SCC BUFFER FULL IDLE TIMEOUT OCCURRED FR 1 BYTE 4 HAS FRAMING ERROR ...
Page 180
... A framing error is detected by the UART controller when no stop bit is detected in the re- ceive data string. PR—Parity Error A character with a parity error was received and is located in the last byte of this buffer. OV—Overrun A receiver overrun occurred during message reception. 4-60 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 181
... The data buffer, which has been prepared for transmission by the user, has not been transmitted or is currently transmitting. No fields of this BD may be written by the user once this bit is set. MOTOROLA For More Information On This Product, NOTE NOTE ...
Page 182
... No preamble sequence is sent The UART sends one preamble sequence ( ones) before sending the data. The following bits are written by the CP after it has finished transmitting the associated data buffer. 4-62 For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 183
... All unmasked bits must be cleared before the CP will clear the internal interrupt request. This register is cleared at reset. An example of the timing of various events in the UART event register is shown in Figure 4- 23. MOTOROLA For More Information On This Product, Communications Processor (CP) NOTE MC68302 USER’ ...
Page 184
... A change in the status of the receive serial line was detected on the UART channel. The SCC status register may be read to determine the current status. 4-64 For More Information On This Product, 10 CHARACTERS RX CCR IDL 7 CHARACTERS TX CTS IDL BRK CCR BSY TX MC68302 USER’S MANUAL Go to: www.freescale.com LINE IDLE BREAK RX BRK CD LINE IDLE 0 RX MOTOROLA ...
Page 185
... For simplicity, assume that the line is not multidrop (no addresses are transmitted) and that each S record will fit into a single data buffer. MOTOROLA For More Information On This Product, Communications Processor (CP) MC68302 USER’S MANUAL Go to: www ...
Page 186
... It also defines a broadcast address. Some HDLC-type protocols also allow for extended addressing beyond 16-bits. 4-66 For More Information On This Product, INFORMATION CONTROL (OPTIONAL) 8 BITS 8N BITS MC68302 USER’S MANUAL Go to: www.freescale.com CLOSING CRC FLAG 16 BITS 8 BITS MOTOROLA ...
Page 187
... Four Address Comparison Registers with Mask • Maintenance of Five 16-Bit Error Counters • Flag/Abort/Idle Generation/Detection • Zero Insertion/Deletion • NRZ/NRZI Data Encoding • 16-Bit or 32-Bit CRC-CCITT Generation/Checking MOTOROLA For More Information On This Product, Communications Processor (CP) NOTE MC68302 USER’S MANUAL Go to: www.freescale.com ...
Page 188
... BD's associated data buffer starting with the first address byte. When the data buffer has been filled, the HDLC controller clears the empty bit in the BD and generates an interrupt if the interrupt bit in the BD is set. If the incoming frame ex- 4-68 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 189
... CRC will not be affected. 4.5.12.4 HDLC Programming Model The M68000 core configures each SCC to operate in one of four protocols by the MODE1– MODE0 bits in the SCC mode register (SCM). MODE1–MODE0 = 00 selects HDLC mode. MOTOROLA For More Information On This Product, Communications Processor (CP) Width ...
Page 190
... BD (TBD#) in the channel's transmit BD table. If the transmitter is being re-enabled, the RESTART TRANSMIT command must be used and should be followed by the enabling of the transmitter in the SCC mode register. 4-70 For More Information On This Product, MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 191
... If this limit is exceeded, the remainder of the incoming HDLC frame is discarded, and the LG (Rx frame too long) bit is set in the last BD belonging to that frame. The HDLC controller waits to the end of the frame and reports the frame status MOTOROLA For More Information On This Product, NOTE ...
Page 192
... BD of length two will be opened to report the overrun, and the RXB interrupt will be generated (if enabled). 2. Carrier Detect Lost During Frame Reception. When this error occurs and the channel 4-72 For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 193
... RETRC—Frame Retransmission Counter (due to collision) 4.5.12.9 HDLC Mode Register Each SCC mode register is a 16-bit, memory-mapped, read-write register that controls the SCC operation. The term HDLC mode register refers to the protocol-specific bits (15–6) of MOTOROLA For More Information On This Product, Communications Processor (CP) 1 ...
Page 194
... Toggling FLG will never result in partial flags being transmitted. 4-74 For More Information On This Product FSE — RTE FLG ENC NOTE MC68302 USER’S MANUAL Go to: www.freescale.com 5 0 COMMON SCC MODE BITS MOTOROLA ...
Page 195
... BD after it sets this bit. The empty bit will remain set while the HDLC controller is currently filling the buffer with received data. X—External Buffer 0 = The buffer associated with this internal dual-port RAM The buffer associated with this external memory. MOTOROLA For More Information On This Product ...
Page 196
... BUFFER ADDRESS 1 ADDRESS 2 CONTROL BYTE 8 BYTES 5 INFORMATION (I-FIELD) BYTES BUFFER LAST I-FIELD BYTE CRC BYTE 1 CRC BYTE 2 8 BYTES EMPTY BUFFER ADDRESS 1 ADDRESS 2 CONTROL BYTE 8 BYTES EMPTY BUFFER EMPTY 8 BYTES ABORT/IDLE PRESENT UNEXPECTED ABORT TIME OCCURS BEFORE CLOSING FLAG! MOTOROLA ...
Page 197
... BD. NO—Rx Nonoctet Aligned Frame A frame that contained a number of bits not exactly divisible by eight was received. AB—Rx Abort Sequence A minimum of seven consecutive ones was received during frame reception. MOTOROLA For More Information On This Product, Communications Processor (CP) NOTE MC68302 USER’S MANUAL Go to: www ...
Page 198
... DATA LENGTHTX BUFFER POINTER (24-bits used, upper 8 bits must be 0) OFFSET + 6 Figure 4-28. HDLC Transmit Buffer Descriptor 4-78 For More Information On This Product, NOTE NOTE — — — — MC68302 USER’S MANUAL Go to: www.freescale.com — — — — MOTOROLA ...
Page 199
... Transmit the CRC sequence after the last data byte. Bits 9–2—Reserved for future use. The following status bits are written by the HDLC controller after it has finished transmitting the associated data buffer. MOTOROLA For More Information On This Product, Communications Processor (CP) NOTE MC68302 USER’ ...
Page 200
... All unmasked bits must be cleared before the CP will clear the internal interrupt request. This register is cleared at reset. An example of the timing of various events in the HDLC event register is shown in Figure 4- 29. 4-80 For More Information On This Product, NOTE MC68302 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...