21285-AB

Manufacturer Part Number21285-AB
DescriptionMicroprocessor, 21285 Core Logic For SA-110 Microprocessor
ManufacturerIntel Corporation
21285-AB datasheet
 


Specifications of 21285-AB

CaseBGADc99+/00+
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Registers
7.3.20
I
O Inbound Post_List Count Register—Offset 138h
2
The contents of the inbound post_list count register contain the number of entries available on the
I
O inbound post_list. When a PCI bus master places an entry onto the post_list (via a write to
2
offset 40h), the value is incremented by one. When the SA-110 writes to this address, the action is
dependent on the value of bit 31 of the data. If 0, the value in the register is decremented by one
(disregarding the rest of the write data); if 1, the data is written into the register. When the value is
not equal to 0, an interrupt is posted to the SA-110 (if not masked by IRQEnable/FIQEnable).
Dword Bit
Name
15:0
Inbound post_list count
31:16
7.3.21
SA-110 Control Register—Offset 13Ch
Dword Bit
Name
0
Initialize complete
1
Assert SERR
2
3
Received SERR
7-36
R/W
Description
R/W
I
O inbound post_list count.
2
Reset value: 0.
R
Read only as 0.
R/W
Description
R/W
This bit indicates that the SA-110 software has initialized
the 21285 CSRs. Specifically, the following CSRs should
be loaded before this bit is set.
• SDRAM base address mask register
• SDRAM base address offset register
• Expansion ROM base address mask register
When 0: The 21285 returns retry response as the target
of PCI configuration cycles, and will not assert devsel_l to
the PCI, I/O, or memory commands.
When 1: The 21285 returns normal response to PCI
configuration cycles. This allows the SA-110 to initialize
CSRs such as subsystem vendor ID, base address
masks, and so on before the host processor’s
configuration software can read them.
Reset value: 0.
R/W
When 1: The 21285 asserts serr_l for one cycle if
pci_cfn is deasserted and command register bit SERR#
enable bit [8] is a 1.
Reset value: 0.
R
Read only as 0.
W1C
Set when serr_l is asserted by an external device and
pci_cfn is asserted. It can cause an interrupt to the
SA-110 if enabled in the IRQEnable/FIQEnable registers
(see
Section
7.3.31).
Reset value: 0.
21285 Core Logic for SA-110 Datasheet
(Sheet 1 of 3)