21285-AB Originated Transactions - Intel Corporation
Manufacturer Part Number
Microprocessor, 21285 Core Logic For SA-110 Microprocessor
Specifications of 21285-AB
All 21285 transactions occur between the SA-110, PCI, SDRAM, ROM, and X-Bus.
shows the three FIFOs used in performing the various transactions.
Outbound FIFO (256 bytes)
— SA-110 write addresses and data for PCI
— SA-110 read addresses for PCI
— DMA write addresses and data for PCI
— DMA read addresses for PCI
Inbound FIFO (256 bytes)
— PCI write addresses and data for SDRAM and ROM
— PCI read addresses for SDRAM and ROM
— DMA write data for SDRAM
— SA-110 read data from PCI
PCI Read FIFO (128 bytes)
— PCI read data from SDRAM and ROM
SA-110 Originated Transactions
The following sections describe SA-110 originated bus transactions. These transactions are
classified by their address spaces (refer to
The 21285 controls the SA-110 clock, MCLK, by stretching the high time to stall the SA-110
during bus cycles (indicated by assertion of nMREQ by SA-110). The number of cycles that
MCLK stays high may be different for each address space and depends upon other 21285 activity
at the time nMREQ asserts.
The SA-110 write data is written to the selected CSR (the CSR with offset equal to SA-110 address
A[10:2]). The SA-110 is normally stalled for three cycles, but can be stalled longer. If a
nonexistent CSR is selected within the CSR address range, the write data is discarded (no error
action is taken).
The CSR address space is listed in Tables 7-2, 7-3, and 7-4.
The selected CSR (the CSR with offset equal to SA-110 address A[10:2]) read data is driven onto
D[31:0]. If a nonexistent CSR is selected within the CSR address range, zeros are read (no error
action is taken). The SA-110 normally stalls for three cycles.
21285 Core Logic for SA-110 Datasheet