AD817AR Analog Devices Inc, AD817AR Datasheet - Page 9

• Manufacturer Part Number: AD817AR
• Description: IC OPAMP HS LP 8-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD817AR

• Slew Rate: 350 V/µs
• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Applications: General Purpose
• Number Of Circuits: 1
• -3db Bandwidth: 50MHz
• Current - Supply: 7mA
• Current - Output / Channel: 50mA
• Voltage - Supply, Single/dual (±): 5 V ~ 36 V, ±2.5 V ~ 18 V
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• No. Of Amplifiers: 1
• Bandwidth: 50MHz
• No. Of Pins: 8
• Settling Time: 70ns
• Operating Temperature Max: 85°C
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

REV. B
DRIVING CAPACITIVE LOADS
The internal compensation of the AD817, together with its high
output current drive, permit excellent large signal performance
while driving extremely high capacitive loads.
THEORY OF OPERATION
The AD817 is a low cost, wide band, high performance opera-
tional amplifier which effectively drives heavy capacitive or resis-
tive loads. It also provides a constant slew rate, bandwidth and
settling time over its entire specified temperature range.
The AD817 (Figure 31) consists of a degenerated NPN differ-
ential pair driving matched PNPs in a folded-cascode gain stage.
The output buffer stage employs emitter followers in a class AB
amplifier which delivers the necessary current to the load while
maintaining low levels of distortion.
The capacitor, C
capacitive loads. At low frequencies, and with low capacitive
loads, the gain from the compensation node to the output is
very close to unity. In this case, C
contribute to the overall compensation capacitance of the device.
As the capacitive load is increased, a pole is formed with the
output impedance of the output stage. This reduces the gain,
and therefore, C
some fraction of C
capacitance, reducing the unity gain bandwidth. As the load
capacitance is further increased, the bandwidth continues to fall,
maintaining the stability of the amplifier.
GENERATOR
Figure 30b. Inverting Amplifier Pulse Response While
Driving Capacitive Loads
PULSE
Figure 30a. Inverting Amplifier Driving a 1000 pF
Capacitive Load
HP
100
90
10
0%
V
5V
5V
IN
50
F
F
1k
R
, in the output stage mitigates the effect of
is incompletely bootstrapped. Effectively,
IN
F
contributes to the overall compensation
2
3
AD817
–V
+V
7
4
1k
S
S
0.01 F
0.01 F
3.3 F
3.3 F
6
F
V
is bootstrapped and does not
OUT
500ns
C
1000pF
TEKTRONIX
P6201 FET
L
PROBE
100pF
1000pF
TEKTRONIX
PREAMP
7A24
–9–
INPUT CONSIDERATIONS
An input protection resistor (R
cuits where the input to the AD817 will be subjected to tran-
sient or continuous overload voltages exceeding the +6 V
maximum differential limit. This resistor provides protection for
the input transistors by limiting their maximum base current.
For high performance circuits, it is recommended that a “bal-
ancing” resistor be used to reduce the offset errors caused by
bias current flowing through the input and feedback resistors.
The balancing resistor equals the parallel combination of R
and R
terminal. The offset voltage error will then be reduced by more
than an order of magnitude.
GROUNDING & BYPASSING
When designing high frequency circuits, some special precau-
tions are in order. Circuits must be built with short interconnect
leads. When wiring components, care should be taken to pro-
vide a low resistance, low inductance path to ground. Sockets
should be avoided, since their increased interlead capacitance
can degrade circuit bandwidth.
Feedback resistors should be of low enough value (<1 k ) to
assure that the time constant formed with the inherent stray
capacitance at the amplifier’s summing junction will not limit
performance. This parasitic capacitance, along with the parallel
resistance of R
may result in peaking. A small capacitance (1 pF–5 pF) may be
used in parallel with the feedback resistor to neutralize this effect.
Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. Ceramic disc capacitors of 0.1 F
are recommended.
–IN
+IN
F
and thus provides a matched impedance at each input
Figure 32. Offset Null Configuration
Figure 31. Simplified Schematic
F
NULL 1
/R
IN
, form a pole in the loop transmission which
2
3
AD817
–V
4
S
NULL 8
+V
1
7
IN
S
10k
in Figure 22) is required in cir-
8
6
V
OS
C
ADJUST
F
AD817
+V
OUTPUT
–V
S
S
IN