SII150ACT100 ETC, SII150ACT100 Datasheet

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SII150ACT100

Manufacturer Part Number
SII150ACT100
Description
Manufacturer
ETC
Datasheet

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Si
PanelLink
General Description
to support displays ranging from VGA to SXGA (25-112 MHz). The SiI 150A
transmitter supports up to true color panels (24 bit/pixel, 16.7M colors) in 1 or
2 pixels/clock mode, and also features an inter-pair skew tolerance up to 1 full
input clock cycle. An advanced on-chip jitter filter is also added to extend
tolerance to VGA clock jitter. Since all PanelLink products are designed on
scaleable CMOS architecture to support future performance requirements
while maintaining the same logical interface, system designers can be
assured that the interface will be fixed through a number of technology and
performance generations.
the system level issues associated with high-speed digital design, providing
the system designer with a digital interface solution that is quicker to market
and lower in cost.
Si
Revision C
I
I
D I O 2 0
D I O 1 9
D I O 1 8
D I O 1 7
D I O 1 6
D I O 1 5
D I O 1 4
D I O 1 3
D I O 1 2
D I O 1 1
D I O 1 0
I V C C
150A Pin Diagram
D I O 9
D I O 8
D I O 7
D I O 6
D I O 5
D I O 4
D I O 3
D I O 2
D I O 1
D I O 0
V C C
G N D
G N D
150A
As the universal transmitter, SiI 150A uses PanelLink Digital technology
PanelLink Digital technology simplifies PC design by resolving many of
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
6 5
6 6
6 7
6 8
6 9
7 0
7 1
7 2
7 3
7 4
7 5
C O N T R O L S
®
Digital Transmitter
G P I
D I F F E R E N T I A L
P L L
1 0 0- P i n T Q F P
S I G N A L
S i I 1 5 0 A
(Top View)
EVEN 8-bits RED
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
8
7
6
5
4
3
2
1
P I X S
E D G E
R E S E R V E D
R E S E R V E D
R E S E R V E D
R E S E R V E D
P G N D 1
P V C C 1
I V C C
D I E 0
D I E 1
D I E 2
D I E 3
D I E 4
D I E 5
D I E 6
D I E 7
V C C
G N D
D I E 8
D I E 9
D I E 1 0
D I E 1 1
D I E 1 2
D I E 1 3
Features
Scaleable Bandwidth: 25-112 MHz (VGA to SXGA)
Low Power: 3.3V core operation & power-down
mode
High Skew Tolerance: 1 full input clock cycle (9ns at
108 MHz)
Flexible panel interface: single or dual pixel in at up
to 24-bits
Cable Distance Support: over 5m with twisted-pair,
fiber-optics ready
Compliant with DVI 1.0 (DVI is backwards
compatible with VESA® P&D
Functional Block Diagram
E X T _ S W I N G
DIE[23:0]
DIO[23:0]
D E
H S Y N C
V S Y N C
C T L 1
C T L 2
C T L 3
E D G E
P I X S
I D C K
Subject to Change without Notice
2 4
2 4
Capture
Logic
D a t a
D A T A
H S Y N C
V S Y N C
D A T A
C T L 1
D A T A
C T L 2
C T L 3
Filter
Jitter
TM
and DFP)
Encoder
Encoder
Encoder
P L L
0
1
2
July 2000
Control
S w i n g
T x C
T x 0
T x 1
T x 2
T x 0 +
T x0 -
T x 1 +
T x1 -
T x 2 +
T x2 -
T x C +
T x C -

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SII150ACT100 Summary of contents

Page 1

I Si 150A ® PanelLink Digital Transmitter General Description As the universal transmitter, SiI 150A uses PanelLink Digital technology to support displays ranging from VGA to SXGA (25-112 MHz). The SiI 150A transmitter supports up to true color panels (24 ...

Page 2

Silicon Image, Inc. Absolute Maximum Conditions Note: Permanent device damage may occur if absolute maximum conditions are exceeded. Functional operation should be restricted to the conditions described under Normal Operating Conditions. Symbol Parameter V Supply Voltage 3. Input ...

Page 3

Silicon Image, Inc. AC Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter T IDCK Period, 1 Pixel/Clock CIP F IDCK Frequency, 1 Pixel/Clock CIP T IDCK Period, 2 Pixels/Clock CIP F IDCK Frequency, 2 Pixels/Clock CIP T IDCK ...

Page 4

Silicon Image, Inc. Input Timing D[23:0], DE CTL[3: 0 ...

Page 5

Silicon Image, Inc. Configuration Pin Description Pin Name Pin # Type Description EDGE 24 In Data/Control Latching Edge. A low level indicates that all input signals (DIE/DIO[23:0], HSYNC, VSYNC, DE, and CTL[3:1]) are latched on the falling edge of IDCK, ...

Page 6

... Ordering Information Part Number SiI150ACT100 Copyright Notice This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or send/transmit any part of this documentation without the express written permission of Silicon Image, Inc. ...

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