TC9204M IC Plus, TC9204M Datasheet
TC9204M
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TC9204M Summary of contents
Page 1
... Mbit/s. Each port includes dedicated receive and transmit FIFOs with necessary logic to implement flow control for both full and half duplex modes. TC9204M uses IEEE 802.3x frame based flow control for full duplex and backpressure for half duplex. ...
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... Block Diagram Confidential. Copyright © 2003, IC Plus Corp. 208 PQFP. EEprom Interface Configuration Register From RX MAC Rx FIFO Tx FIFO To TX MAC Address LoockUp & Resolution Unit 2/49 TC9204M Preliminary Data Sheet Queue Management Memory Interface & Arbiter Internal SSRAM Buffer July 29, 2003 TC9204M-DS-R05 ...
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... Data Read Register .............................................................................................. 44 11 Timing Requirements................................................................................................................................45 11.1 GMII / MII Receive Timing Requirements .......................................................................... 45 11.2 GMII / MII Transmit Timing................................................................................................. 45 11.3 PHY Management (MDIO) Timing ..................................................................................... 46 11.4 EEPROM Timing................................................................................................................ 47 12 Electrical Specifications ............................................................................................................................48 12.1 ABSOLUTE MAXIMUM RATINGS..................................................................................... 48 12.2 RECOMMENDED OPERATING CONDITIONS ................................................................ 48 Confidential. Copyright © 2003, IC Plus Corp. Preliminary Data Sheet 3/49 TC9204M July 29, 2003 TC9204M-DS-R05 ...
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... TC9204-DS-R04 TC9204-DS-R05 1. Modify “Pin Latched” field in Class of Service section. 2. Correct the register map of “Broadcast Configuration Register” 3. Correct the junction temperature limit. Confidential. Copyright © 2003, IC Plus Corp. Preliminary Data Sheet Change Description 4/49 TC9204M July 29, 2003 TC9204M-DS-R05 ...
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... July 29, 2003 TC9204M-DS-R05 Gnd Vdd 2.0 Gnd Vss 3.3 VLANPrMap0 Vdd 3.3 VLANPrMAp1 EnVLANPr IPTosMap0 IPTosMap1 EnlPPr rxd27 rxd26 rxd25 rxd24 rxd23 Vss 3 ...
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... MII collision indication Receive Error Digital +2.0V power supply for core MII receive clock GMII/MII data valid GMII receive data - least significant nibble. MII receive data GMII receive data - least significant nibble. MII receive data 6/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... PriClass[0] – ‘00’ – port 0 has low priority PriClass[0] – ‘01’ – port 0 has normal priority PriClass[0] – ‘10’ – port 0 has high priority PriClass[0] – ‘11’ – port 0 has very high priority PriClass[0] is latched on reset 7/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... Selsck – ‘1’ – sysck is driven by a 25Mhz external clock. Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use 8/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... PriClass[2] - '10' - port 2 has high priority PriClass[2] - '11' - port 2 has very high priority PriClass[2] is latched on reset GMII/MII transmit enable GMII transmit clock Digital ground for core Transmit Error MII transmit clock MII carrier sense indication 9/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... VLAN Tag Header. ‘1’ – VLAN priority will be taken into consideration ‘0’ – VLAN priority will be neglected EnVLANPr is latched on reset VLAN priority mapping VLANPrMap(1)is latched on reset. Digital +3.3V power supply for I/O 10/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... Enables/disables flow control for broadcast packets. '1' – enabled '0' – disabled FcBcstEn is latched on reset. GMII/MII transmit data - bit 3 Digital ground for core GMII/MII transmit data - bit 2 GMII/MII transmit data - bit 1 Priority class - most significant bit. PriClass[4] is latched on reset. 11/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... The backpressure time limit is based in the EEPROM’s BPTimeValue register. When this configuration is ‘0’ the backpressure process will also be limited from exceeding 28-consecutive collisions. The default value (28) can be changed in the EEPROM settings. FullBp is latched upon reset 12/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... Reserved for future use Reserved for future use Digital +2.0V power supply for core MDIO Clock. MDIO Data. Digital ground for core EEPROM's serial clock. EEPROM's serial data. TestInt - '0' - switch normal mode(default) TestInt -'1' - internal memory test mode. 13/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... TC9204M will set a decremental timer in the pause counter according to the value of the pausing period. A non-zero value sets in the pause counter will issue the Receive MAC to XOFF (Transmit Stop) the Transmit MAC. The pause counter will decrement the ‘ ...
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... Underrun conditions never occur if the system is operating at the recommended clock frequency or higher. For full duplex mode TC9204M implements the flow control algorithm according to the IEEE 802.3x standard, using the XON/XOFF method. Full duplex flow control can be configured automatically, by auto-negotiation result, or manually, pin configuration and/or EEPROM settings, to enable/disable the function ...
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... Normal and priority transmission queues are implemented within TC9204M for each port. All available frame buffers are shared between all transmission queues and each queue can fully extend to all buffers. Still memory resource utilization is limited on receive port basis ...
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... Classes of Service TC9204M implements advanced Class of Service (CoS), supporting both traffic priority and delay bound features. It provides four classes of service: class 0 (low), class 1 (normal), class 2 (high) and class 3 (very high). Each class of service has its dedicated transmission queue for each port. The frames assign with higher service class will arrive sooner at the destination ...
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... Selects one of four mappings for the 8 level user_priority extracted from the frame’s VLAN Tag to the 4 level priority offered by TC9204M (C0, C1, C2, C3 – class service) Designated priority class VLANPrMap[1: ...
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... If enabled, direct flow control addressing can be executed. This implies inserting the port address each flow control frame generated by TC9204M and recognizing as flow control all received frames with the port’s address as DA, MAC control type and PAUSE opcode. ...
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... EEPROM setting HUB is connected to many workstations, one of the ports may be partitioned in heavy traffic when the switch executes backpressure. TC9204M can prevent this by discontinuing the backpressure process after a predefined number of consecutive collisions have reached. This function can be enabled using the shared configuration pin FullBP or adjusting EEPROM setting ...
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... Port Mirroring Although TC9204M is a smart switch, it has the ability to set a pair of mirroring ports. This feature is available only through EEPROM settings. The port mirroring feature can be enabled by setting a value of ‘1’ in either EnTxMirror field from EEPROM’s PortMirrorConfig register or EnRxMirror field from the same register, or both. When port-mirroring feature has been enabled, the SourcePort field from EEPROM’ ...
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... Gigabit speed will be disabled. 01 – Advertise one mode: Auto-Negotiation Enable is checked and if found to be disabled TC9204M will attempt to enable it. If successful the switch will force the port’s speed and duplex mode by advertising only the technology corresponding to the Speed and Duplex fields from EEPROM's ConfigRegP[x], otherwise bits 0 ...
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... The EEPROM can be reprogrammed using an external parallel port. A dedicated signal from this port can be used to hold the RESET pin Low. Once the TC9204M interface pins have got to the high impedance state the EEPROM can be programmed by the parallel port trough the SDA and SCL pins. ...
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... Port 6 Configuration Register Reserved IFGConfigP0 Port 0 IFG Configuration IFGConfigP2 Port 2 IFG Configuration IFGConfigP4 Port 4 IFG Configuration IFGConfigP6 Port 6 IFG Configuration Reserved FlowContrReg Flow Control Register BPTimeValue Backpressure Time Value Register FCBaseAddress Flow Control Source Base Address Register 24/49 TC9204M July 29, 2003 TC9204M-DS-R05 ...
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... ID 4 virtual LAN Register Reserved PVIDEn ID 5 virtual LAN Register Reserved PVIDEn ID 6 virtual LAN Register Reserved PVIDEn ID 7 virtual LAN Register Reserved - Data Write Register - Phy Address Register - Phy's Register Address Register - IO Control Register - Data Read Register 25/49 TC9204M July 29, 2003 TC9204M-DS-R05 ...
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... ConfigRegP0 Reserved ConfigRegP2 Reserved ConfigRegP4 Reserved ConfigRegP6 Reserved not used IFGConfigP0 Reserved IFGConfigP2 Reserved IFGConfigP4 Reserved IFGConfigP6 Reserved not used FlowContrReg BPTimeValue Reserved BroadcastConfig IPTosMapping VLANPriMapping QoSBandwidth Reserved QoSConfig PortMirrorReg GeneralConfig not used PortVLANEn not used July 29, 2003 TC9204M-DS-R05 ...
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... Port Mirroring Register GeneralConfig – validation bit for General Configuration Register PortVLANEn – validation bit for Port VLAN Enable Register Confidential. Copyright © 2003, IC Plus Corp. Description EEPROM’s Configuration Registers Validation Register 27/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... ANMode This field selects the way auto-negotiation advertisements are configured by the TC9204M’s physical layer management polling entity and the way Phy speed and duplex modes are extracted from management registers. It can enable EEPROM forced modes that also use Duplex and Speed bits below to configure the Phy mode. ...
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... Setting this bit to '1' will force the corresponding port to the priority set within the PortPriority field, otherwise the pin configuration will be used. PortPriority This bit will set one of the four priority classes on the corresponding port. Confidential. Copyright © 2003, IC Plus Corp. Preliminary Data Sheet 29/49 TC9204M July 29, 2003 TC9204M-DS-R05 ...
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... Copyright © 2003, IC Plus Corp. IFGConfig RedGbBndw GbBndwSel not used Description Interframe Gap Configuration Reduced gigabit bandwidth Gigabit bandwidth selection not used IFG (bit time (default) 128 … 480 512 Transmission bandwidth 50% 66% 80% 90% 30/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... BPMaxCol field. Default value is its corresponding FullBP pin value. BPMaxCol Specifies the number of consecutive collisions that will determine TC9204M to quit backpressure (see the setting above). Default is ‘011100’ (28). BPSkip1 If FullBP setting is configured to ‘0’ and a number of BPMaxCol collisions is reached, the MAC will ensure receiving the next packet without colliding it if this bit is set to ‘ ...
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... DisBPBk pin value. FrcFdxFC Setting this bit to ‘1’ will instruct TC9204M to disregard the auto-negotiation result for the full duplex flow control ability. Link partner will be considered full duplex flow control able. This setting is effective only for ports configured in 10/100 Mbps speed modes. Default is ‘ ...
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... Contains a 48-bit MAC address used to generate the individual port address used in direct flow control addressing. The port addresses are obtained by incrementing this base address and assigning the result to the TC9204M’s ports starting with port 0. The least significant 5 bits of this address will be ignored and replaced with ‘0’, so these bits will encode the port number in the actual port address ...
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... BcstThrot Reserved not used Description Source port loading limit for broadcast Flow control broadcast enable Flow control broadcast mode not used Global buffer pool loading threshold for broadcast Broadcast throttling (bandwidth) not used 34/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... IP precedence 2 priority mapping for IP precedence 3 priority mapping for IP precedence 4 priority mapping for IP precedence 5 priority mapping for IP precedence 6 priority mapping for IP precedence 7 CoS 00 Class 0 priority 01 Class 1 priority 10 Class 2 priority 11 Class 3 priority 35/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... VLAN user_priority 3 priority mapping for VLAN user_priority 4 priority mapping for VLAN user_priority 5 priority mapping for VLAN user_priority 6 priority mapping for VLAN user_priority 7 CoS 00 Class 0 priority 01 Class 1 priority 10 Class 2 priority 11 Class 3 priority 36/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... The weight for priority class 2 queue not used The weight for priority class 3 queue not used f(“100” f(“101” f(“110”) = not used f(“111”) = not used 37/49 TC9204M Preliminary Data Sheet 3 Σ ( F(CoS[n]Weight July 29, 2003 TC9204M-DS-R05 ...
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... This configuration can be used especially when CoSResolution setting is ‘0’. Default is “01” (CoS 1). Confidential. Copyright © 2003, IC Plus Corp. Description Enable IP priority Enable VLAN priority CoS Resolution Mode VLAN Precedence Default Class of Service not used 38/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... EnRxMirror EnTxMirror not used not used not used Description Source port(monitored port) not used Destination port(monitoring port) not used Enable mirroring on receiving packets Enable mirroring on transmitting packets not used not used not used 39/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... Default is ‘01’(600 seconds). DisAging Setting this bit to '1' will cause TC9204M to disable its aging mechanism for the stored MAC addresses. Default is '0'. FwdBadCRC Setting this bit to ‘1’ will enable forwarding of bad CRC packets. Default is '0'. ...
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... VLAN 1 enable VLAN 2 enable VLAN 3 enable Description Port 0 membership to VLAN y Port 2 membership to VLAN y Port 4 membership to VLAN y Port 6 membership to VLAN y 41/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... DeviceAddress – Contains a 5 bit word used as device address in MDIO operations. Confidential. Copyright © 2003, IC Plus Corp. DataW riteReg Description MDIO Data Write Register Description Physical layer device address register not used 42/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... MDIO error. ‘0’- MDIO read successful. Confidential. Copyright © 2003, IC Plus Corp. Description Physical layer device’s register address register not used Description Operation code Valid Data Read MDIO Error not used 43/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... IOControl’s bit 2. The ValidDataRead bit is always read as ‘1’ unless the EEPROM line is driven at over 1MHz speed error occurred then data can be read from DataReadReg. Confidential. Copyright © 2003, IC Plus Corp. DataReadReg Description MDIO Data Read Register 44/49 TC9204M Preliminary Data Sheet July 29, 2003 TC9204M-DS-R05 ...
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... Confidential. Copyright © 2003, IC Plus Corp. Description T Rx_Clk T hRx_Clk T sRx_Clk GMII / MII Receive Description T Tx_Clk T dTx_Clk GMII / MII Transmit 45/49 TC9204M Preliminary Data Sheet Min. Typ. Max. Unit - 0 Min. Typ. Max. Unit - July 29, 2003 TC9204M-DS-R05 ...
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... MDIO hold time mh MDClk MDIO MDClk MDIO Confidential. Copyright © 2003, IC Plus Corp. Description T ms MDIO Write Cicle MDIO Read Cicle 46/49 TC9204M Preliminary Data Sheet Min. Typ. Max. Unit - 300 - ns - 300 - ns - 600 - July 29, 2003 TC9204M-DS-R05 ...
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... LOW HIGH t t HD.STA HD.DAT t SU.DAT VALID VALID VALID EEPROM Interface Timing 47/49 TC9204M Preliminary Data Sheet Min. Typ. Max. Unit - 66.6 - KHz 4 SU.STO BUF VALID July 29, 2003 TC9204M-DS-R05 ...
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... V 0.93 1. +/- +/- 48/49 TC9204M Preliminary Data Sheet MAX. UNIT 4 +150 °C 70 °C mA MAX. UNIT 3.6 V 2.05 V 125 °C 1.0 V 5.5 V MAX. UNIT 0 17.0 mA 40.0 mA 1.76 V 1.79 V 1.06 V +/-1000 nA +/-1000 nA 122 KΩ 127 KΩ July 29, 2003 TC9204M-DS-R05 ...
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... Hsin-Chu City, Taiwan 300, R.O.C. TEL : 886-3-575-0275 FAX : 886-3-575-0475 Website: www.icplus.com.tw Confidential. Copyright © 2003, IC Plus Corp. Preliminary Data Sheet Sales Office 4F, No. 106, Hsin-Tai-Wu Road, Sec.1, Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C. TEL : 886-2-2696-1669 FAX : 886-2-2696-2220 49/49 TC9204M July 29, 2003 TC9204M-DS-R05 ...