VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 
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I/O Offset 08h – SMBus Slave Control ............................ RW
7-4
Reserved
........................................ always reads 0
3
SMBus Alert Enable
0
Disable ...................................................default
1
Enable generation of an interrupt or resume
event on the assertion of the SMBALERT#
signal
2
SMBus Shadow Port 2 Enable
0
Disable ...................................................default
1
Enable generation of an interrupt or resume
event on external SMBus master generation of
a transaction with an address that matches the
SMBus Slave Shadow Port 2 register (PCI
function 4 configuration register RxD5).
1
SMBus Shadow Port 1 Enable
0
Disable ...................................................default
1
Enable generation of an interrupt or resume
event on external SMBus master generation of
a transaction with an address that matches the
SMBus Slave Shadow Port 1 register (PCI
function 4 configuration register RxD4).
0
SMBus Slave Enable
0
Disable ...................................................default
1
Enable generation of an interrupt or resume
event on external SMBus master generation of
a transaction with an address that matches the
SMBus host controller slave port of 10h, a
command field which matches the SMBus
Slave Command register (PCI function 4
configuration register RxD3), and a match of
one of the corresponding enabled events in the
SMBus Slave Event Register (I/O Offset 0Ah).
Revision 1.71 June 9, 2000
I/O Offset 09h – SMBus Shadow Command ................... RO
This register is used to store command values for external
SMBus master accesses to the host slave and slave shadow
ports.
7-0
Shadow Command....................................default = 0
This field contains the command value which was
received during an external SMBus master access
whose address field matched the host slave address
(10h) or one of the slave shadow port addresses.
I/O Offset 0Ah – SMBus Slave Event ............................. RW
This register is used to enable generation of interrupt or
resume events for accesses to the host controller’s slave port.
15-0 SMBus Slave Event ..................................default = 0
This field contains data bits used to compare against
incoming data to the SMBus Slave Data Register (I/O
Offset 0Ch). When a bit in this register is set and the
corresponding bit the Slave Data register is also set,
an interrupt or resume event will be generated if the
command value matches the value in the SMBus
Slave Command register and the access was to
SMBus host address 10h.
I/O Offset 0Ch – SMBus Slave Data ................................ RO
This register is used to store data values for external SMBus
master accesses to the shadow ports or the SMBus host
controller’s slave port.
15-0 SMBus Slave Data ....................................default = 0
This field contains the data value which was
transmitted during an external SMBus master access
whose address field matched one of the slave shadow
port addresses or the SMBus host controller slave
port address of 10h.
-101-
System Management Bus I/O-Space Registers
VT82C686B