VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Page 21
22
Page 22
23
Page 23
24
Page 24
25
Page 25
26
Page 26
27
Page 27
28
Page 28
29
Page 29
30
Page 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Page 24/128:

ISA Bus Interface

Download datasheet (2Mb)Embed
PrevNext
7HFKQRORJLHV ,QF
Signal Name
Pin #
SA[19:16],
K1, K2, P3, P4,
SA[15-0] /
P5, R1, R2, R3,
SDD[15-0]
R4, R5, T1, T2,
T3, T4, U1, U2,
U3, V1, V2,
W1
J2, J3, J4, J5
LA[23:20]
SD[15:0]
P2, P1, N5, N3,
N1, M4, M2,
L5, W4, Y4,
V3, W3, Y3,
W2, Y2, Y1
SBHE#
F2
IOR#
D1
IOW#
C2
MEMR#
U4
MEMW#
V4
SMEMR#
A1
SMEMW#
B1
BALE
H2
F3
IOCS16#
F1
MCS16#
F4
IOCHCK# /
GPI0
IOCHRDY
A2
AEN
B2
Revision 1.71 June 9, 2000

ISA Bus Interface

I/O
Signal Description
IO
System Address Bus. SA[19-16] are connected to ISA bus SA[19-16] directly.
IO
SA[19-17] are also connected to LA[19-17] of the ISA bus. If the audio interface is
disabled (SPKR pin strapped low), SA[15-0] are connected directly to ISA address
bus pins SA[15-0] (the audio interface pins are used for the IDE secondary data bus).
If the audio interface is enabled (SPKR pin strapped high), SA[15-0] are multiplexed
with the IDE Secondary Data Bus. In this case, SA[15-0] may be connected to both
SDD[15-0] and ISA bus SA[15-0]. However, if ISA address bus loading is a
concern, 74F245 transceivers may be used to externally drive ISA address bus pins
SA[15-0]. In this case, these pins would connect directly to the IDE secondary data
bus and to the transceiver “A” pins and the ISA address bus would connect to the
transceiver “B” pins. SOE# would be used to control the transceiver output enables
and the ISA bus MASTER# signal would drive the transceiver direction controls.
IO
System “Latched” Address Bus: The LA[23:20] address lines are bi-directional.
These address lines allow accesses to physical memory on the ISA bus up to
16Mbytes. LA[19-17] on the ISA bus are connected to SA[19-17] (see notes above).
IO
System Data. SD[15:0] provide the data path for devices residing on the ISA bus.
X-Bus data signals XD[7:0] may be derived if needed from SD[7:0] using an
external 74F245-type transceiver (see the XDIR pin description for transceiver
connection details).
SD7:4 are strap options for keyboard inputs 6:3 (see Function 0 Rx5A)
IO
System Byte High Enable. SBHE# indicates, when asserted, that a byte is being
transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is negated during
refresh cycles.
IO
I/O Read. IOR# is the command to an ISA I/O slave device that the slave may drive
data on to the ISA data bus.
IO
I/O Write. IOW# is the command to an ISA I/O slave device that the slave may
latch data from the ISA data bus.
IO
Memory Read. MEMR# is the command to a memory slave that it may drive data
onto the ISA data bus.
IO
Memory Write. MEMW# is the command to a memory slave that it may latch data
from the ISA data bus.
O
Standard Memory Read. SMEMR# is the command to a memory slave, under
1MB, which indicates that it may drive data onto the ISA data bus
O
Standard Memory Write. SMEMW# is the command to a memory slave, under
1MB, which indicates that it may latch data from the ISA data bus.
O
Bus Address Latch Enable.
VT82C686B to indicate that the address (SA[19:0], LA[23:17] and the SBHE#
signal) is valid
I
16-Bit I/O Chip Select. This signal is driven by I/O devices on the ISA Bus to
indicate that they support 16-bit I/O bus cycles.
I
Memory Chip Select 16. ISA slaves that are 16-bit memory devices drive this line
low to indicate they support 16-bit memory bus cycles.
I
I/O Channel Check (Rx74[0] = 1). When this signal is asserted, it indicates that a
parity or an uncorrectable error has occurred for an I/O or memory device on the
ISA Bus. The same pin may optionally be used as General Purpose Input 0.
I
I/O Channel Ready (Rx74[0] = 1). This signal is normally high. Devices on the
ISA Bus assert IOCHRDY low to indicate that additional time (wait states) is
required to complete the cycle.
O
Address Enable. AEN is asserted during DMA cycles to prevent I/O slaves from
misinterpreting DMA cycles as valid I/O cycles.
-18-
BALE is an active high signal asserted by the
VT82C686B
Pinouts