VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 
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7HFKQRORJLHV ,QF
PCI Function 0 Registers – PCI-to-ISA Bridge
Configuration Space PCI-to-ISA Bridge Header Registers
Offset PCI Configuration Space Header
1-0 Vendor ID
3-2 Device ID
5-4 Command
7-6 Status
8
Revision ID
9
Programming Interface
A
Sub Class Code
B
Base Class Code
C
-reserved- (cache line size)
D
-reserved- (latency timer)
E
Header Type
F
Built In Self Test (BIST)
10-27 -reserved- (base address registers)
28-2B -reserved- (unassigned)
2F-2C Subsystem ID Read
30-33 -reserved- (expan. ROM base addr)
34-3B -reserved- (unassigned)
3C
-reserved- (interrupt line)
3D
-reserved- (interrupt pin)
3E
-reserved- (min gnt)
3F
-reserved- (max lat)
Configuration Space PCI-to-ISA Bridge-Specific Registers
Offset ISA Bus Control
40
ISA Bus Control
41
ISA Test Mode
42
ISA Clock Control
43
ROM Decode Control
44
Keyboard Controller Control
45
Type F DMA Control
46
Miscellaneous Control 1
47
Miscellaneous Control 2
48
Miscellaneous Control 3
49
-reserved-
4A
IDE Interrupt Routing
4B
-reserved-
4C
DMA / Master Mem Access Control 1
4D
DMA / Master Mem Access Control 2
4F-4E DMA / Master Mem Access Control 3
Offset Plug and Play Control
50
PnP DMA Request Control
51
PnP Routing for LPT / FDC IRQ
52
PnP Routing for COM2 / COM1 IRQ
53
-reserved-
Revision 1.71 June 9, 2000
Default
Acc
Offset Plug and Play Control (cont’d)
RO
54
PCI IRQ Edge / Level Select
1106
0686
RO
55
PnP Routing for PCI INTA
56
PnP Routing for PCI INTB-C
0087
RW
0200
WC
57
PnP Routing for PCI INTD
RO
58
APIC IRQ Output Control
nn
00
RO
59
-reserved-
RO
5A
KBC / RTC Control
01
06
RO
5B
Internal RTC Test Mode
00
5C
DMA Control
00
5D-5E -reserved-
80
RO
5F
-reserved- (do not program)
00
RO
† Bit 7-4 power-up default depends on external strapping
00
Offset Distributed DMA
00
61-60 Channel 0 Base Address / Enable
00
RO
63-62 Channel 1 Base Address / Enable
00
65-64 Channel 2 Base Address / Enable
00
67-66 Channel 3 Base Address / Enable
00
69-68 Serial IRQ Control
00
6B-6A Channel 5 Base Address / Enable
00
6D-6C Channel 6 Base Address / Enable
00
6F-6E Channel 7 Base Address / Enable
Offset Miscellaneous
Default
Acc
70
Subsystem ID Write
00
RW
71-73 -reserved-
00
RW
74
GPIO Control 1
00
RW
75
GPIO Control 2
00
RW
76
GPIO Control 3
00
RW
77
GPIO Control 4
00
RW
79-78 PCS0# I/O Port Address
00
RW
7B-7A PCS1# I/O Port Address
00
RW
7D-7C PCI DMA Channel Enable
RW
01
7F-7E 32-Bit DMA Control
00
80
Programmable Chip Select Mask
RW
04
81
ISA Positive Decoding Control 1
00
82
ISA Positive Decoding Control 2
00
RW
83
ISA Positive Decoding Control 3
00
RW
84
ISA Positive Decoding Control 4
RW
0300
85
Extended Function Enable
86-87 PnP IRQ/DRQ Test (do not program)
Default
Acc
88
PLL Test
2D
RW
89
PLL Control
00
RW
8A
PCS2/3 I/O Port Address Mask
00
RW
8B
PCS Control
00
8D-8C PCS2# I/O Port Address
8F-8E PCS3# I/O Port Address
90-FF -reserved-
-30-
VT82C686B
Default
Acc
00
RW
00
RW
00
RW
00
RW
00
RW
04
RW
x4†
00
RW
00
RW
00
04
RW
Default
Acc
0000
RW
0000
RW
0000
RW
0000
RW
0000
RW
0000
RW
0000
RW
0000
RW
Default
Acc
00
WO
00
00
RW
00
RW
00
RW
10
RW
0000 0000 RW
0000 0000 RW
0000
RW
0000
RW
00
RW
00
RW
00
RW
00
RW
00
RW
00
RW
00
RW
00
RW
00
RW
00
RW
00
RW
0000
RW
0000
RW
00
Register Overview