VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 


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Parallel Port Registers
These registers are located at I/O ports which are offsets from
“LPTBase” (index E6h of the Super-I/O configuration
registers). LPTBase is typically set to allow these ports to be
accessed at the standard parallel port address range of 378-
37Fh.
Port LPTBase+0 – Parallel Port Data ............................. RW
7-0
Parallel Port Data
Port LPTBase+1 – Parallel Port Status ............................ RO
7
BUSY#
0
Printer busy, offline, or error
1
Printer not busy
6
ACK#
0
Data transfer to printer complete
1
Data transfer to printer in progress
5
PE
0
Paper available
1
No paper available
4
SLCT
0
Printer offline
1
Printer online
3
ERROR#
0
Printer error
1
Printer OK
2-0
Reserved
................................... always read 1 bits
Port LPTBase+2 – Parallel Port Control ........................ RW
Undefined ................................. always read back 1
7-5
4
Hardware Interrupt
0
Disable ...................................................default
1
Enable
3
Printer Select
0
Deselect printer ......................................default
1
Select printer
2
Printer Initialize
0
Initialize Printer......................................default
1
Allow printer to operate normally
1
Automatic Line Feed
0
Host handles line feeds...........................default
1
Printer does automatic line feeds
0
Strobe
0
No data transfer ......................................default
1
Transfer data to printer
Revision 1.71 June 9, 2000
Port LPTBase+3 – Parallel Port EPP Address............... RW
Port LPTBase+4 – Parallel Port EPP Data Port 0 ......... RW
Port LPTBase+5 – Parallel Port EPP Data Port 1 ......... RW
Port LPTBase+6 – Parallel Port EPP Data Port 2 ......... RW
Port LPTBase+7 – Parallel Port EPP Data Port 3 ......... RW
Port LPTBase+400h – Parallel Port ECP Data / Cfg A RW
Port LPTBase+401h – Parallel Port ECP Config B ....... RW
Port LPTBase+402h – Parallel Port ECP Extd Ctrl ...... RW
7-5
Parallel Port Mode Select
000 Standard Mode....................................... default
001 PS/2 Mode
010 FIFO Mode
011 ECP Mode
100 EPP Mode
101 -reserved-
110 -reserved-
111 Configuration Mode
4
Parallel Port Interrupt Disable
0
Enable an interrupt pulse to be generated on
the high to low edge of the fault. An interrupt
will also be generated if the fault condition is
asserted and this bit is written from 1 to 0.
1
Disable the interrupt generated on the asserting
edge of the fault condition
3
Parallel Port DMA Enable
0
Disable DMA unconditionally
1
Enable DMA
2
Parallel Port Interrupt Pending
0
Interrupt not pending
1
Interrupt pending (DMA & interrupts disabled)
This bit is set to 1 by hardware and must be written to
0 to re-enable interrupts
1
FIFO Full
......................................................... RO
0
FIFO has at least 1 free byte
1
FIFO full or cannot accept byte
0
FIFO Empty......................................................... RO
0
FIFO contains at least 1 byte of data
1
FIFO is completely empty
-49-
Register Descriptions - Super-I/O I/O Ports
VT82C686B