VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Page 61
62
Page 62
63
Page 63
64
Page 64
65
Page 65
66
Page 66
67
Page 67
68
Page 68
69
Page 69
70
Page 70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Page 62/128

Download datasheet (2Mb)Embed
PrevNext
7HFKQRORJLHV ,QF
Offset 42 - ISA Clock Control. ......................................... RW
7
Latch IO16#
0
Enable (recommended setting) ...............default
1
Disable
6
MCS16# Output
0
Disable ...................................................default
1
Enable
Master Request Test Mode (do not program)
5
0
Disable ...................................................default
1
Enable
Reserved (Do Not Program) ................... default = 0
4
3
ISA Clock (BCLK) Select Enable
0
BCLK = PCICLK / 4..............................default
1
BCLK selected per bits 2-0
2-0
ISA Bus Clock Select (if bit-3 = 1)
000 BCLK = PCICLK / 3..............................default
001 BCLK = PCICLK / 2
010 BCLK = PCICLK / 4
011 BCLK = PCICLK / 6
100 BCLK = PCICLK / 5
101 BCLK = PCICLK / 10
110 BCLK = PCICLK / 12
111 BCLK = OSC / 2
Note: Procedure for ISA Clock switching:
1) Set bit 3 to 0; 2) Change value of bit 2-0; 3) Set bit 3 to 1
Revision 1.71 June 9, 2000
Offset 43 - ROM Decode Control .................................... RW
Setting these bits enables the indicated address range to be
included in the ROMCS# decode:
FFFE0000h-FFFEFFFFh ..........................default=0
7
6
FFF80000h-FFFDFFFFh...........................default=0
5
FFF00000h-FFF7FFFFh............................default=0
4
000E0000h-000EFFFFh ............................. default=0
000D8000h-000DFFFFh............................. default=0
3
2
000D0000h-000D7FFFh ............................. default=0
000C8000h-000CFFFFh............................. default=0
1
0
000C0000h-000C7FFFh ............................. default=0
Offset 44 - Keyboard Controller Control ....................... RW
7
KBC Timeout Test (do not program)........default = 0
Reserved (do not program) ........................default = 0
6-4
3
Mouse Lock Enable
0
Disable................................................... default
1
Enable
2-1
Reserved (do not program) ........................default = 0
0
Reserved (no function) ..............................default = 0
Offset 45 - Type F DMA Control .................................... RW
7
ISA Master / DMA to PCI Line Buffer
0
Disable................................................... default
1
Enable
6
DMA type F Timing on Channel 7............default=0
5
DMA type F Timing on Channel 6............default=0
4
DMA type F Timing on Channel 5............default=0
3
DMA type F Timing on Channel 3............default=0
2
DMA type F Timing on Channel 2............default=0
1
DMA type F Timing on Channel 1............default=0
0
DMA type F Timing on Channel 0............default=0
Note:
For bits 0-6 above, see also Rx41[3]
-56-
Function 0 Registers - PCI to ISA Bridge
VT82C686B