VT82C686B

Manufacturer Part NumberVT82C686B
ManufacturerETC-unknow
VT82C686B datasheet
 


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Offset 5A – KBC / RTC Control ...................................... RW
Bits 7-4 of this register are latched from pins SD7-4 at power-
up but are read/write accessible so may be changed after
power-up to change the default strap setting:
Keyboard RP16 ............................. latched from SD7
7
6
Keyboard RP15 ............................ latched from SD6
Keyboard RP14 ............................ latched from SD5
5
4
Keyboard RP13 ............................ latched from SD4
3
Audio Function Enable
....... RO, strapped from SPKR pin V5
0
Disable (SDD pins function as SDD)
1
Enable (SDD pins function as Audio / Game)
2
Internal RTC Enable
0
Disable
1
Enable ....................................................default
1
Internal PS2 Mouse Enable
0
Disable ..................................................default
1
Enable
0
Internal KBC Enable
0
Disable ..................................................default
1
Enable
Note:
External strap option values may be set by connecting
the indicated external pin to a 4.7K ohm pullup (for
1) or driving it low during reset with a 7407 TTL
open collector buffer (for 0) as shown in the
suggested circuit below:
Figure 5. Strap Option Circuit
Revision 1.71 June 9, 2000
Offset 5B - Internal RTC Test Mode .............................. RW
7-4
Reserved
........................................always reads 0
3
Map RTC Rx32 to Rx3F
0
Disable................................................... default
1
Enable
2
RTC Reset Enable (do not program)
0
Disable................................................... default
1
Enable
1
RTC SRAM Access Enable
0
Disable................................................... default
1
Enable
This bit is set if the internal RTC is disabled but it is
desired to still be able to access the internal RTC
SRAM via ports 74-75.
enabled, setting this bit does nothing (the internal
RTC SRAM should be accessed at either ports 70/71
or 72/73.
0
RTC Test Mode Enable (do not program) .default=0
Offset 5C - DMA Control ................................................. RW
7
PCS0# & PCS1# 16-Bit I/O
0
Disable................................................... default
1
Enable
6
Passive Release
0
Disable................................................... default
1
Enable
5
Internal Passive Release
0
Disable................................................... default
1
Enable
4
Dummy PREQ
0
Disable................................................... default
1
Enable
3
Reserved
........................................always reads 0
2
APIC Connection
0
APIC on SD Bus.................................... default
1
APIC on XD Bus
1
Reserved (Do Not Program) ....................default = 0
0
DMA Line Buffer Disable
0
DMA cycles can be to/from line buffer ....... def
1
Disable DMA Line Buffer
-60-
Function 0 Registers - PCI to ISA Bridge
VT82C686B
If the internal RTC is