CH7005C-T Chrontel, CH7005C-T Datasheet

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... PC solution using the primary display. LINE YUV-RGB CONVERTER MEMORY TRUE SCALE SCALING & DEFLICKERING ENGINE SYSTEM CLOCK PLL RESET* XCLK H Figure 1: Functional Block Diagram CH7005C TM D ESCRIPTION NTSC/PAL TRIPLE ENCODER DAC & FILTERS TIMING & SYNC GENERATOR XI DS/BCO V XO/FIN ...

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... CHRONTEL ESCRIPTIONS 3.1 Package Diagram D[3] 1 D[4] 2 D[5] 3 D[6] 4 DVDD 5 D[7] 6 D[8] 7 DGND 8 D[9] 9 D[10] 10 D[11 CHRONTEL CH7005 Figure 2: 44-Pin LQFP CH7005C 33 XO/FIN XO/FIN AVDD AVDD DVDD 30 DVDD RESET* 29 ADDR DGND 28 DGND VDD 25 VDD RSET 24 RSET GND 23 GND 201-0000-025 Rev. 2.9, 6/24/2004 ...

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... A 75 Ω termination resistor with short traces should be attached between Y and ground for optimum performance. In normal operating modes other than SCART and RGB bypass, this pin outputs the composite video signal. In SCART and RGB Bypass modes, this pin outputs the red signal. CH7005C 3 ...

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... Application Information section. Digital Supply Voltage These pins supply the 3.3V power to the digital section of CH7005. Digital Ground These pins provide the ground reference for the digital section of CH7005, and MUST be connected to the system ground to prevent latchup. CH7005C 201-0000-025 Rev. 2.9, 6/24/2004 ...

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... RGB 24-bit YCrCb (24-bit) Cb,Y0,Cr,Y1,(CCIR656 style) RGB 24 8-8-8 over two words - ‘C’ version RGB 24 8-8-8 over two words - ‘I’ version RGB 24 (32) CH7005C Format Reference 5-6-5 each word 5-5-5 each word 5-5-5 over two bytes 5-6-5 over two bytes 8-8-8 over three bytes 8-8,8X over two words ...

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... Y0[2] G1[4] G2[4] G3[4] Y0[1] G1[3] G2[3] G3[3] Y0[0] G1[2] G2[2] G3[2] Cb0[7] G1[1] G2[1] G3[1] Cb0[6] G1[0] G2[0] G3[0] Cb0[5] B1[4] B2[4] B3[4] Cb0[4] B1[3] B2[3] B3[3] Cb0[3] B1[2] B2[2] B3[2] Cb0[2] B1[1] B2[1] B3[1] Cb0[1] B1[0] B2[0] B3[0] Cb0[0] 1 YCrCb 16-bit S[7] Y0[7] Y1[7] Y2[7] S[6] Y0[6] Y1[6] Y2[6] S[5] Y0[5] Y1[5] Y2[5] CH7005C HP1 P1b P2a P2b 1 YCrCb (16-bit Y1[7] Y2[7] Y3[7] Y1[6] Y2[6] Y3[6] Y1[5] Y2[5] Y3[5] Y1[4] Y2[4] Y3[4] Y1[3] Y2[3] Y3[3] Y1[2] Y2[2] Y3[2] Y1[1] Y2[1] Y3[1] Y1[0] Y2[0] Y3[0] Cr0[7] Cb2[7] Cr2[7] Cr0[6] Cb2[6] Cr2[6] Cr0[5] Cb2[5] Cr2[5] Cr0[4] Cb2[4] Cr2[4] Cr0[3] Cb2[3] Cr2[3] ...

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... Cr0[6] Cb2[6] 0 Cb0[5] Cr0[5] Cb2[5] 0 Cb0[4] Cr0[4] Cb2[4] 0 Cb0[3] Cr0[3] Cb2[3] 0 Cb0[2] Cr0[2] Cb2[2] 0 Cb0[1] Cr0[1] Cb2[1] 0 Cb0[0] Cr0[0] Cb2[ SP2 P0a P0b CH7005C Y3[4] Y4[4] Y5[4] Y3[3] Y4[3] Y5[3] Y3[2] Y4[2] Y5[2] Y3[1] Y4[1] Y5[1] Y3[0] Y4[0] Y5[0] Cr2[7] Cb4[7] Cr4[7] Cr2[6] Cb4[6] Cr4[6] Cr2[5] Cb4[5] Cr4[5] Cr2[4] Cb4[4] Cr4[4] Cr2[3] Cb4[3] Cr4[3] Cr2[2] ...

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... IDF# Format Pixel# Bus Data D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Note: The AX[7:0] data is ignored RGB 5-6-5 P0b P1a P1b P0a R0[4] G1[2] R1[4] G0[2] R0[3] G1[1] R1[3] G0[1] R0[2] G1[0] R1[2] G0[0] R0[1] B1[4] R1[1] B0[4] R0[0] B1[3] R1[0] B0[3] G0[5] B1[2] G1[5] B0[2] G0[4] B1[1] G1[4] B0[1] G0[3] B1[0] G1[3] B0[0] 4 12-bit RGB (12-12) P0b P1a P1b P0a R0[7] G1[3] R1[7] G0[4] R0[6] G1[2] R1[6] G0[3] R0[5] G1[1] R1[5] G0[2] R0[4] G1[0] R1[4] B0[7] R0[3] B1[7] R1[3] B0[6] R0[2] B1[6] R1[2] B0[5] R0[1] B1[5] R1[1] B0[4] R0[0] B1[4] R1[0] B0[3] G0[7] B1[3] G1[7] G0[0] G0[6] B1[2] G1[6] B0[2] G0[5] B1[1] G1[5] B0[1] G0[4] B1[0] G1[4] B0[0] 16-bit RGB (16-8) P0a P0b G0[7] A0[7] G0[6] A0[6] G0[5] A0[5] G0[4] A0[4] G0[3] A0[3] G0[2] A0[2] G0[1] A0[1] G0[0] A0[0] B0[7] R0[7] B0[6] R0[6] B0[5] R0[5] B0[4] R0[4] B0[3] R0[3] B0[2] R0[2] B0[1] R0[1] B0[0] R0[0] CH7005C 8 RGB 5-5-5 P0b P1a P1b x G1[2] x R0[4] G1[1] R1[4] R0[3] G1[0] R1[3] R0[2] B1[4] R1[2] R0[1] B1[3] R1[1] R0[0] B1[2] R1[0] G0[4] B1[1] G1[4] G0[3] B1[0] G1[3] 5 12-bit RGB (12-12) P0b P1a P1b R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] G1[2] R1[5] R0[4] B1[7] R1[4] R0[3] B1[6] R1[3] G0[7] B1[7] G1[7] G0[6] B1[4] G1[6] G0[5] B1[3] G1[5] R0[2] G1[0] R1[2] R0[1] B1[2] R1[1] R0[0] B1[1] R1[0] G0[1] B1[0] G1[1] 2 P1a P1b G1[7] R1[7] G1[6] R1[6] G1[5] R1[5] G1[4] R1[4] G1[3] R1[3] G1[2] R1[2] G1[1] R1[1] G1[0] R1[0] B1[7] A1[7] B1[6] A1[6] B1[5] A1[5] B1[4] A1[4] B1[3] A1[3] B1[2] A1[2] B0[1] A1[1] B0[0] A1[0] 201-0000-025 Rev. 2.9, 6/24/2004 ...

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... P1b P2a 0 0 S[7] Cb2[ S[6] Cb2[ S[5] Cb2[ S[4] Cb2[ S[3] Cb2[ S[2] Cb2[ S[1] Cb2[ S[0] Cb2[ SP3 P0a P0b P0c CH7005C P2b P3a P3b Y2[7] Cr2[7] Y3[7] Y2[6] Cr2[6] Y3[6] Y2[5] Cr2[5] Y3[5] Y2[4] Cr2[4] Y3[4] Y2[3] Cr2[3] Y3[3] Y2[2] Cr2[2] Y3[2] Y2[1] Cr2[1] Y3[1] Y2[0] Cr2[0] Y3[0] P2b P3a P3b Y2[7] Cr2[7] Y3[7] Y2[6] Cr2[6] Y3[6] Y2[5] Cr2[5] Y3[5] Y2[4] ...

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... S-Video outputs, which are converted by the three 9-bit DACs into analog outputs. In order to minimize the hazard of ESD, a set of protection diodes MUST BE used for each DAC connecting to TV (Refer to AN-38 for details RGB 8-bit P0b P0c P1a P1b G0[7] R0[7] B1[7] G1[7] G0[6] R0[6] B1[6] G1[6] G0[5] R0[5] B1[5] G1[5] G0[4] R0[4] B1[4] G1[4] G0[3] R0[3] B1[3] G1[3] G0[2] R0[2] B1[2] G1[2] G0[1] R0[1] B1[1] G1[1] G0[0] R0[0] B1[0] G1[0] CH7005C P1c P2a P2b P2c R1[7] B2[7] G2[7] R2(7) R1[6] B2[6] G2[6] R2(6) R1[5] B2[5] G2[5] R2(5) R1[4] B2[4] G2[4] R2(4) R1[3] B2[3] G2[3] R2(3) R1[2] B2[2] G2[2] R2(2) R1[1] B2[1] G2[1] R2(1) R1[0] B2[0] G2[0] R2(0) 201-0000-025 Rev. 2.9, 6/24/2004 ...

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... CH7005C Pixel Horizontal Vertical Clock Total Total 24.671 784 525 28.196 784 600 30.210 800 630 39.273 1040 630 43.636 1040 700 47.832 1064 750 21.147 840 420 26.434 840 525 30 ...

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... Power is shut off to the unused DACs associated with S-Video outputs. In Composite-off state, power is shut off to the unused DAC associated with CVBS output. In this power-down state, all but the serial port interface circuits are disabled. This places the CH7005 in its lowest power consumption mode. CH7005C 201-0000-025 Rev. 2.9, 6/24/2004 ...

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... The composite luminance and chrominance frequency response is depicted in Figures 7 through 9. 201-0000-025 Rev. 2.9, 6/24/2004 TM , Inc. and the customer. Luminance Bandwidth with Sin(X) /X (MHz) CVBS S-Video YCV YSV[1:0], YPEAK = 0.95 2.26 3.37 2.26 1.18 2.82 4.21 2.82 0.81 1.93 2.87 1.93 0.99 2.36 3.52 2.36 1.27 3.03 4.51 3.03 1.57 3.75 5.59 3.75 1.07 2.56 3.81 2.56 1.33 3.17 4.72 3.17 1.13 2.69 4.01 2.69 1.42 3.39 5.05 3.39 0.95 2.28 3.39 2.28 1.19 2.84 4.24 2.84 1.36 3.25 4.84 3.25 0.95 2.26 3.37 2.26 1.18 2.82 4.21 2.82 1.42 3.39 5.05 3.39 0.98 2.35 3.50 2.35 1.13 2.70 4.02 2.70 1.21 2.89 4.31 2.89 1.18 2.82 4.20 2.82 1.44 3.44 5.13 3.44 1.56 3.73 5.56 3.73 1.18 2.82 4.20 2.82 1.31 3.13 4.66 3.13 1.44 3.43 5.11 3.43 1.08 2.58 3.85 2.58 1.08 2.58 3.85 2.58 0.71 1.70 2.53 1.70 0.57 1.37 2.04 1.37 CH7005C S-Video YSV[1:0], YPEAK = 3.37 5.23 2.57 4.44 4.21 6.53 3.21 5.56 2.87 4.46 2.19 3.79 3.52 5.46 2.68 4.64 4.51 7.00 3.44 5.95 5.59 8.68 4.27 7.38 3.81 5.92 2.91 5.04 4.72 7.33 3.60 6.23 4.01 6.22 3.06 5.29 5.05 7.84 3.85 6.67 3.39 5.26 2.59 4.48 4.24 6.58 3.23 5.59 4.84 7.52 3.70 6.39 3.37 5.23 2.57 4.44 4.21 6.53 3.21 5.56 5.05 7.84 3.85 6.67 3.50 5.43 2.67 4.62 4.02 6.24 3.07 5.30 4.31 6.68 3.29 5.68 4.20 6.53 3.21 5.55 5.13 7.97 3.92 6.77 5.56 8.63 4.24 7.34 4.20 6.52 3.20 5.54 4.66 7.24 3.56 6.16 5.11 7.94 3.90 6.75 3.85 5.97 2.94 5.08 3.85 5.97 2.94 5.08 2.53 3.92 1.93 3.34 2.04 3.17 1.56 2.69 1X 5.23 6.53 4.46 5.46 7.00 8.68 5.92 7.33 6.22 7.84 5.26 6.58 7.52 5.23 6.53 7.84 5.43 6.24 6.68 6.53 7.97 8.63 6.52 7.24 7.94 5.97 5.97 3.92 3.17 13 ...

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... Figure 7: Composite Luminance Frequency Response (YCV = -12 -18 <i> (YSVdB ) n -24 -30 -36 - Figure 8: S-Video Luminance Frequency Response (YSV = 1X, YPEAK = n n CH7005C 201-0000-025 Rev. 2.9, 6/24/2004 ...

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... CHRONTEL 0 -6 -12 -18 <i> (UVfirdB ) n -24 -30 -36 - Figure 9: Chrominance Frequency Response 201-0000-025 Rev. 2.9, 6/24/2004 n CH7005C ...

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... Active video and black ( times vary greatly due to different scaling ratios used in different modes. 4. Black times (F and H) vary with position controls. 16 Level (mV) NTSC PAL 1.49 - 1.51 287 300 4. 0.59 - 0.61 287 300 2.50 - 2.53 287 300 1.55 - 1.61 287 300 0.00 - 7.50 340 300 37.66 - 52.67 340 300 0.00 - 7.50 340 300 201-0000-025 Rev. 2.9, 6/24/2004 CH7005C Duration (uS) NTSC PAL 1.48 - 1.51 4.69 - 4.71 0.88 - 0.92 2.24 - 2.26 2.62 - 2.71 0.00 - 8.67 34.68 - 52.01 0.00 - 8.67 ...

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... CH7005C 271 272 273 274 275 268 268 269 269 270 270 271 271 ...

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... FIE LD 4 FIE LD 4 312 313 314 315 316 317 312 313 314 315 316 317 4 3 ° ° ° ° ° ° CH7005C 318 318 319 319 320 320 321 321 322 322 323 323 6 ...

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... Green 18.98 Magenta 15.62 Red 13.49 Blue 10.14 Blank/ Black 8.00 Sync 0.00 Figure 14: PAL Y (Luminance) Video Output Waveform (DACG = 1) 201-0000-025 Rev. 2.9, 6/24/2004 Color bars: V 1.000 0.925 0.801 0.726 0.608 0.533 0.415 0.340 0.287 0.000 Color bars: V 1.003 0.923 0.792 0.712 0.586 0.506 0.380 0.300 0.000 CH7005C 19 ...

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... Peak Burst 19.21 0.720 Blank 15.24 0.572 Peak Burst 11.28 0.423 Yellow/Blue 6.56 0.246 Green/Magenta 3.81 0.143 Cyan/Red 2.97 0.111 Figure 16: PAL C (Chrominance) Video Output Waveform (DACG = 1) 20 Color bars: 3.579545 MHz Color Burst (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7005C 201-0000-025 Rev. 2.9, 6/24/2004 ...

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... Color/Level V Peak Chrome 33.31 1.249 White 26.75 1.003 Peak Burst 11.97 0.449 Blank/Black 8.00 0.300 Peak Burst 4.04 0.151 Sync 0.00 0.000 Figure 18: Composite PAL Video Output Waveform (DACG = 1) 201-0000-025 Rev. 2.9, 6/24/2004 Color bars: 3.579545 MHz Color Burst (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7005C 21 ...

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... Controls for the PLL and memory sections 21H 5 Control of CIV value 22H - 8 each Readable register containing the calculated 24H subcarrier increment value 25H 8 Device version number 26H - 30 Reserved for test (details not included herein) 29H 3FH 6 Current register being addressed CH7005C Functional Summary 201-0000-025 Rev. 2.9, 6/24/2004 ...

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... CIV4 CIV3 VID5 VID4 VID3 TS1 TS0 RSA MS2 MS1 MSO YLM5 YLM4 YLM3 CLM5 CLM4 CLM3 AR5 AR4 AR3 CH7005C Bit 2 Bit 1 Bit 0 SR2 SR1 SR0 FY0 FT1 FT0 YSV1 YSV0 YCV IDF2 IDF1 IDF0 XCM0 PCM1 PCM0 SAV2 SAV1 ...

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... CH7005C Address: 00H Bits SR2 SR1 SR0 R/W R/W R Output Pixel Clock Format Scaling (MHz) PAL 5/4 21.000000 ...

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... Settings for Chroma Channel 00 Minimal Flicker Filtering 01 Slight Flicker Filtering 10 Maximum Flicker Filtering 11 Enable Chroma DotCrawl Reduction 201-0000-025 Rev. 2.9, 6/24/2004 01 10 NTSC PAL FC1 FC0 FY1 R/W R/W R CH7005C 11 NTSC-J Symbol: FFR Address: 01H Bits FY0 FT1 FT0 R/W R/W R ...

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... Bit DACG Symbol: R/W Type: 0 Default CBW1 CBW0 YPEAK R/W R/W R RGBBP IDF3 R/W R CH7005C Symbol: VBW Address: 03H Bits YSV1 YSV0 YCV R/W R/W R Symbol: IDF Address: 04H Bits IDF2 IDF1 IDF0 R/W R/W R 201-0000-025 Rev. 2.9, 6/24/2004 ...

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... CH7005C μ A, Symbol: CM Address: 06H Bits XCM0 PCM1 PCM0 R/W R/W R ...

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... SAV8 (bit 2) is the MSB of the start of active video value (see explanation under “Start Active Video Register”). SAV5 SAV4 SAV3 R/W R/W R CH7005C Symbol: SAV Address: 07H Bits SAV2 SAV1 SAV0 R/W R/W R Symbol: PO Address: 08H ...

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... BL4 BL3 R/W R/W R HP5 HP4 HP3 R/W R/W R VP5 VP4 VP3 R/W R/W R CH7005C Symbol: BLR Address: 09H Bits BL2 BL1 BL0 R/W R/W R Symbol: HPR Address: 0AH Bits HP2 HP1 HP0 R/W R/W R Symbol: VPR Address: 0BH ...

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... VCO divided output when the DS/BCO pin is selected output). S-Video DACs are powered down All circuits and pins are active. All circuitry is powered down, except serial port interface circuit. CH7005C Symbol: SPR Address: 0DH Bits ...

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... From this point on, the video signal is pulled towards the white direction, with the effect increasing with increasing settings of CE[2:0]. 201-0000-025 Rev. 2.9, 6/24/2004 1.235V). If the measured voltage is below this threshold threshold CH7005C Symbol: CDR Address: 10H Bits CVBST SENSE ...

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... Normal Contrast = (17/16)*(Y -0) out in = (9/8)*(Y -0) out in = (5/4)*(Y -0) out in = (3/2)*(Y -0) = Enhances White out 128 160 192 Reserved Reserved R/W R CH7005C 224 256 Symbol: MNE Address: 13H Bits R/W R/W R 201-0000-025 Rev. 2.9, 6/24/2004 ...

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... NTSC, 5 800X600, NTSC, 3:4 108 3 24 800X600, NTSC, 7: 720X576, PAL, 1 720X480, NTSC, 1 800X500, PAL, 1:1 190 13 28 640X400, NTSC, 1 CH7005C Symbol: PLLM Address: 14H Bits R/W R/W R Symbol: PLLN Address: 15H Bits R/W R/W R/W ...

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... TV horizontal sync (for test use only) 111 TV vertical sync (for test use only) Table 27. K3 Selection SHF[2:0] K3 000 2.5 010 3.5 011 4 100 4.5 101 5 110 6 111 SHF2 SHF1 SHF0 R/W R/W R CH7005C Symbol: BCO Address: 17H Bits SCO2 SCO1 SCO0 R/W R/W R 201-0000-025 Rev. 2.9, 6/24/2004 ...

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... R/W NTSC “No Dot Crawl” 763,366,524 623,156,346 574,432,187 463,964,459 646,236,211 516,988,968 452,365,347 623,156,346 545,261,803 508,911,016 521,960,016 469,764,015 428,556,645 569,410,927 1,073,746,319 CH7005C Symbol: FSCI Address: 18H - 1FH Bits each FSCI# FSCI# FSCI# R/W R/W R/W PAL-M “Normal Dot Crawl 762,524,467 622,468,953 573,798,541 463,452,668 ...

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... P-OUTP FSCI19 R/W R DSEN FSCI15 R/W R CH7005C Symbol: Address: 1BH Bits FSCI18 FSCI17 FSCI16 R/W R/W R Symbol: Address: 1CH Bits FSCI14 FSCI13 FSCI12 R/W R/W R ...

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... PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs. Mode is shown below PLLCPI PLLCHI controls the charge pump current of the PLL. The default value should be used. 201-0000-025 Rev. 2.9, 6/24/2004 PLLCPI PLLCAP PLLS R/W R/W R CH7005C Symbol: PLLC Address: 20H Bits PLL5VD PLL5VA MEM5V R/W R/W R ...

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... See descriptions in the next section. 38 PLLCAP Value CIV25 CIV24 CH7005C Symbol: CIVC Address: 21H Bits CIVH1 CIVH0 ACIV R/W R/W R 201-0000-025 Rev. 2.9, 6/24/2004 ...

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... VID5 VID4 VID3 AR5 AR4 AR3 R/W R/W R CH7005C Symbol: CIV Address: 22H - 24H Bits CIV# CIV# CIV Symbol: VID Address: 25H Bits VID2 VID1 VID0 ...

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... S-Video & composite outputs) DVDD (3.3V) current RSET = 360 Ω, VREF = 1.235V, and NTSC CCIR601 operation. 40 Min - 0.5 1 GND - 0 Min 4.75 4.75 3 Min Typ 9 9 33.89 105 40 CH7005C Typ Max Units 7.0 V DVDD + V 0.5 Indefinite Sec °C 125 °C 150 °C 150 °C 260 °C 245 °C 225 ...

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... CHRONTEL Table 34. CH7005C Supply Current Characteristics Description Normal Operation IDD1 IDD2 IDD3 Normal Operation S-Video only IDD1 IDD2 IDD3 Normal Operation, composite only IDD1 IDD2 IDD3 Partial Power Down IDD1 IDD2 IDD3 Full Power Down IDD1 IDD2 IDD3 Notes The above data is typical with the following supply voltages: DVDD=3 ...

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... Pixel Clock High Time PH3 tdc3 Pixel Clock Duty Cycle (t 42 Test Condition IOL = 3.2 mA IOL = - 400 μA IOL = 3.2 mA Min PH1 PH2 PH3 P3 CH7005C Min Typ Max Unit 0.4 V 3.4 DVDD+0.5 V GND-0.5 1.4 V 2.5 DVDD+0.5 V GND-0.5 0.8 V 2.8 V 0.2 V Typ Max Unit ...

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... Low Voltage Notes: - refers to all digital pixel and clock inputs V DATA V - refers to pixel data output time - Graphics. P-OUT 201-0000-025 Rev. 2.9, 6/24/2004 Test Condition Min IOL = 2.0 mA 2.7 GND-0.5 Vref+0.25 GND-0.5 IOL = - 400 μA 2.8 IOL = 3 CH7005C Typ Max Unit 0.4 V DVDD + 0.5 V 1.4 V DVDD+0.5 V Vref-0. 0 ...

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... Hold time: t4 Differential Clock: (XCLK = XCLK*) to (D[11:0 & VREF) Single-ended Clock: (XCLK =VREF) to (D[11:0 & VREF) t5 D[11:0 & DS rise/fall time w/15pF load PIXELS 1 VGA Line t5 DVDD2 - 0.2 CH7005C t4 t3 P0a P0b P1a P1b P2a P2b t5 t3 Min Typ Max Unit 1 ...

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... Differential Clock: (XCLK = XCLK*) to (D[11:0 & VREF) Single-ended Clock: (XCLK =VREF) to (D[11:0 & VREF) t5 D[11:0 & DS rise/fall time w/15pF load 201-0000-025 Rev. 2.9, 6/24/2004 PIXELS 1 VGA Line t5 DVDD2 - 0.2 CH7005C P0a P0b P1a P1b P2a P2b t5 t3 Min Typ ...

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... Differential Clock: (XCLK = XCLK*) to (D[11:0 & VREF) Single-ended Clock: (XCLK =VREF) to (D[11:0 & VREF) t5 D[11:0 & DS rise/fall time w/15pF load Hold time: t6 P-OUT to HSYNC, VSYNC delay t7 (P-OUT=VREF) to (XCLK =XCLK*) delay PIXELS 1 VGA Line CH7005C P0a P0b P1a P1b P2a t3 Min Typ Max 1.7 3.6 DVDD2 - 0 ...

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... Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. Dimension B does not include allowable mold protrusions up to 0.25 mm per side. 201-0000-025 Rev. 2.9, 6/24/2004 SYMBOL 0.30 1.35 0.05 0.80 0.40 1.45 0.15 0.012 0.0531 0.00197 0.031 0.016 0.0571 0.0059 CH7005C LEAD E .004 0.50 0° 1.016 0.75 0.17 7° 0.0197 0° 0.040 0.0295 0.0067 7° 47 ...

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... CH7005C-T CH7005C-T-TR CH7005C-TF CH7005C-TF-TR ©2004 Chrontel, Inc. All Rights Reserved. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death ...