TQ8106 TriQuint Semiconductor, TQ8106 Datasheet

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TQ8106

Manufacturer Part Number
TQ8106
Description
Manufacturer
TriQuint Semiconductor
Datasheet

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The TQ8105/TQ8106 are SONET/SDH transceivers that integrate
multiplexing, demultiplexing, SONET/SDH framing, clock-synthesis PLL, and
enhanced line and clock diagnostic functions into a single monolithic device.
The TQ8106 is a pin-compatible upgrade of the TQ8105 that includes a
Clock and Data Recovery (CDR) function. The TQ8105 and TQ8106 allow
maximum flexibility in the selection of internal/external Clock and Data
Recovery, Opto-Electronic (O/E) Module, and Reference Clock Sources.
On-chip PLLs use external RC-based loop filters to allow custom tailoring of
loop response and support the wide range of reference clock frequencies
found in SONET/SDH/ATM systems. For transmit clock synthesis or for CDR,
the PLLs exceed ANSI, Bellcore, and ITU jitter specifications for systems
when combined with industry-typical O/E devices such as Sumitomo, AT&T,
HP, and AMP. The TQ8105/TQ8106 PLLs provide byte clocks and constant-
rate 38.88 MHz and 51.84 MHz, synthesized clock outputs, providing
clocking for UTOPIA and other system busses. Transmit data may also be
clocked into the devices with respect to the reference clock.
Operating from a single +5V supply, the TQ8105/TQ8106 provides fully
compliant functionality and performance, utilizing direct-connected PECL
levels (differential or single-ended) for high-speed I/O. As compared to AC-
coupled schemes, the direct-coupled connections reduce jitter and
switching-level offsets due to data patterns. The TQ8105/TQ8106 can also
provide direct connection to high-speed I/O utilizing ECL levels with a –5V
supply. Low-speed bus, control, and clock I/O utilize TTL levels. (An ECL/
PECL reference clock input is also provided; at 155.52 MHz the input should
be only PECL/ECL.) Output TTL pins can be tristated and may also be
configured for V
T
SONET/SDH
SONET/SDH
Processor
Overhead
Processor
Overhead
R
Reference
Clock
OH
I
with a 3.3V supply connection.
Q
U
For additional information and latest specifications, see our website: www.triquint.com
I
SONET/SDH
SONET/SDH
Transceiver
Transceiver
with CDR
TQ8105
TQ8106
TQ8106
or
N
T
S E M I C O N D U C T O R , I N C .
Rx O/E
Tx O/E
Rx O/E
Tx O/E
CDR
with
TQ8105/8106
SONET/SDH
Transceivers
Features
PRELIMINARY DATA SHEET
• Single-chip, byte-wide Mux,
• TQ8106 includes monolithic
• SONET/SDH/ATM compliant for
• 155.52, 77.76, 51.84, 38.88, or
• 38.88 MHz and 51.84 MHz clock
• External RC-based loop filters
• Integrated loopbacks with
• Direct-coupled standard, PECL,
• Clean TTL interface to
• 100-pin 14x14 mm JEDEC
• +5V-only supply for PECL I/O
• –40 to +125 C case operating
Demux, Framer, and Tx clock-
synthesis PLL with enhanced
diagnostics
Clock and Data Recovery
STS-12/STM-4 (622 Mb/s) or
STS-3/STM-1 (155 Mb/s) rates
19.44 MHz reference clock inputs
with TTL, PECL, or ECL level
outputs for UTOPIA as well as
byte clock rate (77.76 or 19.44 MHz)
enhanced line and reference
clock diagnostics
high-speed I/O with ECL option
PMC-Sierra devices
plastic package
(–5.2V required for ECL I/O option)
temperature
1

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TQ8106 Summary of contents

Page 1

... SONET/SDH framing, clock-synthesis PLL, and enhanced line and clock diagnostic functions into a single monolithic device. The TQ8106 is a pin-compatible upgrade of the TQ8105 that includes a Clock and Data Recovery (CDR) function. The TQ8105 and TQ8106 allow maximum flexibility in the selection of internal/external Clock and Data Recovery, Opto-Electronic (O/E) Module, and Reference Clock Sources ...

Page 2

... JEDEC, metric, plastic package, the low-power dissipation of the device, and the wide case- temperature range permits operation without a heat sink in most designs. The TQ8106 uses the same pinout as the TQ8105 and is compatible with it. The TQ8105/TQ8106 provides comprehensive, integrated, loopback functionality and enhanced line and reference clock diagnostics required of SONET/ SDH systems, minimizing additional external circuitry ...

Page 3

... Figure 2. TQ8106 Block Diagram 3 CKSRC(2:0) Clock TxBC B Phase Synthesizer PH(1:0) Clock/8 Clock Parallel 8 MXD(7:0) To Data Serial 2 LBM(1:0) Clock Serial Hold 8 11 DXD(7:0) To Data Register Parallel NOE NRESET RxBC Framer FRPWR LOS LOS Detect CLRLOS For additional information and latest specifications, see our website: www.triquint.com ...

Page 4

... RXDP ECL/PECL Input Note: *TQ8106-specific signal 4 For additional information and latest specifications, see our website: www.triquint.com Note: *TQ8106-specific signal Description ECL/PECL section power Do not connect ECL/PECL Positive Supply (see Table 6B) ECL/PECL Driver Return (see Table 6B) Tx Ref. Clock or Bypass Clock, Complement Tx Ref ...

Page 5

... Demultiplexer Data Bit 6 TTL Driver Ground Demultiplexer Data Bit 7 (MSB) Output Driver Internal Positive Supply Core Positive Supply GND for TQ8106 to powerup CDR (ignored by TQ8105) Core Ground Framer Power Control (power on when high) Out-of-Frame: Initiates Frame Search/Bit Alignment TTL Driver Positive Supply Loss of Signal (high when > ...

Page 6

... REFCKT TTL Input 99 GND GND 100 NC/NCDREN* TTL Input Note:*TQ8106-specific signal 6 For additional information and latest specifications, see our website: www.triquint.com Description Active-high Clear LOS output Receive Clock meets lock criteria when high Loopback Mode Control (see Table 3) Core Ground ...

Page 7

... Clock Source Mode 011 (see Table 3). Framer The TQ8105 and TQ8106 provide a clean interface to devices from PMC-Sierra and others. The Out-of-Frame (OOF) input is a state (level)-initiated event, rather than the edge-triggered event found on TriQuint’s first- generation TQ8101 transceiver ...

Page 8

... The LOR (Loss Of Reference) output goes high when the reference clock is absent. Note that this signal is not latched and is only high when the reference clock is missing. A reference clock is required for the TQ8106 CDR to function correctly. The NSOL (Loss-of-signal input, active low, PECL/ECL level) input allows the receiver to force zeroes onto the demux outputs ...

Page 9

... These design notes are provided to assist the circuit designer in achieving the highest possible performance while reducing design time. Unless noted otherwise, references to the TQ8105 apply equally to the TQ8106. Interfacing to PMC-Sierra Devices The transmit timing of the TQ8105 is such that the PMC-Sierra byte outputs (POUT(0:7)) may be directly connected to the TQ8105 mux inputs (MXD(0:7)) ...

Page 10

... TQ8105/TQ8106 PRELIMINARY DATA SHEET Figure 4. Reference Design Schematic 10 For additional information and latest specifications, see our website: www.triquint.com ...

Page 11

... Table 2A. TQ8105/TQ8106 Recommended Transmit Loop Filter Values (Preliminary) Reference Frequency Divide (MHz) Ratio 19.44 32 38.88 16 51.84 12 77.76 8 155.52* 4 Note: *Internal divide by two on Reference Table 2B. TQ8106 Recommended CDR Loop Filter Values (Preliminary) Incoming Resistor Capacitor NRZ Data Rate Value R2 Value C3 (Mbs) (ohms 155.52 470 1 ...

Page 12

... NSOL 1 = Pass receive data Force receive data to 0 OC3 1 = Operate at STM1/STS-3 (or PLL bypass divided by 4 Operate at STM4/STS-12/PLL bypass NRESET 1 = Normal operation Reset internal counters NCDREN 1 = TQ8105/CDR Off mode Enable CDR (TQ8106 only) Table 4. Absolute Maximum Ratings Parameter Symbol Positive supply V V ...

Page 13

... Power dissipation, Framer on, TQ8106 CDR off DF P Power dissipation, Framer off, TQ8106 CDR off D P Power dissipation, Framer on, TQ8106 CDR on Table 6A. Recommended Operating Conditions Parameter Positive supply Output driver positive supply Negative supply (ECL mode only) Operating case temperature (see Figure 9) Table 6B ...

Page 14

... TQ8105/TQ8106 PRELIMINARY DATA SHEET Table 7. DC Characteristics—ECL/PECL I/O (Specifications apply over recommended operating ranges). Parameter Condition Internal ECL reference Single-ended inputs Common mode voltage Differential inputs Differential voltage Differential inputs Input HIGH voltage V = 1300 mV REF Input LOW voltage Output HIGH voltage ...

Page 15

... TXCK falling edge to TXD (see Figure 7) Notes 0.8V/2.0V levels 2. With PH(1:0) set to 00, 18pF total loading 3. TTL outputs test load (V = +5V): CC 330 220 For additional information and latest specifications, see our website: www.triquint.com TQ8105/TQ8106 PRELIMINARY DATA SHEET Symbol Minimum Nominal T 1.6 — C(RXCK) T 1.6 — ...

Page 16

... TQ8105/TQ8106 PRELIMINARY DATA SHEET Figure 6. Input Timing RXCKP RXD TXBC MXD(7:0) Figure 7. Output Timing TXCK TXD RXBC DXD(7:0) DXSYNC 16 For additional information and latest specifications, see our website: www.triquint.com T T S(RXD) H(RXD S(MXD) H(MXD) T P(TXD) T P(DXD) T P(DXSYNC) ...

Page 17

... For additional information and latest specifications, see our website: www.triquint.com TQ8105/TQ8106 PRELIMINARY DATA SHEET RXBC Resync 200 300 400 500 Required airflow (LFPM) T (DXSYNCPW) TQ8105 TQ8106 600 17 ...

Page 18

... TQ8105/TQ8106 PRELIMINARY DATA SHEET Figure 10. Mechanical Package (100 pins mm) 1 Package Package “P” Package “S” 2 Dimension Value Value A 2.35 1.7 max A 0.25 max 0. 2.00 1. 17.20 0.25 16.00 0.4 D 14.00 14. 17.20 0.25 16.00 0.4 E 14.00 14. 0.88 +0.15/–0.10 0.50 0.20 b 0.22 0.18 e 0.50 0.50 N 100 pins 100 pins Notes: 1. Not recommended for new designs. 2. All dimensions in millimeters (mm). ...

Page 19

... TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright © 1998 TriQuint Semiconductor, Inc. All rights reserved. Revision 0.3.A For additional information and latest specifications, see our website: www.triquint.com TQ8105/TQ8106 PRELIMINARY DATA SHEET • User’s Manual / Product Specification • PCB Artwork (all layers) • ...

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