HYB18TC512160BF-3S Qimonda, HYB18TC512160BF-3S Datasheet
HYB18TC512160BF-3S
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HYB18TC512160BF-3S Summary of contents
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... Adapted internet edition 39 Modified AC Timing Parameters Previous Revision: 2006-06, Rev.1.1 For product types : HYB18TC512160BF-2.5, HYB18TC512800BF-2.5, HYB18TC512160BF-3, HYB18TC512800BF-3, HYB18TC512160BF-3S, HYB18TC512800BF-3S, HYB18TC512160BF-3.7, HYB18TC512800BF-3.7, HYB18TC512160BF-5, HYB18TC512800BF-5 Previous Revision: 2005-11, Rev. 1.04 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document ...
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Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics. 1.1 Features The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: ± ± • 1.8 V 0.1 V Power Supply 1.8 ...
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Product Type Speed Code Speed Grade Max. Clock Frequency Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time Product Type Speed Code Speed Grade f Max. Clock Frequency @CL5 CK5 f @CL4 CK4 f @CL3 ...
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Product Type Speed Code Speed Grade Max. Clock Frequency Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time Rev. 1.11, 2006-09 03292006-HDLH-OAY6 512-Mbit Double-Data-Rate-Two SDRAM –5 DDR2–400B 3–3–3 f @CL5 200 CK5 f @CL4 200 ...
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... Inputs are Product Type Org Speed ×16 HYB18TC512160BF-2.5 DDR2-800E ×8 HYB18TC512800BF-2.5 DDR2-800E ×16 HYB18TC512160BF-3 DDR2-667C ×8 HYB18TC512800BF-3 DDR2-667C ×16 HYB18TC512160BF-3S DDR2-667D ×8 HYB18TC512800BF-3S DDR2-667D ×16 HYB18TC512160BF-3.7 DDR2-533C ×8 HYB18TC512800BF-3.7 DDR2-533C ×16 HYB18TC512160BF-5 DDR2-400B ×8 HYB18TC512800BF-5 DDR2-400B ...
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Pin Configuration This chapter contains the pin configuration tables. 2.1 CPin Configuration for TFBGA–60 TFBGA–84 The pin configuration of a DDR2 SDRAM is listed by function in columns are explained in Table 7 and Table 8 for ×4, for ...
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Ball#/Pin# Name Pin Type A10 ...
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Ball#/Pin# Name Pin Type Data Signals ×8 Organization C8 DQ0 I/O C2 DQ1 I/O D7 DQ2 I/O D3 DQ3 I/O D1 DQ4 I/O D9 DQ5 I/O B1 DQ6 I/O B9 DQ7 I/O Data Signals ×16 Organization G8 DQ0 I/O G2 ...
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Ball#/Pin# Name Pin Type Data Strobe ×16 Organization B7 UDQS I/O A8 UDQS I/O F7 LDQS I/O E8 LDQS I/O Data Mask ×8 Organization Data Mask ×16 Organization B3 UDM I F3 LDM I Power Supplies ×8 ...
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Ball#/Pin# Name Pin Type Not Connected ×4 Organization A2, B1, B9, D1 D9,G1, L3,L7, L8 Not Connected ×8 Organization G1, L3,L7 Not Connected ×16 Organization A2, E2, L1, R3 R7, R8 Other Pins ...
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Notes and are power and ground for the DLL. DDL SSDL V V connected to on the device and are isolated on the device. SSQ Rev. 1.11, 2006-09 03292006-HDLH-OAY6 512-Mbit Double-Data-Rate-Two SDRAM Pin Configuration ...
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Notes 1. RDQS / RDQS are enabled by EMRS(1) command RDQS / RDQS is enabled, the DM function is disabled 3. When enabled, RDQS & RDQS are used as strobe signals during reads. Rev. 1.11, 2006-09 03292006-HDLH-OAY6 HYB18TC512[16/80]0BF ...
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Notes 1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0] Rev. 1.11, 2006-09 03292006-HDLH-OAY6 HYB18TC512[16/80]0BF 512-Mbit Double-Data-Rate-Two SDRAM Pin Configuration for ×16 components, PG-TFBGA-84-8 2. LDM is the data mask signal for DQ[7:0], UDM is the ...
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Mbit DDR2 Addressing This chapter contents the table for the 512 Mbit DDR2 Addressing. Configuration Bank Address Number of Banks Auto-Precharge Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes] 1) Referred ...
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Functional Description This chapter describes the Functional Description. 1) Field Bits Type Description BA2 16 reg. addr. Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components 0 B BA1 15 Bank Address [1] 0 ...
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Field Bits Type Description CL [6:4] w CAS Latency Note: All other bit combinations are illegal. 011 B 100 B 101 B 110 B 111 Burst Type [2:0] w Burst ...
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Field Bits Type Description BA2 16 reg. addr. Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components 0 B BA1 15 Bank Address [ BA0 14 Bank Address [ A13 ...
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Field Bits Type Description AL [5:3] Additive Latency Note: All other bit combinations are illegal. 000 B 001 B 010 B 011 B 100 B R 6,2 Nominal Termination Resistance of ODT TT Note: See ...
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EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010 1) Field Bits Type Description BA2 16 w Bank Address[2] Note: BA2 is not available on 256Mbit and 512Mbit components 0 BA2 Bank Address B BA [15:14] w Bank Adress[15:14 MRS ...
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EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010 1) Field Bits Type Description BA2 16 reg.addr Bank Address[2] Note: BA2 is not available on 256Mbit and 512Mbit components 0 BA2 Bank Address B BA1 15 Bank Adress[1] 1 BA1 Bank Address ...
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Burst Length Starting Address (A2 A1 A0) × × ×1 0 × ...
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Truth Tables The truth tables in this chapter summarize the commands and there signal coding to control a standard Double-Data-Rate-Two SDRAM. 1) Current State CKE 6) Previous Cycle (N-1) Power-Down L L Self Refresh L L Bank(s) Active H ...
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Function CKE Previous Cycle (Extended) Mode H Register Set Auto-Refresh H Self-Refresh Entry H Self-Refresh Exit L Single Bank Precharge H Precharge all Banks H Bank Activate H Write H Write with Auto- H Precharge Read H Read with Auto- ...
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Electrical Characteristics This chapter lists the electrical characteristics. 5.1 Absolute Maximum Ratings This chapter contains the absolute maximum ratings table. Symbol Parameter V V Voltage on pin relative Voltage on pin relative to DDQ ...
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DC Characteristics This chapter describes the DC characteristics. Symbol Parameter V Supply Voltage DD V Supply Voltage for DLL DDDL V Supply Voltage for Output DDQ V Input Reference Voltage REF V Termination Voltage ...
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DC & AC Characteristics DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The ...
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Symbol Parameter V DC input signal voltage IN(dc differential input voltage ID(dc differential input voltage ID(ac differential cross point input voltage IX(ac differential cross point output voltage 0.5 × OX(ac ...
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Output Buffer Characteristics This chapter describes the Output Buffer Characteristics. Symbol Parameter I Output Minimum Source DC Current OH I Output Minimum Sink DC Current 1 1. – ...
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Symbol Description — Output Impedance — Pull-up / Pull down mismatch — Output Impedance step size for OCD calibration S Output Slew Rate OUT V ± V ± 1 1.8 V 0.1 V DDQ ...
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Overshoot and Undershoot Specification This chapter describes the Overshoot and Undershoot Specification. AC Overshoot / Undershoot Specification for Address and Control Pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area V Maximum ...
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AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area V Maximum overshoot area above DDQ V Maximum undershoot area below SSQ AC ...
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Specifications and Conditions This chapter describes the Specifications and Conditions. Parameter Operating Current - One bank Active - Precharge CK(IDD) RC RC(IDD) RAS RAS.MIN(IDD) and control inputs ...
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Parameter Self-Refresh Current CKE ≤ 0.2 V; external clock off, CK and Other control and address inputs are floating, Data bus inputs are floating. Operating Bank Interleave Read Current I 1. All banks interleaving reads, = ...
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Symbol –2.5 –3 DDR2-800E DDR2-667C DD0 100 DD1 115 105 DD2P DD2N DD2Q DD3P DD3N I ...
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Timing Characteristics This chapter contains speed grade definition, AC timing parameter and ODT tables. 7.1 Speed Grade Definitions All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications( List of Speed Grade Definition tables: • Table 38 “Speed ...
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Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time 1) Timings are guaranteed with CK/CK differential Slew ...
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V 3) Inputs are not recognized as valid until 4) The output timing reference voltage level calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to ...
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AC Timing Parameters List of Timing Parameters Tables. • Table 42 “Timing Parameter by Speed Grade - DDR2–800” on Page 39 • Table 43 “Timing Parameter by Speed Grade - DDR2–667” on Page 42 • Table 44 “Timing Parameter ...
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... Mode register set command cycle time MRS command to ODT update delay OCD drive mode output delay Minimum time clocks remain ON after CKE asynchronously drops LOW 1) For details and notes see the relevant Qimonda component data sheet 1.8 V ± 0.1V; = 1.8 V ± 0.1 V. See notes ...
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V 6) Inputs are not recognized as valid until 7) The output timing reference voltage level New units, ‘ ‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘ CK.AVG under operation. Unit ‘nCK‘ represents one ...
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When the device is operated with input clock jitter, this parameter needs to be derated by the actual deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t t ...
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Parameter DQ hold skew factor DQ/DQS output hold time from DQS Write command to DQS associated clock edges DQS latching rising transition to associated clock edges DQS input high pulse width DQS input low pulse width DQS falling edge to ...
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... Mode register set command cycle time MRS command to ODT update delay OCD drive mode output delay Minimum time clocks remain ON after CKE asynchronously drops LOW 1) For details and notes see the relevant Qimonda component data sheet 1.8 V ± 0.1V; = 1.8 V ± 0.1 V. See notes ...
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used in conjunction with t to derive the DRAM output timing QHS following equation; = MIN ( , HP ...
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T1 T2 tHZ,tRPST DQS DQS Rev. 1.11, 2006-09 03292006-HDLH-OAY6 512-Mbit Double-Data-Rate-Two SDRAM Method for calculating transitions and endpoint VOH - x mV VTT + 2x mV VOH - 2x mV VTT + x mV VOL + ...
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CK CK Rev. 1.11, 2006-09 03292006-HDLH-OAY6 512-Mbit Double-Data-Rate-Two SDRAM Differential input waveform timing - tIH tIS tIH tIS 47 Internet Data Sheet HYB18TC512[16/80]0BF FIGURE and DDQ V min IH(ac) V min IH(dc) V REF(dc) ...
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Parameter DQ output access time from CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks ...
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... Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command 1) For details and notes see the relevant Qimonda component data sheet = 1.8 V ± 0 1.8 V ±0.1 V. See notes ...
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The , and , parameters are referenced to a specific voltage level, which specify when the device output is no longer driving HZ RPST LZ RPRE begins ...
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Parameter DQ output access time from CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks ...
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... Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command 1) For details and notes see the relevant Qimonda component data sheet = 1.8 V ± 0 1.8 V ±0.1 V. See notes ...
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The , and , parameters are referenced to a specific voltage level, which specify when the device output is no longer driving HZ RPST LZ RPRE begins ...
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ODT AC Electrical Characteristics This chapter contains the ODT AC electrical characteristic tables. ODT AC Characteristics and Operating Conditions for DDR2-667 & DDR2-800 Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on ...
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Package Dimensions This chapter contains the Package Dimension tables. Rev. 1.11, 2006-09 03292006-HDLH-OAY6 HYB18TC512[16/80]0BF 512-Mbit Double-Data-Rate-Two SDRAM Package Outline PG-TFBGA-60 55 Internet Data Sheet FIGURE 11 ...
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Rev. 1.11, 2006-09 03292006-HDLH-OAY6 HYB18TC512[16/80]0BF 512-Mbit Double-Data-Rate-Two SDRAM Package Outline P-TFBGA-84 56 Internet Data Sheet FIGURE 12 ...
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... Product Nomenclature For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter. Example for Field Number 1 2 DDR2 DRAM HYB 18 Field Description 1 QIMONDA Component Prefix 2 Interface Voltage [V] 3 DRAM Technology, consumer variant 4 Component Density [Mbit] 5+6 Number of I/Os 7 Product Variations 8 Die Revision ...
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List of Figures Pin Configuration for ×4 components, PG-TFBGA-60 (top view ...
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List of Tables Table 1 Performance tables for –2 ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system ...