P-80C32 ETC, P-80C32 Datasheet

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P-80C32

Manufacturer Part Number
P-80C32
Description
Manufacturer
ETC
Datasheet

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Rev. G (14 Jan. 97)
CMOS 0 to 44 MHz Single Chip 8–bit Microntroller
Description
TEMIC’s 80C52 and 80C32 are high performance CMOS
versions of the 8052/8032 NMOS single chip 8 bit C.
The fully static design of the TEMIC 80C52/80C32
allows to reduce system power consumption by bringing
the clock frequency down to any value, even DC, without
loss of data.
The 80C52 retains all the features of the 8052 : 8 K bytes
of ROM ; 256 bytes of RAM ; 32 I/O lines ; three 16 bit
timers ; a 6-source, 2-level interrupt structure ; a full
duplex serial port ; and on-chip oscillator and clock
circuits. In addition, the 80C52 has 2 software-selectable
Features
Optional
MATRA MHS
80C32 : Romless version of the 80C52
80C32/80C52-L16 : Low power version
Vcc : 2.7 – 5.5 V
80C32/80C52-12 : 0 to 12 MHz
80C32/80C52-16 : 0 to 16 MHz
80C32/80C52-20 : 0 to 20 MHz
80C32/80C52-25 : 0 to 25 MHz
80C32/80C52-30 : 0 to 30 MHz
Power control modes
256 bytes of RAM
8 Kbytes of ROM (80C52)
32 programmable I/O lines
Three 16 bit timer/counters
64 K program memory space
64 K data memory space
Secret ROM : Encryption
Secret TAG : Identification number
Freq : 0-16 MHz
modes of reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the RAM, the timers, the serial port and the interrupt
system continue to function. In the power down mode the
RAM is saved and all other functions are inoperative.
The 80C32 is identical to the 80C52 except that it has no
on-chip ROM. TEMIC’s 80C52/80C32 are manufactured
using SCMOS process which allows them to run from 0
up to 44 MHz with Vcc = 5 V.
TEMIC’s 80C52 and 80C32 are also available at 16 MHz
with 2.7 V < V
* 0 to 70 C temperature range.
For other speed and temperature range availability please consult your
sales office.
80C32/80C52-36 : 0 to 36 MHz
80C32-40 : 0 to 40 MHz*
80C32-42 : 0 to 42 MHz*
80C32-44 : 0 to 44 MHz*
Fully static design
0.8 CMOS process
Boolean processor
6 interrupt sources
Programmable serial port
Temperature range : commercial, industrial, automotive,
military
CC
< 5.5 V.
80C32/80C52
1

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P-80C32 Summary of contents

Page 1

... RAM, the timers, the serial port and the interrupt system continue to function. In the power down mode the RAM is saved and all other functions are inoperative. The 80C32 is identical to the 80C52 except that it has no on-chip ROM. TEMIC’s 80C52/80C32 are manufactured using SCMOS process which allows them to run from MHz with Vcc = 5 V. TEMIC’ ...

Page 2

Interface Figure 1. Block Diagram 2 MATRA MHS Rev. G (14 Jan. 97) ...

Page 3

... Figure 2. Pin Configuration DIL Diagrams are for reference only. Package sizes are not to scale. MATRA MHS Rev. G (14 Jan. 97) P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3 RST RxD/P 30 80C32/80C52 NC TxD/P 31 INT0/P 32 INT1/P 33 T0/P 34 T1/P 35 Flat Pack 80C32/80C52 P0.4/A4 P0.5/A5 P0.6/A6 P0.7/A7 EA 80C32/80C52 NC ALE PSEN P2 ...

Page 4

... Supply voltage during normal, Idle, and Power Down operation. Port 0 Port bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory ...

Page 5

... GF1 GF0 PD IDL If 1’s are written to PD and IDL at the same time. PD takes, precedence. The reset value of PCON is (000X0000). Idle Mode The instruction that sets PCON.0 is the last instruction executed before the Idle mode is activated. Once in the Idle mode the CPU status is preserved in its entirety : the ...

Page 6

... It should be noted that if the power down mode is activated while in external program memory, the port data that is held in the Special Function Register P2 is restored to Port 2. If the data the port pin is held high during the power down mode by the strong pullup, T1, shown in Figure 4. ...

Page 7

... When an I/O pin on Ports used as an input, the user should be aware that the external circuit must sink current during the logical 1-to-0 transition. The maximum sink current is specified as ITL under the D ...

Page 8

... TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Timer 2 external enable flag. When set, allows capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. ...

Page 9

... This routine is implemented inside the microcontroller ROM memory in case of masked version which can be kept secret (and then the value of the Secret Tag also) by using a ROM Encryption. For further information, please refer to the application note (ANM031) available upon request. ...

Page 10

... Freq 12 MHz Icc op = 1.25 Freq (MHz Icc idle = 0.36 Freq (MHz Notice Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions –40 ...

Page 11

... MATRA MHS Rev. G (14 Jan. 97) * Notice Stresses above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and –40 to +125 functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not – ...

Page 12

... Icc idle = 0.36 Freq (MHz Notice Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only –55 to +125 and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is – ...

Page 13

... MATRA MHS Rev. G (14 Jan. 97) * Notice Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect – ...

Page 14

... Idle ICC is measured with all output pins disconnected ; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 5 V, VIH = VCC –. XTAL2 N.C ; Port 0 = VCC ; EA = RST = VSS. Power Down ICC is measured with all output pins disconnected ; EA = PORT 0 = VCC ; XTAL2 N.C. ; ...

Page 15

... TA = – Vss = 2.7 V < Vcc < 5 MHz TA = –55 + 125 C ; Vss = Vcc = MHz (Load Capacitance for PORT 0, ALE and PSEN = 100 pF ; Load Capacitance for all other outputs = 80 pF) External Program Memory Characteristics (values in ns) SYM- ...

Page 16

... Address to Valid Data IN TLLWL ALE TAVWL Address TQVWX Data valid to WR transition TQVWH Data Setup to WR transition TWHQX Data Hold after WR TRLAZ RD low to Address Float TWHLH high to ALE high External Data Memory Write Cycle External Data Memory Read Cycle ...

Page 17

... Serial Port Timing – Shift Register Mode (values in ns) SYM- PARAMETER BOL TXLXL Serial Port Clock Cycle Time TQVXH Output Data Setup to Clock Rising Edge TXHQX Output Data Hold after Clock Rising Edge TXHDX Input Data Hold after Clock Rising Edge ...

Page 18

... External Clock Drive Waveforms AC Testing Input/Output Waveforms AC inputs during testing are driven at Vcc – 0.5 for a logic “1” and 0.45 V for a logic “0”. Timing measurements are made at VIH min for a logic “1” and VIL max for a logic “0”. Float Waveforms For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs ...

Page 19

... Clock Waveforms This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (T and WR propagation delays are approximately 50 ns ...

Page 20

... Radiation Tolerant I : Industrial A : Automotive M : Military Package Type P: PDIL 40 S: PLCC 44 F1: PQFP 44 (Foot print 13.9 mm) F2: PQFP 44 (Foot print 12.3 mm) V: VQFP (1.4 mm) T: TQFP (1.0 mm) D: CDIL 40 Q: CQFP 44 R: LCC 44 C: Side Braze 40 (.6) (1) Only for 80C31 at commercial range. 20 – MHz version – ...

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