A1020B

Manufacturer Part NumberA1020B
ManufacturerActel Corporation
A1020B datasheet
 


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Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by
the Equation 1.
Power (uW) = C
* V
EQ
CC2
Where:
C
is the equivalent capacitance expressed in pF.
EQ
V
is the power supply in volts.
CC
F is the switching frequency in MHz.
Equivalent capacitance is calculated by measuring I
at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over a
range of frequencies at a fixed value of V
capacitance is frequency independent so that the results may
be used over a wide range of operating conditions. Equivalent
capacitance values are shown below.
C
Values for Actel FPGAs
EQ
A10V10B
A10V20B
Modules (C
)
EQM
Input Buffers (
)
CEQI
Output Buffers (C
)
EQO
Routed Array Clock Buffer
Loads (C
)
EQCR
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 2 shows a piece-wise linear summation
over all components.
2
Power = V
* [(m * C
* f
)
CC
EQM
m
modules
(n * C
* f
)
+ (p * (C
+ C
) * f
EQI
n
inputs
EQO
L
0.5 * (q
* C
* f
)
+
1
EQCR
q1
routed_Clk1
(r
* f
)
]
1
q1
routed_Clk1
Where:
m
= Number of logic modules switching at fm
n
= Number of input buffers switching at fn
p
= Number of output buffers switching at fp
q
= Number of clock loads on the first routed array
1
clock (All families)
r
= Fixed capacitance due to first routed array
1
clock (All families)
1-290
C
= Equivalent capacitance of logic modules in pF
EQM
C
= Equivalent capacitance of input buffers in pF
EQI
C
= Equivalent capacitance of output buffers in pF
EQO
* F
(1)
C
= Equivalent capacitance of routed array clock in
EQCR
C
= Output lead capacitance in pF
L
f
= Average logic module switching rate in MHz
m
f
= Average input buffer switching rate in MHz
n
active
f
= Average output buffer switching rate in MHz
CC
p
f
= Average first routed array clock rate in MHz (All
q1
. Equivalent
CC
Fixed Capacitance Values for Actel FPGAs
(pF)
Device Type
A1010B
A1010B
A1020B
A1020B
3.2
3.7
A10V10B
10.9
22.1
A10V20B
11.6
31.2
Determining Average Switching Frequency
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to the
4.1
4.6
circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
Logic Modules (m)
+
Inputs switching (n)
)
+
p
outputs
Outputs switching (p)
First routed array clock loads (q
(2)
Load capacitance (C
Average logic module switching rate (f
Average input switching rate (f
Average output switching rate (f
Average first routed array clock rate
(f
)
q1
pF
families)
r
1
routed_Clk1
41.4
68.6
40
65
90% of modules
#inputs/4
#outputs/4
)
40% of modules
1
)
35 pF
L
) F/10
m
)
F/5
n
)
F/10
p
F