F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 
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Page 32/154:

EXTENSION REGISTER SUMMARY

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EXTENSION REGISTER SUMMARY: 00-2F
Reg
Register Name
XRX Extension Index Register
XR00 Chip Version
XR01 Configuration
XR02 CPU Interface Control
XR03 -reserved-
(ROM Interface) --
XR04 Memory Control
XR05 -reserved-
(Clock Control) --
XR06 Color Palette Control (DRAM Intfc) 3
XR07 -reserved-
XR08 -reserved- (Gen Purp Output Select B) --
XR09 -reserved- (Gen Purp Output Select A) --
XR0A -reserved-
(Cursor Address Top) --
XR0B CPU Paging
XR0C Start Address Top
XR0D Auxiliary Offset
XR0E Text Mode Control
XR0F Software Flags 2
XR10 Single/Low Map Register
XR11 High Map Register
XR12 -reserved-
XR13 -reserved-
XR14 Emulation Mode
XR15 Write Protect
XR16 -reserved-
(Trap Enable)
XR17 -reserved-
(Trap Status)
XR18 Alternate H Disp End
XR19 Alternate H Sync Start / Half-line
XR1A Alternate H Sync End
XR1B Alternate H Total
XR1C Alternate H Blank Start / H Panel Size 8 R/W 3B7/3D7
XR1D Alternate H Blank End
XR1E Alternate Offset
XR1F Virtual EGA Switch Register
XR20 -reserved-
(453 Interface II)/(SUD) --
XR21 -reserved-
(Sliding Hold A) --
XR22 -reserved-
(Sliding Hold B) --
XR23 -reserved-
(SHC)/(WBM Ctrl) --
XR24 FP AltMaxScanline (SHD)/(WBM Patt) 5
XR25 -reserved-
XR26 -reserved-
(453 Config)
XR27 -reserved-
XR28 Video Interface
XR29 -reserved-
(Function Control)
XR2A -reserved-
(Frame Intrpt Count)
XR2B Default Video
XR2C FP Vsync (FLM) Delay (Force H High) 8
XR2D FP Hsync (LP) Delay (Force H Low) 8
XR2E -reserved-
XR2F FP Hsync (LP) Width (Force V Low) 7
Reset Codes:
x = Not changed by RESET (indeterminate on power-up)
d = Set from the corresponding data bus pin on falling edge of RESET
h = Read-only Hercules Configuration Register Readback bits
Note: Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column
Note: 450–453 VGAs drive CRTs only, 455–457 & 655x0 VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD)
Revision 0.7
Bits Access
Port
Reset
7
R/W 3B6/3D6
- x x x x x x x
8
R/O 3B7/3D7
1 0 0 1 r r r r
8
R/O 3B7/3D7
d d d d d d d d
5
R/W 3B7/3D7
0 - 0 0 0 - 0 -
--
3B7/3D7
3
R/W 3B7/3D7
- - 0 0 - 0 - -
--
3B7/3D7
R/W 3B7/3D7
0 0 0 - - - - -
--
--
3B7/3D7
--
3B7/3D7
--
3B7/3D7
--
3B7/3D7
4
R/W 3B7/3D7
- - - 0 - 0 0 0
1
R/W 3B7/3D7
- - - - - - - 0
2
R/W 3B7/3D7
- - - - - - 0 0
2
R/W 3B7/3D7
- - - - 0 0 - -
8
R/W 3B7/3D7
x x x x x x x x
8
R/W 3B7/3D7
x x x x x x x x
8
R/W 3B7/3D7
x x x x x x x x
--
--
3B7/3D7
--
--
3B7/3D7
8
R/W 3B7/3D7
0 0 0 0 h h 0 0
8
R/W 3B7/3D7
0 0 0 0 0 0 0 0
--
--
3B7/3D7
--
--
3B7/3D7
8
R/W 3B7/3D7
x x x x x x x x
8
R/W 3B7/3D7
x x x x x x x x
5
R/W 3B7/3D7
- - - x x x x x
8
R/W 3B7/3D7
x x x x x x x x
x x x x x x x x
2
R/W 3B7/3D7
- x x - - - - -
8
R/W 3B7/3D7
x x x x x x x x
5
R/W 3B7/3D7
0 - - - x x x x
--
3B7/3D7
--
3B7/3D7
--
3B7/3D7
--
3B7/3D7
R/W 3B7/3D7
- - - x x x x x
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
3
R/W 3B7/3D7
- 0 - 0 - 0 - -
--
--
3B7/3D7
--
--
3B7/3D7
8
R/W 3B7/3D7
0 0 0 0 0 0 0 0
R/W 3B7/3D7
x x x x x x x x
R/W 3B7/3D7
x x x x x x x x
--
--
3B7/3D7
R/W 3B7/3D7
x x x - x x x x
28
Register Summary
Chips' VGA Product Family
450 451 452 453 455 456 457 65520 65530
3
3
3
3
3
3
3
3
3
3
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3
3
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– = Not implemented (always reads 0)
r = Chip revision # (starting from 0000)
0/1 = Reset to 0/1 by falling edge of RESET
Preliminary 65510
3
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3
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3