F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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Page 49/154:

CRT Controller Registers

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Register
Mnemonic
Register Name
CRX
CRTC Index
CR00
Horizontal Total
CR01
Horizontal Display Enable End
CR02
Horizontal Blank Start
CR03
Horizontal Blank End
CR04
Horizontal Sync Start
CR05
Horizontal Sync End
CR06
Vertical Total
CR07
Overflow
CR08
Preset Row Scan
CR09
Maximum Scan Line
CR0A
Cursor Start Scan Line
CR0B
Cursor End Scan Line
CR0C
Start Address High
CR0D
Start Address Low
CR0E
Cursor Location High
CR0F
Cursor Location Low
CR10
Vertical Sync Start (See Note 2)
CR11
Vertical Sync End (See Note 2)
CR10
Lightpen High (See Note 2)
CR11
Lightpen Low (See Note 2)
CR12
Vertical Display Enable End
CR13
Offset
CR14
Underline Row
CR15
Vertical Blank Start
CR16
Vertical Blank End
CR17
CRT Mode Control
CR18
Line Compare
CR22
Memory Data Latches
CR24
Attribute Controller Toggle
CR3x
Clear Vertical Display Enable
Note 1:
When MDA or Hercules emulation is enabled, the CRTC I/O address should be set to 3B0h-3B7h by
setting the I/O address select bit in the Miscellaneous Output register (3C2h/3CCh bit-0) to zero. When
CGA emulation is enabled, the CRTC I/O address should be set to 3D0h-3D7h by setting Misc Output
Register bit-0 to 1.
Note 2:
In the EGA, all CRTC registers except the cursor (CR0C-CR0F) and light pen (CR10 and CR11)
registers are write-only (i.e., no read back). In both the EGA and VGA, the light pen registers are at
index locations conflicting with the vertical sync registers. This would normally prevent reads and writes
from occurring at the same index. Since the light pen registers are not normally useful, the VGA
provides software control (CR03 bit-7) of whether the vertical sync or light pen registers are readable at
indices 10-11.
Revision 0.7

CRT Controller Registers

Index
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
10h
11h
12h
13h
14h
15h
16h
17h
18h
22h
24h
3xh
45

CRT Controller Registers

I/O
Protect
Access
Address
Group
RW
3B4h/3D4h
RW
3B5h/3D5h
0
RW
3B5h/3D5h
0
RW
3B5h/3D5h
0
RW
3B5h/3D5h
0
RW
3B5h/3D5h
0
RW
3B5h/3D5h
0
RW
3B5h/3D5h
0
RW
3B5h/3D5h
0/3
RW
3B5h/3D5h
3
RW
3B5h/3D5h
2/4
RW
3B5h/3D5h
2
RW
3B5h/3D5h
2
RW
3B5h/3D5h
RW
3B5h/3D5h
RW
3B5h/3D5h
RW
3B5h/3D5h
W or RW
3B5h/3D5h
4
W or RW
3B5h/3D5h
3/4
R
3B5h/3D5h
R
3B5h/3D5h
RW
3B5h/3D5h
4
RW
3B5h/3D5h
3
RW
3B5h/3D5h
3
RW
3B5h/3D5h
4
RW
3B5h/3D5h
4
RW
3B5h/3D5h
3/4
RW
3B5h/3D5h
3
R
3B5h/3D5h
R
3B5h/3D5h
W
3B5h/3D5h
Preliminary 65510
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