21150-AB Intel Corporation, 21150-AB Datasheet - Page 140

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21150-AB

Manufacturer Part Number
21150-AB
Description
Communications, Transparent PCI-to-PCI Bridge
Manufacturer
Intel Corporation
Datasheet

Specifications of 21150-AB

Case
QFP
21150
Dword Bit
13
The 21150 clock disable
15:14
Reserved
15.2.9
p_serr_l Status Register—Offset 6Ah
This section describes the p_serr_l status register.
This status register indicates the reason for the 21150’s assertion of p_serr_l.
Dword address = 68h
Byte enable p_cbe_l<3:0> = x0xxb
Dword Bit
16
Address parity error
Posted write data parity
17
error
18
Posted write nondelivery
Target abort during
19
posted write
Master abort during
20
posted write
132
Name
R/W
When 1—Signal s_clk_o<9> is disabled and
driven low.
When 0—Signal s_clk_o<9> is enabled.
R/W
Upon secondary bus reset, this bit is initialized
by shifting in a serial data stream. This bit is
assigned to correspond to the 21150
secondary clock input, s_clk.
R
Reserved. Returns 0 when read.
Name
R/W
When 1—Signal p_serr_l was asserted
because an address parity error was detected
R/W1TC
on either the primary or secondary PCI bus.
Reset value: 0.
When 1—Signal p_serr_l was asserted
because a posted write data parity error was
R/W1TC
detected on the target bus.
Reset value: 0.
When 1—Signal p_serr_l was asserted
because the 21150 was unable to deliver
posted write data to the target after 2
R/W1TC
attempts.
Reset value: 0.
When 1—Signal p_serr_l was asserted
because the 21150 received a target abort
R/W1TC
when delivering posted write data.
Reset value: 0.
When 1—Signal p_serr_l was asserted
because the 21150 received a master abort
R/W1TC
when attempting to deliver posted write data.
Reset value: 0.
Description
Description
24
Preliminary
Datasheet

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