21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 


Specifications of 21150-AB

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Dword Bit
21
Delayed write nondelivery
Delayed read—no data
22
from target
Delayed transaction
23
master timeout
15.3
Configuration Register Values After Reset
Table 35
lists the value of the 21150 configuration registers after reset. Reserved registers are not
listed and are always read as 0.
Table 35. Configuration Register Values After Reset (Sheet 1 of 2)
Byte Address
00–01h
02–03h
04–05h
06–07h
8h
09–0Bh
0Ch
0Dh
0Eh
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh–1Fh
20–21h
22–23h
24–25h
Preliminary
Datasheet
Name
R/W
When 1—Signal p_serr_l was asserted
because the 21150 was unable to deliver
R/W1TC
delayed write data after 2
Reset value: 0.
When 1—Signal p_serr_l was asserted
because the 21150 was unable to read any
R/W1TC
data from the target after 2
Reset value: 0.
When 1—Signal p_serr_l was asserted
because a master did not repeat a read or write
transaction before the master timeout counter
R/W1TC
expired on the initiator’s PCI bus.
Reset to 0.
Register Name
Vendor ID
Device ID
Command
Status
Revision ID
Class code
Cache line
Primary master latency timer
Header type
Primary bus number
Secondary bus number
Subordinate bus number
Secondary master latency timer
I/O base
I/O limit
Secondary status
Memory mapped I/O base
Memory-mapped I/O limit
Prefetchable memory base
21150
Description
24
attempts.
24
attempts.
Reset Value
1011h
0022h
0000h
0280h–21150-AA only
0290h–33 MHz 21150
02B0h–66 MHz capable 21150
1
xxh
060400h
00h
00h
01h
00h
00h
00h
00h
01h
01h
0280h–33 MHz 21150
02A0h–66 MHz capable 21150
0000h
0000h
0001h
133