21150-AB

Manufacturer Part Number21150-AB
DescriptionCommunications, Transparent PCI-to-PCI Bridge
ManufacturerIntel Corporation
21150-AB datasheet
 

Specifications of 21150-AB

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21150
The 21150 sets the secondary interface data parity detected bit in the secondary status register,
if the secondary parity error response bit is set in the bridge control register.
The 21150 captures the parity error condition to forward it back to the initiator on the primary
bus.
Similarly, for upstream transactions, when the 21150 is delivering data to the target on the primary
bus and p_perr_l is asserted by the target, the following events occur:
The 21150 sets the primary interface data parity detected bit in the status register, if the
primary parity error response bit is set in the command register.
The 21150 captures the parity error condition to forward it back to the initiator on the
secondary bus.
A delayed write transaction is completed on the initiator bus when the initiator repeats the write
transaction with the same address, command, data, and byte enable bits as the delayed write
command that is at the head of the posted data queue. Note that the parity bit is not compared when
determining whether the transaction matches those in the delayed transaction queues.
Two cases must be considered:
When parity error is detected on the initiator bus on a subsequent reattempt of the transaction
and was not detected on the target bus.
When parity error is forwarded back from the target bus.
For downstream delayed write transactions, when the parity error is detected on the initiator bus
and the 21150 has write status to return, the following events occur:
The 21150 first asserts p_trdy_l and then asserts p_perr_l two cycles later, if the primary
interface parity error response bit is set in the command register.
The 21150 sets the primary interface parity error detected bit in the status register.
Because there was not an exact data and parity match, the write status is not returned and the
transaction remains in the queue.
Similarly, for upstream delayed write transactions, when the parity error is detected on the initiator
bus and the 21150 has write status to return, the following events occur:
The 21150 first asserts s_trdy_l and then asserts s_perr_l two cycles later, if the secondary
interface parity error response bit is set in the bridge control register.
The 21150 sets the secondary interface parity error detected bit in the secondary status register.
Because there was not an exact data and parity match, the write status is not returned and the
transaction remains in the queue.
For downstream transactions, in the case where the parity error is being passed back from the target
bus and the parity error condition was not originally detected on the initiator bus, the following
events occur:
The 21150 asserts p_perr_l two cycles after the data transfer, if both of the following are true:
— The primary interface parity error response bit is set in the command register.
— The secondary interface parity error response bit is set in the bridge control register.
The 21150 completes the transaction normally.
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Preliminary
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