MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet
MC68EN360AI25VL
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MC68EN360AI25VL Summary of contents
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... Freescale Semiconductor, Inc. MC68360 QUad Integrated Communications Controller User’s Manual For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. ii For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... IEEE 1149.1 Test Access Port Section 9 Applications Section 10 Electrical Characteristics Section 11 Ordering Information and Mechanical Data Appendix A Serial Performance Appendix B Development Tools and Support Appendix C RISC Microcode from RAM Appendix D MC68MH360 Product Brief For More Information On This Product, PREFACE MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...
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... Data and Size Acknowledge (DSACK1–DSACK0). ................................ 2-8 2.1.7.2 Autovector/Interrupt Acknowledge (AVEC/IACK5).................................. 2-8 2.1.7.3 Address Strobe (AS). .............................................................................. 2-8 2.1.7.4 Data Strobe (DS)..................................................................................... 2-8 For More Information On This Product, Thi d Title Section 1 Introduction Section 2 Signal Descriptions MC68360 USER’S MANUAL Go to: www.freescale.com ith Table of Contents Page Number ...
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... GNDS1 and GNDS2. .............................................................................2-13 2.1.14.4 VCC and GND. ......................................................................................2-13 2.1.14.5 NC4–NC1...............................................................................................2-13 2.2 System Bus Signal Index in Slave Mode ...............................................2-14 2.3 On-Chip Peripherals Signal Index..........................................................2-15 ii For More Information On This Product, Title Section 3 MC68360 USER’S MANUAL Go to: www.freescale.com Page Number ...
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... Bus Exception Control Cycles ............................................................... 4-41 4.5.1 Bus Errors ............................................................................................. 4-42 4.5.2 Retry Operation ..................................................................................... 4-44 4.5.3 Halt Operation ....................................................................................... 4-46 4.5.4 Double Bus Fault................................................................................... 4-48 For More Information On This Product, Title QUICC Memory Map Section 4 Bus Operation MC68360 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number ...
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... System Control Instructions ...................................................................5-25 5.3.3.10 Condition Tests ......................................................................................5-26 5.3.4 Using the TBL Instructions.....................................................................5-27 5.3.4.1 Table Example 1: Standard Usage ........................................................5-28 5.3.4.2 Table Example 2: Compressed Table....................................................5-29 iv For More Information On This Product, Title Section 5 CPU32+ MC68360 USER’S MANUAL Go to: www.freescale.com Page Number ...
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... Type III—Correcting Faults by Conversion and Restart........................ 5-55 5.5.3.2.6 Type III—Correcting Faults via RTE...................................................... 5-55 5.5.3.2.7 Type IV—Correcting Faults via Software .............................................. 5-55 5.5.4 CPU32+ Stack Frames ......................................................................... 5-56 For More Information On This Product, Title MC68360 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number ...
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... Future Commands .................................................................................5-80 5.6.3 Deterministic Opcode Tracking..............................................................5-80 5.6.3.1 Instruction Fetch (IFETCH) ....................................................................5-80 5.6.3.2 Instruction Pipe (IPIPE1–IPIPE0) ..........................................................5-80 5.6.3.3 Opcode Tracking during Loop Mode......................................................5-82 vi For More Information On This Product, Title MC68360 USER’S MANUAL Go to: www.freescale.com Page Number ...
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... PIT Period Calculation........................................................................... 6-10 6.3.2.2 Using the PIT as a Real-Time Clock ..................................................... 6-11 6.3.3 Freeze Support...................................................................................... 6-11 6.3.4 Low-Power Stop Support ...................................................................... 6-11 6.4 Low Power in Normal Operation ........................................................... 6-12 For More Information On This Product, Title Section 6 MC68360 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number ...
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... Reset Status Register (RSR) .................................................................6-34 6.9.3.4 Software Watchdog Interrupt Vector Register (SWIV)...........................6-35 6.9.3.5 System Protection Control Register (SYPCR) .......................................6-35 6.9.3.6 Periodic Interrupt Control Register (PICR).............................................6-37 viii For More Information On This Product, Title MC68360 USER’S MANUAL Go to: www.freescale.com Page Number ...
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... RISC Controller Configuration Register (RCCR).................................... 7-4 7.1.2 RISC Microcode Revision Number......................................................... 7-5 7.2 Command Set ........................................................................................ 7-5 7.2.1 Command Register Examples................................................................. 7-8 7.2.2 Command Execution Latency ................................................................. 7-8 For More Information On This Product, Title Section 7 MC68360 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number ...
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... DONEx...................................................................................................7-33 7.6.4 IDMA Operation ....................................................................................7-34 7.6.4.1 Single Buffer ..........................................................................................7-34 7.6.4.2 Auto Buffer and Buffer Chaining ............................................................7-34 7.6.4.2.1 IDMA Parameter RAM ...........................................................................7-35 7.6.4.2.2 IDMA Buffer Descriptors (BDs) ..............................................................7-36 x For More Information On This Product, Title MC68360 USER’S MANUAL Go to: www.freescale.com Page Number ...
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... Two Multiplexed Channels with Dynamic Frames................................. 7-71 7.8.4.5 Programming SI RAM Entries ............................................................... 7-72 7.8.4.6 SI RAM Programming Example ............................................................ 7-75 7.8.4.7 SI RAM Dynamic Changes.................................................................... 7-75 7.8.5 SI Registers........................................................................................... 7-77 7.8.5.1 SI Global Mode Register (SIGMR) ........................................................ 7-77 For More Information On This Product, Title MC68360 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number ...
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... SCC Mask Register (SCCM) ...............................................................7-129 7.10.8.3 SCC Status Register (SCCS) ..............................................................7-129 7.10.9 SCC Initialization.................................................................................7-129 7.10.10 SCC Interrupt Handling........................................................................7-130 7.10.11 SCC Timing Control .............................................................................7-130 7.10.11.1 Synchronous Protocols ........................................................................7-130 xii For More Information On This Product, Title MC68360 USER’S MANUAL Go to: www.freescale.com Page Number ...
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... HDLC Controller Key Features............................................................ 7-170 7.10.17.2 HDLC Channel Frame Transmission Processing................................ 7-171 7.10.17.3 HDLC Channel Frame Reception Processing..................................... 7-172 7.10.17.4 HDLC Memory Map............................................................................. 7-172 7.10.17.5 HDLC Programming Model ................................................................. 7-174 For More Information On This Product, Title MC68360 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number ...
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... BISYNC Command Set........................................................................7-204 7.10.20.5.1 Transmit Commands............................................................................7-204 7.10.20.5.2 Receive Commands.............................................................................7-205 7.10.20.6 BISYNC Control Character Recognition ..............................................7-206 7.10.20.7 BSYNC-BISYNC SYNC Register.........................................................7-207 7.10.20.8 BDLE-BISYNC DLE Register...............................................................7-208 xiv For More Information On This Product, Title MC68360 USER’S MANUAL Go to: www.freescale.com Page Number ...
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... Ethernet Channel Frame Reception.................................................... 7-242 7.10.23.7 CAM Interface ..................................................................................... 7-243 7.10.23.8 Ethernet Memory Map......................................................................... 7-246 7.10.23.9 Ethernet Programming Model ............................................................. 7-250 7.10.23.10 Ethernet Command Set....................................................................... 7-250 For More Information On This Product, Title MC68360 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number ...
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... SMC UART Transmission Processing .................................................7-278 7.11.7.5 SMC UART Reception Processing ......................................................7-279 7.11.7.6 SMC UART Programming Model.........................................................7-279 7.11.7.7 SMC UART Command Set ..................................................................7-279 7.11.7.7.1 Transmit Commands............................................................................7-279 xvi For More Information On This Product, Title MC68360 USER’S MANUAL Go to: www.freescale.com Page Number ...
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... SMC Monitor Channel Transmission................................................... 7-306 7.11.14.1.2 SMC Monitor Channel Reception........................................................ 7-307 7.11.14.2 SMC C/I Channel Handling ................................................................. 7-307 7.11.14.2.1 SMC C/I Channel Transmission .......................................................... 7-307 7.11.14.2.2 SMC C/I Channel Reception ............................................................... 7-307 For More Information On This Product, Title MC68360 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number ...
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... PIP Key Features.................................................................................7-331 7.13.2 PIP Overview .......................................................................................7-332 7.13.3 General-Purpose I/O Pins (Port B) ......................................................7-333 7.13.4 Interlocked Data Transfers...................................................................7-333 7.13.5 Pulsed Data Transfers .........................................................................7-334 7.13.5.1 Busy Signal ..........................................................................................7-335 xviii For More Information On This Product, Title MC68360 USER’S MANUAL Go to: www.freescale.com Page Number ...
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... Receiver Errors ................................................................................... 7-354 7.13.8.21.1 Buffer Descriptor Busy ........................................................................ 7-354 7.13.8.22 Centronics Receive Buffer Descriptor ................................................. 7-354 7.13.8.23 Centronics Receiver Event Register (PIPE)........................................ 7-355 7.13.9 Port B Registers .................................................................................. 7-356 For More Information On This Product, Title MC68360 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number ...
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... CPM Interrupt Mask Register (CIMR) ..................................................7-380 7.15.5.4 CPM Interrupt In-Service Register (CISR) ...........................................7-380 7.15.6 Interrupt Handler Examples .................................................................7-381 7.15.6.1 Example 1—PC6 Interrupt Handler .....................................................7-381 7.15.6.2 Example 2—SCC1 Interrupt Handler...................................................7-381 xx For More Information On This Product, Title MC68360 USER’S MANUAL Go to: www.freescale.com Page Number ...
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... Step 1: Decide on Reset Stack Pointer and Initial Program Counter .... 9-13 Step 2: Stay in Supervisor Mode........................................................... 9-13 Step 3: Write the VBR ........................................................................... 9-14 For More Information On This Product, Title Section 8 Scan Chain Test Access Port Section 9 Applications MC68360 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number ...
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... QUICC Memory Interface Pins. .............................................................9-37 9.4.2.2 Regular EPROM. ...................................................................................9-38 9.4.2.3 Burst EPROM. .......................................................................................9-38 9.4.2.4 Flash EPROM. .......................................................................................9-41 9.4.2.5 Regular SRAM. ......................................................................................9-41 9.4.2.6 Burst SRAM. ..........................................................................................9-41 xxii For More Information On This Product, Title MC68360 USER’S MANUAL Go to: www.freescale.com Page Number ...
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... Bus Arbitration....................................................................................... 9-78 9.8.1.6 Breakpoint Generation .......................................................................... 9-78 9.8.1.7 Bus Monitor Function ............................................................................ 9-78 9.8.1.8 Spurious Interrupt Monitor..................................................................... 9-78 9.8.1.9 Software Watchdog ............................................................................... 9-79 9.8.1.10 Periodic Interval Timer .......................................................................... 9-79 For More Information On This Product, Title MC68360 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number ...
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... Bus Type Slave Mode Internal Read/write/IACK Cycles AC Electrical Specifications10-51 10.17 040 Bus Type SRAM/DRAM Cycles Ac Electrical Specifications .......10-56 10.18 IDMA AC Electrical Specifications ......................................................10-62 10.19 PIP/PIO AC Electrical Specifications ...................................................10-64 xxiv For More Information On This Product, Title Section 10 Electrical Characteristics MC68360 USER’S MANUAL Go to: www.freescale.com Page Number ...
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... MGCI Controller Key Features ................................................................C-3 C.2.3 Performance............................................................................................C-4 C.3 ATOM1/ATM Controller...........................................................................C-4 C.3.1 Key Features ...........................................................................................C-4 C.3.2 Performance............................................................................................C-5 For More Information On This Product, Title Section 11 Appendix A Serial Performance Appendix B Appendix C RISC Microcode from RAM MC68360 USER’S MANUAL Go to: www.freescale.com Table of Contents Page Number ...
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... The QMC Microcode............................................................................... D-7 D.2.5 Data Flow................................................................................................ D-8 D.2.6 Data Management .................................................................................. D-8 D.2.7 Performance ........................................................................................... D-9 D.2.8 Development Support ........................................................................... D-10 D.2.9 Ordering Information ............................................................................. D-10 xxvi For More Information On This Product, Title Appendix D MC68MH360 Product Brief MC68360 USER’S MANUAL Go to: www.freescale.com Page Number ...
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... QUICC Features Usable in Slave Mode • Memory Controller (Eight Banks) —Contains Complete Dynamic Random-Access Memory (DRAM) Controller —Each Bank Can Be a Chip Select or Support a DRAM Bank — Wait States For More Information On This Product, Thi d MC68360 USER’S MANUAL Go to: www.freescale.com ith versatile one- ...
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... Kbytes of Dual-Port RAM —14 Serial DMA (SDMA) Channels —Three Parallel I/O Registers with Open-Drain Capability —Each Serial Channel Can Have Its Own Pins (NMSI Mode) • Four Baud Rate Generators 1-2 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... Be internally Connected to Six Serial Channels (Four SCCs and Two SMCs) 1. SDLC is a trademark of International Business Machines. 2. AppleTalk is a registered trademark of Apple Computer, Inc. 3. DDCMP is a trademark of Digital Equipment Corporation. For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com Introduction ...
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... CHIP SELECTS FEATURES IMB (32 BIT) CPM COMMUNICATIONS PROCESSOR 2.5-KBYTE RISC DUAL-PORT CONTROLLER RAM INTERRUPT DMAs CONTROLLER OTHER TIMER SLOT FEATURES ASSIGNER MC68360 USER’S MANUAL Go to: www.freescale.com JTAG BREAKPOINT LOGIC DRAM CONTROLLER AND SYSTEM EXTERNAL I/F BUS INTERFACE FOUR GENERAL- PURPOSE TIMERS ...
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... Regardless of the choice of the system bus size, dynamic bus sizing is supported. Bus sizing allows 8-, 16-, and 32-bit peripherals and memory to exist in the 32- bit system bus mode and 8- and 16-bit peripherals and memory to exist in the 16-bit system bus mode. For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com Introduction ...
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... Although the features of the SIM60 do not exactly correspond to those of the MC68302 SIM, they are very similar. The QUICC SIM60 combines the best MC68302 SIM features with the best MC68340 SIM features for improved performance. 1-6 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... Although the registers used to initialize the QUICC CPM are new (for example, the SCM on the MC68302 is replaced with the GSMR and PSMR on the QUICC), most registers retain their original purpose such as the SCC event, SCC mask, SCC status, and com- For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com Introduction ...
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... For More Information On This Product, 8-BIT BOOT (FLASH OR REGULAR) CS0 CE (ENABLE (OUTPUT ENABLE) WE0 WE (WRITE) DATA DATA ADDRESS 16- OR 32-BIT DRAM SIMM (OPTIONAL PARITY) RAS1 RAS CAS3–CAS0 R/W W (WRITE) DATA ADDRESS PARITY MC68360 USER’S MANUAL Go to: www.freescale.com EPROM ...
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... OE (OUTPUT ENABLE) WE (WRITE) DATA ADDRESS 8-, 16-, OR 32-BIT SRAM E (ENABLE) G (OUTPUT ENABLE) W (WRITE) DATA ADDRESS RAS RAS BUFFER CAS3–CAS0 W (WRITE) DATA ADDRESS PARITY ). The MC68160 EEST supports MC68360 USER’S MANUAL Go to: www.freescale.com Introduction 16- OR 32-BIT TWO DRAM SIMMs (OPTIONAL PARITY) ...
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... For More Information On This Product, ETHERNET QUICC MC68160 SCC1 EEST QUICC MC68160 SCC1 EEST QUICC MC68160 SCC1 EEST QUICC RS422 SCC XCVR QUICC RS422 SCC XCVR MC68302 MC68195 LA RS422 SCC XCVR protocol without the need for the MC68195. MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... HDLC bus—any node can obtain mastership. 2. The QUICC handles collisions without external glue. Figure 1-6. HDLC Bus LAN QUICC SCC QUICC SDLC BUS SCC MC68302 SCC NOTE: No collisions are allowed in this master-slave approach. Also available on the MC68302. MC68360 USER’S MANUAL Go to: www.freescale.com Introduction ...
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... UART MC68302 SCC NOTES: 1. Simple LAN based on UART mode. 2. Ninth bit is an "address" bit. QUICC SPI MASTER/SLAVE QUICC SPI SPI BUS MASTER/SLAVE QUICC SPI MASTER/SLAVE NOTE: SPI bus configuration—each QUICC can be the master in turn. MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... For More Information On This Product, SPI BUS SCP SPI SLAVE SPI SLAVE SPI BUS SPI SPI MASTER SLAVE SPI SLAVE CENTRONICS INTERFACE PIP 8 DATA LINES MC68360 USER’S MANUAL Go to: www.freescale.com Introduction QUICC EEPROMS ETC. QUICC EEPROMS ETC. HOST COMPUTER OR PRINTER ...
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... Figure 1-16 shows other point-to-point options that are possible with the QUICC and the MC68302. 1-14 For More Information On This Product, PARALLEL INTERFACE PIP PIP 8 DATA LINES HDLC/SDLC BISYNC MC68302 UART TRANSPARENT SCC SCC HDLC/SDLC BISYNC UART QUICC TRANSPARENT SYNCHRONOUS UART SS#7 SCC SCC MC68360 USER’S MANUAL Go to: www.freescale.com QUICC ...
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... For More Information On This Product, MC68302 SMC SCC UART TRANSPARENT MC68302 SMC SCP TRANSPARENT QUICC SMC SMC UART TRANSPARENT QUICC TIME TIME DIVISION MULTIPLEXED BUS SLOT ASSIGNER T1, CEPT, IDL, GCI, ISDN, PRIMARY RATE, USER-DEFINED MC68360 USER’S MANUAL Go to: www.freescale.com Introduction ...
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... SMC SMC AND SMCs MAY BE CONNECTED TO ANY TDM. with the time slot assigner. QUICC SCC SCC TIME SCC SLOT SCC ASSIGNER SMC SMC QUICC SCC SCC SCC TIME SLOT SCC ASSIGNER SMC SMC MC68360 USER’S MANUAL Go to: www.freescale.com TDM BUS ...
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... SMC1 RS-232 QUICC SYSTEM BUS QUICC SLAVE CPU32+ CPU32+ SCC SCC SCC SCC SMC SMC SPI MC68360 USER’S MANUAL Go to: www.freescale.com Introduction ETHERNET SIA APPLE TALK X.25 (HDLC) FRAME RELAY (HDLC) TRANSPARENT DATA SCC SCC SCC SCC SMC SMC SPI ...
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... MC68EC040 Figure 1-22. MC68040 Companion Mode 1-18 For More Information On This Product, QUICC SLAVE MC68EC040 SUPPORT FUNCTIONS SYSTEM BUS CONTROL MEMORY CONTROLLER EPROM DRAM ADDRESS MUXs SRAM MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ SCC SCC SCC SCC SMC SMC SPI ...
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... WE1—Corresponds to A30 and selects data bits 23–16. Also may be referred to as UM- WE. WE2—Corresponds to A29 and selects data bits 15–8. Also may be referred to as LMWE. WE3—Corresponds to A28 and selects data bits 7–0. Also may be referred to as LLWE. For More Information On This Product, Thi d MC68360 USER’S MANUAL Go to: www.freescale.com ith ...
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... BUS CONTROL BUS ARBITRATION QUICC MC68360 SYSTEM CONTROL 240 PINS INTERRUPT CONTROL MEMORY CONTROLLER TEST CLOCK MC68360 USER’S MANUAL Go to: www.freescale.com A27–A0 A31–A28/WE3–WE0 FC2–FC0/TM2–TM0 FC3/TT0 D31–D16 D15–D0 PRTY1–PRTY0/IOUT1–IOUT2 PRTY2/IOUT0/RQOUT PRTY3/16BM SIZ0 ...
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... DRAM accesses if internal multiplexing is not used (O). Provides external interrupt requests to the CPU32+ at prior- IRQ7–IRQ1 ity levels 7–1. (I) Autovector request during an interrupt acknowledge cycle AVEC/IACK5 (open-drain I/O) or interrupt level 5 acknowledge line (O). MC68360 USER’S MANUAL Go to: www.freescale.com Signal Descriptions Function ...
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... Special ground for fast AC timing on certain system bus sig- GNDS1 nals. Special ground for fast AC timing on certain system bus sig- GNDS2 nals. VCC, GND Power supply and return to the QUICC. NC4–NC1 Four no-connect pins. MC68360 USER’S MANUAL Go to: www.freescale.com Function ...
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... D31–D16. Additionally, if the QUICC is configured into 16-bit bus mode, the D31–D16 For More Information On This Product Address Space Reserved (Motorola User Data Space User Program Space Reserved (User Reserved (Motorola Supervisor Data Space Supervisor Program Space Supervisor CPU Space DMA Space NOTE MC68360 USER’S MANUAL Go to: www.freescale.com Signal Descriptions ...
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... CHIP SELECT/ROW ADDRESS SELECT/INTERRUPT ACKNOWLEDGE (CS7/ RAS7/IACK7). This pin can be programmed as a CS7/RAS7 pin or as the IACK7 line. See Section 6 System Integration Module (SIM60) for more information on this selection. 2-6 For More Information On This Product, NOTE MC68360 USER’S MANUAL Go to: www.freescale.com chip- ...
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... Bus Control Signals These signals control the bus transfer operations of the QUICC. Refer to Section 4 Bus Operation for more information on these signals. For More Information On This Product, – ) IRQ7 IRQ1 MC68360 USER’S MANUAL Go to: www.freescale.com Signal Descriptions ...
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... Complete cycle—data bus port size is 8 bits. Complete cycle—data bus port size is 16 bits. Complete cycle—data bus port size is 32 bits. Table 2-4. SIZx Encoding SIZ1 SIZ0 Transfer Size 0 1 Byte 1 0 Word Bytes 0 0 Long Word MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... DOUBLE-DRIVE (BCLRO/CONFIG1/RAS2DD). This pin can be programmed as the bus clear out output or as the initial configuration pin 1 input signal during system reset or as the RAS2DD output double-drive signal. For More Information On This Product, NOTE MC68360 USER’S MANUAL Go to: www.freescale.com Signal Descriptions ...
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... Section 6 System Integration Module (SIM60) for more information on these clock signals. 2.1.10.1 SYSTEM CLOCK OUTPUTS (CLKO2–CLKO1). These output signals reflect the general system clock and are used as the bus timing reference by external devices. CLKO1 2-10 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... Multi. Factor EXTAL Freq. CLKIN to the ( (examples) Reserved Reserved 1 >10 MHz 401 4.192 MHz 401 32.768 kHz MC68360 USER’S MANUAL Go to: www.freescale.com Signal Descriptions Initial Freq. PLL (VCO/2) Reserved Reserved =EXTAL =EXTAL 32.75 kHz 13.14 MHz 32.768 kHz 13.14 MHz active- ...
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... After reset, these pins may be programmed to their other function. The CONFIG2–CONFIG0 lines have internal pullup resistors so that if they are left floating, the default selection will be 111. See Section 6 System Integration Module (SIM60) for more information. 2-12 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... MC68040 companion mode; global CS 32-bit size; MBAR at $003FF00; BR input, BG output. CPU enabled; global CS 32-bit size; MBAR at $003FF00. CPU enabled; global CS 16-bit size; MBAR at $003FF00. Slave mode; global CS disabled; MBAR at $003FF04. CPU enabled; global CS 8-bit size; MBAR at $003FF00. (Default) NOTE MC68360 USER’S MANUAL Go to: www.freescale.com Signal Descriptions ...
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... Provides an MBAR access enable (I), or the initial QUICC con- CONFIG2 figuration select. (I) IRQ6,4,1/ Provides an interrupt request to the QUICC interrupt controller IOUT2–IOUT0/ (I), or interrupt output signals (O) (either RQOUT as a single re- IRQOUT quest or IOUT2–IOUT0 encoded). MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... Input clocks to the SCCs, SMCs, SI, and the baud rate generators. (I) An acknowledgement (output) by the IDMA that an IDMA transfer is in progress. (O) of data. (I/O) Time reference input to the timer that allows it to function as a counter. (I) MC68360 USER’S MANUAL Go to: www.freescale.com Signal Descriptions Function ...
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... PIP Data I/O Pins This input causes the PIP output data to be placed on the PIP data pins. This input causes data on the PIP data pins to be latched by the PIP STRBI as input data. Ethernet receive frame. MC68360 USER’S MANUAL Go to: www.freescale.com Function ...
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... Freescale Semiconductor, Inc. Signal Descriptions 2-17 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Signal Descriptions 2-18 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... The 8-Kbyte block is divided into two 4-Kbyte sections. The RAM occupies the first section; the internal registers occupy the second section. The location of the QUICC registers is shown in Figure 3-1. For More Information On This Product, Thi d MC68360 USER’S MANUAL Go to: www.freescale.com ith ...
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... It may be partitioned in several ways, allowing programmable partition sizes to fit the system requirements. This is described in Section 7 Communication Processor Mod- ule (CPM). 3-2 For More Information On This Product, MBAR (SIM) DPRBASE (DUAL-PORT RAM BASE) DUAL-PORT RAM REGB (REGISTER BASE) = DPRBASE + 4K INTERNAL REGISTERS NOTE MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... SPI Base DPRBASE + $D80 Timer Base DPRBASE + $DB0 SCC3 Base DPRBASE + $E00 IDMA1 Base DPRBASE + $E70 MC68360 USER’S MANUAL Go to: www.freescale.com QUICC Memory Map Description User Data / BDs / Microcode Program User Data / BDs User Data / BDs / Microcode Scratch User Data / BDs ...
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... SIM Registers Memory Map Table 3-3 lists the SIM registers memory map. 3-4 For More Information On This Product, SMC1 Base DPRBASE + $E80 SCC4 Base DPRBASE + $F00 IDMA2 Base DPRBASE + $F70 SMC2 Base DPRBASE + $F80 NOTES MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... Global Memory Register Memory Controller Status Register Reserved Base Register 0 Option Register 0 Reserved Base Register 1 Option Register 1 Reserved Base Register 2 Option Register 2 MC68360 USER’S MANUAL Go to: www.freescale.com QUICC Memory Map Reset Value Block 0000 7cff H SIM 00 H H/S f(MODCK1) H f(MODCK1–0) ...
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... Reserved Channel Configuration Register Reserved IDMA1 Mode Register Reserved IDMA1 Source Address Pointer IDMA1 Destination Address Pointer IDMA1 Byte Count Register IDMA1 Function Code Register MC68360 USER’S MANUAL Go to: www.freescale.com 0000 0050 H F000 000x H 0000 0050 H F000 000x H 0000 0050 ...
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... Port A Data Register Reserved Port C Data Direction Register Port C Pin Assignment Register Port C Special Options Port C Data Register Port C Interrupt Control Register Reserved Timer Global Configuration Register MC68360 USER’S MANUAL Go to: www.freescale.com QUICC Memory Map SDMA 0000 H XXXX XXXX IDMA2 ...
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... BRG1 Configuration Register BRG2 Configuration Register BRG3 Configuration Register BRG4 Configuration Register SCC1 General Mode Register SCC1 General Mode Register SCC1 Protocol-Specific Mode Register 0000 SCC1 Transmit on Demand MC68360 USER’S MANUAL Go to: www.freescale.com 0000 0000 FFFF FFFF 0000 0000 0000 0000 ...
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... SCC4 Data Sync. Register SCC4 Event Register SCC4 Mask Register SCC4 Status Register Reserved SMC1 Mode Register SMC1 Event Register SMC1 Mask Register Reserved MC68360 USER’S MANUAL Go to: www.freescale.com QUICC Memory Map 7E7E 0000 0000 00 0000 0000 SCC2 0000 0000 0000 ...
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... Port B Data Direction Register Port B Pin Assignment Register Port B Open Drain Register Port B Data Register Reserved SI Mode Register SI Global Mode Register SI Status Register SI Command Register Reserved SI Clock Route SI RAM Pointers Reserved MC68360 USER’S MANUAL Go to: www.freescale.com 0000 SMC2 00 00 0000 H SPI 0000 H PIP ...
Page 77
... The user should be aware that misalignment of word or long- word operands can cause the CPU32+ to perform multiple bus cycles for operand transfers; therefore, processor performance is optimized if word and long-word memory operands are For More Information On This Product, Thi d NOTE MC68360 USER’S MANUAL Go to: www.freescale.com ith ...
Page 78
... In addition to meeting input setup and hold times for deterministic operation, all input signals must obey the protocols described in this sec- tion. CLK EXT Figure 4-1. Input Sample Window 4-2 For More Information On This Product SAMPLE WINDOW MC68360 USER’S MANUAL Go to: www.freescale.com su ...
Page 79
... For More Information On This Product Address Spaces 0 0 Reserved (Motorola User Data Space 1 0 User Program Space 1 1 Reserved (User Reserved (Motorola Supervisor Data Space 1 0 Supervisor Program Space 1 1 Supervisor CPU Space DMA space MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation ...
Page 80
... The lower write enable (WE3) indicates that the lower eight bits of the data bus contain valid data during a write cycle. 4-4 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
Page 81
... BUS ERROR (BERR). This signal is also a bus cycle termination indicator and can be used in the absence of DSACKx to indicate a bus error condition. BERR can also be asserted in conjunction with DSACKx to indicate a bus error condition, provided it meets the For More Information On This Product, NOTE MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation ...
Page 82
... Table 4-2. DSACKx Encoding Result 1 Insert Wait States in Current Bus Cycle 0 Complete Cycle—Data Bus Port Size is 8 Bits 1 Complete Cycle—Data Bus Port Size is 16 Bits 0 Complete Cycle—Data Bus Port Size is 32 Bits MC68360 USER’S MANUAL Go to: www.freescale.com ...
Page 83
... The same is true for any of the operand bytes. The positioning of bytes is determined by the size and address outputs. For More Information On This Product, 0P0 0P1 0P2 15 WORD OPERAND 0P2 BYTE OPERAND MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation 0 0P3 0 0P3 7 0 0P3 ...
Page 84
... D15–D8 BYTE 1 BYTE 2 BYTE 1 16-BIT PORT BYTE 3 8-BIT PORT Table 4-3. SIZx Encoding SIZ1 SIZ0 Size 0 1 Byte 1 0 Word Bytes 0 0 Long Word MC68360 USER’S MANUAL Go to: www.freescale.com 0P3 3 INTERNAL TO THE MC68360 D7–D0 EXTERNAL BUS BYTE 3 32-BIT PORT ...
Page 85
... OP1 OP0 OP1 OP2 OP3 x OP0 OP1 OP2 x x OP0 OP1 OP0 MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation Byte Port Word Port External External Data Data Bytes Required Bytes Required D31:D24 OP3 x OP3 x OP3 OP3 OP3 x OP3 x OP3 OP3 ...
Page 86
... OP0 OP0 OP0 LONG-WORD OPERAND 0P1 0P2 0P3 D16 MC68360 LSB SIZ1 SIZ0 A1 A0 0P1 0P3 MC68360 USER’S MANUAL Go to: www.freescale.com D15:D8 D7: OP3 OP3 x OP3 x OP3 OP3 x x OP2 OP3 x OP3 OP2 OP3 OP2 x OP2 OP2 OP3 x OP1 OP2 OP3 ...
Page 87
... PC relative data addresses), some performance degradation occurs when additional bus cycles are required for long-word or word operands For More Information On This Product 0P0 0P1 WORD WRITE WORD WRITE LONG-WORD OPERAND WRITE TO 16-BIT PORT MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation S4 0P2 0P3 ...
Page 88
... Attempting to prefetch an instruction word at an odd address causes an address error exception. 15 WORD OPERAND 0P2 D31 DATA BUS BYTE MEMORY 0P2 0P3 Figure 4-6. Example of Word Transfer to Byte Port 4-12 For More Information On This Product, 0 0P3 D24 MC68360 SIZ1 SIZ0 MC68360 USER’S MANUAL Go to: www.freescale.com MEMORY CONTROL A0 DSACK1 DSACK0 ...
Page 89
... Figure 4-9 shows the associated bus transfer signal timing. For More Information On This Product OP2 OP3 OP2 OP3 BYTE WRITE WORD OPERAND WRITE MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation S2 S4 OP3 OP3 OP3 OP3 BYTE WRITE ...
Page 90
... MSB 0P0 XXX 0P1 0P2 OP3 XXX Figure 4-8. Misaligned Long-Word Transfer to Word Port Example 4-14 For More Information On This Product, LONG-WORD OPERAND 0P1 0P2 0P3 D16 MC68360 LSB SIZ1 SIZ0 MC68360 USER’S MANUAL Go to: www.freescale.com 0 MEMORY CONTROL DSACK1 DSACK0 ...
Page 91
... For More Information On This Product 0P0 0P1 0P0 0P2 0P1 0P1 0P2 0P2 WORD WRITE LONG-WORD OPERAND WRITE MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation 0P3 0P3 0P3 0P3 BYTE WRITE ...
Page 92
... OP2 D31 DATA BUS WORD MEMORY MSB XXX 0P3 Figure 4-10. Misaligned Word Transfer to Word Port Example 4-16 For More Information On This Product, 0 OP3 D16 MC68360 SIZ1 SIZ0 LSB 0P2 XXX MC68360 USER’S MANUAL Go to: www.freescale.com MEMORY CONTROL DSACK1 DSACK0 ...
Page 93
... Since the memory is long-word organized, no further bus cycles are necessary. For More Information On This Product 0P2 0P2 0P3 0P2 WORD WRITE BYTE WRITE WORD OPERAND WRITE TO A1/ MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation S4 0P3 0P3 0P3 0P3 ...
Page 94
... XXX XXX 0P1 0P2 Figure 4-12. Misaligned Long-Word Transfer to Long-Word Port Example 4-18 For More Information On This Product, 0 0P2 0P3 D0 MC68EC030 LMB LSB SIZ1 SIZ0 0P0 0P0 0 0 0P3 XXX 1 1 MC68360 USER’S MANUAL Go to: www.freescale.com MEMORY CONTROL DSACK1 DSACK0 ...
Page 95
... For More Information On This Product 0P0 0P0 0P1 0P0 3-BYTE WRITE BYTE WRITE LONG-WORD OPERAND WRITE MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation S4 0P1 0P2 0P3 0P1 ...
Page 96
... BERR and/or HALT must be asserted within the time specified after DSACKx is 4-20 For More Information On This Product, on Write Bus Cycles Number of Bus Cycles 1:2:4 N/A N/A 1:1:1 1:1:1 1:1:1 1:1:2 1:2:2 1:1:2 1:2:4 2:3:4 2:2:4 MC68360 USER’S MANUAL Go to: www.freescale.com 11 N/A 1:1:1 2:2:2 2:3:4 ...
Page 97
... S4. Figure 4-14 shows the DSACKx timing for a read with two wait states, followed by a fast termination read and write. For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation ...
Page 98
... QUICC states described for the CPU32+. The clock cycles used in the descriptions and timing diagrams of data transfer cycles are independent of the clock fre- quency. Bus operations are described in terms of external bus states. 4-22 For More Information On This Product FAST TERMINATION READ NOTES MC68360 USER’S MANUAL Go to: www.freescale.com FAST TERMINATION WRITE ...
Page 99
... REMOVE DATA FROM D31–D0 2) NEGATE DSACKx EXTERNAL DEVICE PRESENT DATA 1) DECODE ADDRESS 2) PLACE DATA ON D31–D24, OR D23–16, OR D15–D8, OR D7–D0. 3) ASSERT DSACKx TERMINATE CYCLE 1) REMOVE DATA FROM D31–D0 2) NEGATE DSACKx MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation ...
Page 100
... DSACK0 D31–D24 D23–D16 D15–D8 D7–D0 WORD READ Figure 4-17. Byte and Word Read Cycles—32-Bit Port Timing 4-24 For More Information On This Product BYTE 0P2 0P3 0P3 BYTE READ MC68360 USER’S MANUAL Go to: www.freescale.com 0P3 BYTE READ ...
Page 101
... The QUICC drives R/W high for a read cycle. SIZ1 and SIZ0 become valid, indicating the number of bytes requested for transfer. For More Information On This Product WORD 0P0 0P2 0P3 0P1 WORD READ MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation LONG WORD 0P0 0P1 0P2 0P3 LONG-WORD READ FROM 32-BIT PORT ...
Page 102
... START NEXT CYCLE Figure 4-19. Write Cycle Flowchart 4-26 For More Information On This Product, EXTERNAL DEVICE PRESENT DATA 1) DECODE ADDRESS 2) PLACE DATA ON D31–D0 3) ASSERT DATA TRANSFER AND SIZE ACKNOWLEDGE (DSACKx) TERMINATE CYCLE 1) NEGATE DSACKx MC68360 USER’S MANUAL Go to: www.freescale.com ...
Page 103
... WE3) are asserted simultaneously with AS. State 2—During S2, the QUICC places the data to be written onto D31–D0 and samples DSACKx at the end of S2. For More Information On This Product WRITE WRITE MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation READ WITH WAIT STATES ...
Page 104
... The QUICC does not issue a bus grant (BG) signal in response to a bus request (BR) signal during this operation. Figure 4- example of a functional timing diagram of a read-modify-write instruction specified in terms of clock periods. 4-28 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
Page 105
... QUICC inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchro- For More Information On This Product READ WRITE INDIVISIBLE CYCLE MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation S4 S0 ...
Page 106
... S5. If more than one write cycle is required, S0–S5 are repeated for each write cycle. The external device keeps DSACKx asserted until it detects the negation (whichever it detects first). The device must remove its data and 4-30 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
Page 107
... If the bus cycle is terminated by DSACKx, the QUICC uses the data on the bus to replace the BKPT instruction in the internal instruction pipeline and then begins execution of that instruction. For More Information On This Product, CPU SPACE CYCLES ADDRESS BUS CPU SPACE TYPE FIELD MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation 0 BKPT LEVEL ...
Page 108
... The breakpoint operation flowchart is shown in Figure 4-23. Figure 4-24 and Figure 4-25 show the timing diagrams for the breakpoint acknowledge cycle with instruction opcodes supplied on the cycle and with an exception signaled, respectively. 4-32 For More Information On This Product, NOTE MC68360 USER’S MANUAL Go to: www.freescale.com ...
Page 109
... INITIATE ILLEGAL INSTRUCTION PROCESSING IF BKPT PIN ASSERTED: 1) INITIATE HARDWARE BREAKPOINT PROCESSING Figure 4-23. Breakpoint Operation Flowchart MC68360 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Bus Operation EXTERNAL DEVICE IF BREAKPOINT INSTRUCTION EXECUTED: 1) PLACE REPLACEMENT OPCODE ON DATA BUS 2) ASSERT DSACKx ...
Page 110
... BERR HALT BKPT BREAKPOINT OCCURS Figure 4-24. Breakpoint Acknowledge Cycle Timing (Opcode Returned) 4-34 For More Information On This Product BREAKPOINT ENCODING (0000) BREAKPOINT NUMBER/T-BIT READ INSTRUCTION WORD FETCH MC68360 USER’S MANUAL Go to: www.freescale.com CPU SPACE FETCHED INSTRUCTION EXECUTION BREAKPOINT ACKNOWLEDGE ...
Page 111
... The external bus interface must get a copy of the interrupt mask level from the CPU32+, For More Information On This Product BREAKPOINT ENCODING (0000) BREAKPOINT NUMBER/T-BIT READ BUS ERROR ASSERTED MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation CPU SPACE EXCEPTION STACKING BREAKPOINT ACKNOWLEDGE ...
Page 112
... The following paragraphs describe the interrupt acknowledge cycle for these devices. Other interrupting conditions or devices cannot supply a vector number and use the autovector cycle described in 4.4.4.2 Autovector Interrupt Acknowledge Cycle. 4-36 For More Information On This Product — MC68360 USER’S MANUAL Go to: www.freescale.com ...
Page 113
... TYPE FIELD (A19–A16 SET R/W TO READ 6) SET FC3–FC0 TO 0111 7) DRIVE SIZx PINS TO INDICATE A ONE-BYTE TRANSFER 8) NEGATE BCLRO. 9) ASSERT AS, DS, AND OE ACQUIRE VECTOR NUMBER 1) LATCH VECTOR NUMBER 2) NEGATE AS, DS, AND OE START NEXT CYCLE MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation QUICC ...
Page 114
... AVEC to terminate the cycle. The DSACKx signals may not be asserted 4-38 For More Information On This Product, 0–2 CLOCKS INTERRUPT LEVEL CPU SPACE 1 BYTE VECTOR FROM 16-BIT PORT VECTOR FROM 8-BIT PORT INTERNAL ARBITRATION IACK CYCLE MC68360 USER’S MANUAL Go to: www.freescale.com S0 S2 WRITE STACK ...
Page 115
... AVEC pin will not be asserted externally). Seven distinct autovectors can be used, corresponding to the seven levels of interrupt available with signals IRQ7–IRQ1. Figure 4-28 shows the timing for an autovector operation. For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation ...
Page 116
... When no internal module (including the SIM60, which responds for external requests) responds during an interrupt acknowledge cycle by arbitrating for the 4-40 For More Information On This Product 0–2 CLOCKS* INTERRUPT LEVEL CPU SPACE 1 BYTE INTERNAL ARBITRATION IACK CYCLE MC68360 USER’S MANUAL Go to: www.freescale.com WRITE STACK ...
Page 117
... Section 10 Electrical Characteristics. DSACKx, BERR, and HALT may be negated after AS. If DSACKx or BERR remain asserted into S2 of the next bus cycle, that cycle may be terminated prematurely. For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation ...
Page 118
... Normal cycle terminate and halt; continue when HALT negated Terminate and take bus error exception, possibly deferred Terminate and take bus error exception, possibly deferred Terminate and retry when HALT negated Terminate and retry when HALT negated. A MC68360 USER’S MANUAL Go to: www.freescale.com Result ...
Page 119
... Exceptions are taken in both cases. (Refer to Section 5 CPU32+ for details of bus error exception processing CLKO1 A31–A0 FC3–FC0 R DSACKx D31–D0 BERR READ CYCLE WITH BUS Figure 4-29. Bus Error without DSACKx For More Information On This Product INTERNAL ERROR PROCESSING MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation STACK WRITE ...
Page 120
... After a synchronization delay, the QUICC retries the previous cycle using the same access information (address, function code, size, etc.). BERR should be negated before S2 of the retried cycle to ensure correct operation of the retried cycle. 4-44 For More Information On This Product WRITE INTERNAL CYCLE PROCESSING MC68360 USER’S MANUAL Go to: www.freescale.com S2 S4 STACK WRITE ...
Page 121
... For More Information On This Product DATA IGNORED HALT RETRY Figure 4-31. Retry Sequence NOTE MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation READ RERUN ...
Page 122
... The single-step operation and the software trace capability allow the system debugger to trace single bus cycles, sin- gle instructions, or changes in program flow. 4-46 For More Information On This Product WRITE HALT CYCLE MC68360 USER’S MANUAL Go to: www.freescale.com S2 S4 WRITE RERUN ...
Page 123
... QUICC coupled with the HALT signal being asserted late into an internal-to-external bus cycle. Note that show cycles mode is not the normal configura- tion for the QUICC. For More Information On This Product, NOTES MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation ...
Page 124
... QUICC. However, bus arbitration can still occur (refer to 4.6 Bus Arbitration). A second bus error or address error that occurs after exception processing has 4-48 For More Information On This Product READ HALT (ARBITRATION PERMITTED WHILE THE PROCESSOR IS HALTED) Figure 4-33. HALT Timing MC68360 USER’S MANUAL Go to: www.freescale.com READ ...
Page 125
... BGACK and maintains BGACK during the entire bus cycle (or cycles) for which it is bus master. The following conditions must be met for an external device to assume mastership of the bus through the normal bus arbitration procedure: it must have For More Information On This Product, NOTE MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation ...
Page 126
... TO BE NEGATED 3) NEXT BUS MASTER ASSERTS BGACK TO BECOME NEW MASTER 4) BUS MASTER NEGATES BR OPERATE AS BUS MASTER 1) PERFORM DATA TRANSFERS (READ AND WRITE CYCLES) ACCORDING TO THE SAME RULES THE PROCESSOR USES RELEASE BUS MASTERSHIP 1) NEGATE BGACK MC68360 USER’S MANUAL Go to: www.freescale.com ...
Page 127
... Freescale Semiconductor, Inc. CLKO1 A31–A0 D31– DSACK1–DSACK0 BR BG BGACK NOTE: BR has synchronous timing. BR has asynchronous timing. Figure 4-35. Bus Arbitration Timing Diagram—Idle Bus Case For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation ...
Page 128
... This prevents unnecessary interference with ordinary processing if the arbitration circuitry inadvertently responds to noise external device determines that it no longer requires use of the bus before it has been granted mastership. 4-52 For More Information On This Product MC68360 USER’S MANUAL Go to: www.freescale.com ...
Page 129
... QUICC internal masters requests an external accesses, the mini- mum time depends on internal synchronization plus one clock. • If SHEN1–SHEN0 = 1 , another clock is added for internal bus arbitration. For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation ...
Page 130
... The QUICC does not allow arbitration of the external bus during the RMC sequence. For the duration of this sequence, the QUICC ignores the BR input. If mastership of the bus is required during an RMC operation, BERR must be used to abort the RMC sequence. 4-54 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
Page 131
... For More Information On This Product STATE STATE STATE 6 RA G—BUS GRANT T —THREE-STATE SIGNAL TO BUS CONTROL V—BUS AVAILABLE TO BUS CONTROL MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation STATE ...
Page 132
... EXTERNAL MASTER ACCESS TO DUAL PORT RAM QUICC REQUIRES EXTERNAL BUS HALT IS ASSERTED AND DRAM REFRESH DOES NOT REQUIRE EXTERNAL BUS QUICC OWNS BUS BR NEGATED BGACK ASSERTED QUICC STILL NEEDS BUS MC68360 USER’S MANUAL Go to: www.freescale.com QUICC WAITING FOR BUS BR ASSERTED ...
Page 133
... USE OF BUS INTERNAL MASTER (IDMA, SDMA, OR DRAM REFRESH) REQUESTS BUS HALT IS ASSERTED AND DRAM REFRESH DOES NOT REQUIRE EXTERNAL BUS QUICC OWNS BUS BG NEGATED BB ASSERTED QUICC STILL NEEDS BUS MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation QUICC WAITING FOR BUS BG NEGATED ...
Page 134
... A31–A0 D31– R/W DSACK1-DSACK0 BR (OUT) BG (IN) BGACK (IN/OUT) NOTES: 1. Synchronous arbitration with SHEN1–SHEN0 = 00. 2. Minimum bus idle time. Figure 4-40. Slave Mode Bus Arbitration Timing Diagram 4-58 For More Information On This Product MC68360 USER’S MANUAL Go to: www.freescale.com S5 ...
Page 135
... QUICC supports the interrupt acknowledge cycles presented in 4.4.4 Interrupt Acknowledge Bus Cycles. The QUICC also supports the MC68EC040 read and write accesses and inter- rupt acknowledge cycles (see Figure 4-41–Figure 4-44). For More Information On This Product, NOTE NOTE NOTE MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation ...
Page 136
... D31–D0 Figure 4-41. MC68EC040 Internal Registers Read Cycle C1 CLKO1 A31–A0 SIZ1–SIZ0 TT1–TT0 TM2–TT0 R TBI D31–D0 Figure 4-42. MC68EC040 Internal Registers Write Cycle 4-60 For More Information On This Product MC68360 USER’S MANUAL Go to: www.freescale.com CW CW ...
Page 137
... A31–A0 SIZ1–SIZ0 TT1–TT0 TM2–TM0 R TBI D31–D8 D7–D0 IACK7 IACK1 Figure 4-44. MC68EC040 Interrupt Acknowledge Cycle MC68360 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com INTERRUPT LEVEL INTERNAL ARBITRATION INTERRUPT LEVEL INTERNAL ARBITRATI0N Bus Operation VECTOR# ...
Page 138
... State 0 – The address, function codes, read/write, and size pins change to begin the next cycle. Data from the preceding cycle is valid through state 0. 4-62 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
Page 139
... Resetting the QUICC causes any bus cycle in progress to terminate as if DSACKx or BERR had been asserted. In addition, the QUICC appropriately initializes registers for a reset exception. For More Information On This Product S41 S42 S43 S1 S2 SHOW CYCLE START OF EXTERNAL CYCLE MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation ...
Page 140
... INTRST EBI Asynchronous INTRST Asynchronous INTRST Asynchronous INTRST Clock Asynchronous INTRST 2 Asynchronous INTRST 512 CYCLES 32 CLKS NOTE MC68360 USER’S MANUAL Go to: www.freescale.com INTSYSRST CLKRST EXTSYSRST — — EXTRST INTSYSRST CLKRST EXTSYSRST INTSYSRST — EXTSYSRST INTSYSRST CLKRST EXTSYSRST INTSYSRST CLKRST EXTSYSRST — ...
Page 141
... In QUICC slave mode (disable CPU32+) the reset operates the same as in the normal (mas- ter) mode except that the RESET instruction does not exist. For More Information On This Product, 512 14 CLOCKS CLKOUT ADDRESS AND CONTROL SIGNALS THREE-STATED NOTE MC68360 USER’S MANUAL Go to: www.freescale.com Bus Operation ...
Page 142
... QUICC drives RESETS pin. In that case RESETS will be driven from CLOCK low (not CLOCK high as in all other cases). This requires a special AC timing parameter which is spec 58A in 10.9 Bus Operation AC Timing Specifications. 4-66 For More Information On This Product, NOTE MC68360 USER’S MANUAL Go to: www.freescale.com ...
Page 143
... PC relative data addresses), some performance degradation occurs when additional bus cycles are required for long-word or word operands that are misaligned. For maximum performance, data items should be For More Information On This Product, Thi d MC68360 USER’S MANUAL Go to: www.freescale.com ith ...
Page 144
... Register Indirect with Base Displacement and Index —Expanded PC Relative Modes —32-Bit Branch Displacements • Instruction Set Additions —High-Precision Multiply and Divide —Trap on Condition Codes —Upper and Lower Bounds Checking 5-2 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
Page 145
... The CPU32+ automatically exits the loop mode during interrupts or other exceptions. For More Information On This Product, INSTRUCTION PREFETCH AND DECODE BUS CONTROL MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ BUS CONTROL ...
Page 146
... To support generic handlers, the processor places the vector offset in the exception stack frame. The processor also marks the frame with a frame format. The format 5-4 For More Information On This Product, ONE-WORD INSTRUCTION DBcc DBcc DISPLACEMENT $FFFC = 4 VECTOR BASE REGISTER (VBR) MC68360 USER’S MANUAL Go to: www.freescale.com 0 ...
Page 147
... Separate User and Supervisor Address Spaces • Separate Program and Data Address Spaces • Many Data Types • Flexible Addressing Modes • Full Interrupt Processing • Expansion Capability For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ ...
Page 148
... SSP and USP, a 16-bit SR, two alternate function code registers, and a 32- bit VBR (see Figure 5-3 and Figure 5-4 Figure 5-3. User Programming Model 5-6 For More Information On This Product (USP CCR MC68360 USER’S MANUAL Go to: www.freescale.com DATA REGISTERS ADDRESS REGISTERS USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER ...
Page 149
... The MOVEC instruction can use registers SFC and DFC to specify the function code of a memory address. For More Information On This Product (SSP (CCR VBR SFC DFC MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ SUPERVISOR STACK POINTER STATUS REGISTER VECTOR BASE REGISTER ALTERNATE FUNCTION CODE REGISTERS ...
Page 150
... However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 core enhancements. 5-8 For More Information On This Product, (CONDITION CODE REGISTER INTERRUPT PRIORITY MASK Figure 5-5. Status Register MC68360 USER’S MANUAL Go to: www.freescale.com USER BYTE EXTEND NEGATIVE ZERO OVERFLOW CARRY ...
Page 151
... Swap Data Register Halves TAS Test and Set Operand TBLS, TBLSN Table Lookup and Interpolate, TBLU, TBLUN Table Lookup and Interpolate, TRAPcc Trap Conditionally (16 Tests) TRAPV Trap on Overflow TST Test UNLK Unlink MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ Description Signed Unsigned ...
Page 152
... These words may be imme- diate operands, extensions to the effective address mode specified in the operation word, branch displacements, bit number, special register specifications, trap operands, or argu- ment counts. 5-10 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
Page 153
... For More Information On This Product, A register field of the instruction contains the num- ber of the register. An effective address field of the instruction con- tains address mode information. The definition of an instruction implies the use of specific registers. MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ 0 ...
Page 154
... User stack pointer FC Function code DFC Destination function code register SFC Source function code register Arithmetic addition or postincrement – Arithmetic subtraction or predecrement / Arithmetic division or conjunction symbol Arithmetic multiplication = Equal to 5-12 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
Page 155
... Shift and Rotate System Control The complete range of instruction capabilities combined with the addressing modes de- scribed previously provide flexibility for program development. All CPU32+ instructions are summarized in Table 5-2. For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ ...
Page 156
... BCLR # data ea –(SSP) BGND BKPT # data BRA label Z; BSET Dn, eaÒ BSET # data ea (SP BSR label BTST Dn BTST # data ea CHK ea ,Dn CHK2 ea ,Rn CLR ea cc CMP ea ,Dn CMPA ea ,An CMPI # data ea cc CMPM (Ay)+,(Ax)+ MC68360 USER’S MANUAL Go to: www.freescale.com Syntax ...
Page 157
... LINK An,# displacement SP SR LPSTOP # data 1 LSd 1 Destination LSd 1 LSd MOVE ea ea MOVEA ea ,An MOVE CCR, ea MOVE ea ,CCR MOVE SR, ea MOVE ea ,SR MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ Syntax 16r:16q 32q 32r:32q 32r:32q 16r:16q 32q 32r:32q 32r:32q Dx,Dy # data ,Dy ea ...
Page 158
... NOP NOT ,Dn Destination OR Dn, ea Destination ORI # data , ea CCR ORI # data ,CCR SR ORI # data ,SR (SP) PEA ea RESET ROd 1 Rx,Dy ROd 1 # data ,Dy Destination ROd 1 ea ROXd 1 Rx,Dy ROXd 1 # data ,Dy Destination ROXd RTD # displacement SP; (SP) PC; RTE SP; RTR SP MC68360 USER’S MANUAL Go to: www.freescale.com Syntax ...
Page 159
... TBLSN. size Dym:Dyn, Dx TBLU. size ea ,Dx TBLU. size Dym:Dyn, Dx TBLUN. size ea ,Dx TBLUN. size Dym:Dyn,Dx (SSP); (SSP); SSP – 2 SSP; TRAP # vector PC TRAPcc TRAPcc.W # data TRAPcc.L TRAPV Condition Codes TST ea An UNLK An MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ Syntax data ...
Page 160
... ROR ( — 5-18 For More Information On This Product Decimal Carry LB (LB < UB) UB < LB Division Overflow * * ? Multiplication Overflow C = Decimal Borrow (Dm – ... V Dm – (Dm – – – – – MC68360 USER’S MANUAL Go to: www.freescale.com Special Definition (IR < LB > UB > UB) (R < LB – ...
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... SP – 16, 32 Source Destination 16 Source Destination 16, 32 Listed registers Destination 16 Source Listed registers Dn [31:24] (An + d); Dn [23:16] Dn [15:8] ( 4); Dn [7:0] 16 [31:24 [15:8]; ( Immediate Data Destination 32 SP – SP; (SP) An MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ Operation (SP 2); ( [23:16]; Dn [7: ...
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... A set of extended instructions provides multiprecision and mixed-size arithmetic. These instructions are add extended (ADDX), subtract extended (SUBX), sign extend (EXT), and negate binary with extend (NEGX). Refer to Table 5-5 for a summary of the integer arith- metic operations. 5-20 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... Dn [7:0]) Temp (Dym 256) + Temp Dyn – Dym Temp 8, 16, 32 (Temp Dn [7:0]) / 256 Dym + Temp Dn MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ Destination Destination Destination Destination Destination Destination (signed or un- Destination Destination Destination (signed or un- Destination Destination Destination Destination ...
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... Immediate Data 8, 16, 32 Source Destination 8, 16, 32 Immediate Data 8, 16, 32 Destination Destination 8, 16, 32 Source V Destination 8, 16 16, 32 Immediate Data V Destination 8, 16, 32 Source – set condition codes MC68360 USER’S MANUAL Go to: www.freescale.com Operation Destination Destination Destination Destination Destination Destination Destination Destination ...
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... Register operands are 32 bits, and memory operands are 8 bits. Table 5 summary of bit manipulation instructions. For More Information On This Product, Operand Size Operation X 16 MSW MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ 0 X LSW ...
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... Operand Size Operation 8 Source 10 + Destination – Destination 10 – Destination 10 – Source 10 – MC68360 USER’S MANUAL Go to: www.freescale.com Z bit bit bit of Z instructions support Destination Destination Destination ...
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... SP – 4 SP; PC (SP); destination none Returns 16 (SP) PC none (SP) CCR none (SP) PC — LT — MI — NE — PL — T — VC — VS — MC68360 USER’S MANUAL Go to: www.freescale.com CPU32 SP; (SP) PC Low or same Less than Minus Not equal Plus True Overflow clear Overflow set ...
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... If V set, then overflow TRAP exception Condition Code Register 8 Immediate Data CCR 8 Immediate Data CCR 16 Source CCR 16 CCR Destination 8 Immediate Data V CCR MC68360 USER’S MANUAL Go to: www.freescale.com SP; (SP) PC SP; EBI; STOP – (SSP); – (SSP); (vector) PC (SSP); (SSP); (SSP); PC (SSP); ...
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... Carry Clear 0100 Carry Set 0101 Not Equal 0110 Equal 0111 Overflow Clear 1000 Overflow Set 1001 Plus 1010 Minus 1011 Greater or Equal 1100 Less Than 1101 Greater Than 1110 Less or Equal 1111 MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ Test ...
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... Y = 1669 + (128 (1679 – 1669)) / 256 = 1674 5-28 For More Information On This Product, X-Value Y-Value 32768 1311 41472 1659 41728 1669 41984 1679 42240 1690 49152 1966 32768 49152 X INDEPENDENT VARIABLE Figure 5-7. Table Example MC68360 USER’S MANUAL Go to: www.freescale.com X 49152. Table 65536 ...
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... In this case the scaling factor is 64, and the scaling is done by a single instruc- tion: LSR.W #6,Dx For More Information On This Product, 512 786 X INDEPENDENT VARIABLE Figure 5-8. Table Example 2 NOTE X-Value Y-Value 512 1311 786 1966 MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ 1024 ...
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... The subroutine uses the data listed in Table 5-15, based on the function shown in Figure 5-9. Y 1024 5-30 For More Information On This Product 2048 3072 X INDEPENDENT VARIABLE Figure 5-9. Table Example 3 MC68360 USER’S MANUAL Go to: www.freescale.com example shows 4096 ...
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... For More Information On This Product (Instruction 256 16 2 512 32 3 768 48 4 1024 64 5 1280 80 6 1536 96 7 1792 112 8 2048 128 9 2304 112 10 2560 96 11 2816 80 12 3072 64 13 3328 48 14 3584 32 15 3840 16 16 4096 MC68360 USER’S MANUAL Go to: www.freescale.com CPU32 ...
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... For More Information On This Product 0010 0000 . 0111 0000 0011 1111 . 0111 0000 0000 0001 . 0111 0000 TBL # 1 0010 0000 . TBL # 2 0011 1111 . TBL # 3 0000 0001 . 0010 0000 . 0011 1111 . 0000 0001 . 0110 0000 . MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... Copy entry number and fraction number Surface interpolation, with round Read just the result No round necessary Half round up MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ ...
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... Privilege Levels To protect system resources, the processor can operate with either of two levels of access— user or supervisor. Supervisor level is more privileged than user level. All instructions are 5-34 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... The RTE instruction causes a return to a program that was executing when an exception occurred. When RTE is executed, the exception stack frame saved on the supervisor stack can be restored in either of two ways. For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ ...
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... Sources of external exception include interrupts, breakpoints, bus errors, and reset requests. Interrupts are peripheral device requests for processor action. Breakpoints are used to support development equipment. Bus error and reset are used for access control and processor restart. 5-36 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... Because there is no protection on the 64 processor-defined vec- tors, external devices can access vectors reserved for internal purposes. This practice is strongly discouraged. MC68360 USER’S MANUAL For More Information On This Product, Go to: www.freescale.com Space Assignment SP Reset: Initial Stack Pointer SP Reset: Initial Program Counter ...
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... Stack Frames for a complete discussion of exception stack frames FORMAT Figure 5-10. Exception Stack Frame 5-38 For More Information On This Product, STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW VECTOR OFFSET OTHER PROCESSOR STATE INFORMATION, DEPENDING ON EXCEPTION ( WORDS) MC68360 USER’S MANUAL Go to: www.freescale.com 0 ...
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... Suspends processing (instruction or excep- tion); saves internal context. Exception processing is a part of instruction execution. Exception processing begins before instruc- tion execution. Exception processing begins when current in- struction or previous exception processing is complete. MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ ...
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... Direct assertion of the internal BERR signal by the on-chip hardware watchdog after detecting a no-response condition Bus error exception processing begins when the processor attempts to use information from an aborted bus cycle. 5-40 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... For More Information On This Product, ENTRY T0,T1 I2:IO VBR BUS ERROR SP BUS ERROR PC BUS ERROR/ ADDRESS ERROR (DOUBLE BUS FAULT) ASSERT HALT EXIT EXIT MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ ...
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... For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... If the format of the control data is improper, the processor generates a format error excep- tion. This exception saves a four-word format exception frame and then vectors through vec- For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ ...
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... An attempt to execute one of these instructions at the user level will cause an exception. The privileged exceptions are as follows: • AND Immediate to SR • EOR Immediate to SR • LPSTOP • MOVE from SR 5-44 For More Information On This Product, 0000. MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... If the instruction is not executed, either because an inter- rupt is taken or because the instruction is illegal, unimplemented, or privileged, an exception is not generated. For More Information On This Product, Table 5-18. Tracing Control T0 Tracing Function 0 No tracing 1 Trace on change of flow 0 Trace on instruction execution 1 Undefined; reserved MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ ...
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... INTERRUPTS. There are seven levels of interrupt priority and 192 assignable interrupt vectors within each exception vector table. Careful use of multiple vector tables and hardware chaining will permit a virtually unlimited number of peripherals to interrupt the pro- cessor. 5-46 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... RETURN FROM EXCEPTION. When exception stacking operations for all pend- ing exceptions are complete, the processor begins execution of the handler for the last exception processed. After the exception handler has executed, the processor must restore For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ ...
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... The stack contents are identified by the special status word (SSW). In addition to identifying the fault type represented by the stack frame, the SSW contains the internal processor state corresponding to the fault SZC1 TR B1 5-48 For More Information On This Product SZC0 MC68360 USER’S MANUAL Go to: www.freescale.com $14 in the stack frame. The SIZ FUNC ...
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... B0 indicates that a breakpoint exception was pending on channel 0 (internal breakpoint source) when the bus error exception was processed. Pending breakpoint status is stacked, regardless of the type of bus error exception Breakpoint not pending 1 = Breakpoint pending For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ ...
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... FC2–FC0 for the faulted bus cycle. This field is reloaded into the bus controller if the RR bit is set during unstacking. All unused bits are stacked as zeros and are ignored during unstacking. Further discussion of the SSW is included in 5.5.3.1 Types of Faults. 5-50 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... The trace pending bit is always cleared since the instruction will be restarted upon return from the handler. Saving a pending exception on the stack causes a trace exception to be For More Information On This Product SZC0 SZC0 MC68360 USER’S MANUAL Go to: www.freescale.com CPU32 SIZ FUNC SIZ FUNC ...
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... However, if the exception is one that causes a four- or six-word stack frame to be written, a bus cycle fault frame is written below the faulted exception stack frame. 5-52 For More Information On This Product SZC0 MC68360 USER’S MANUAL Go to: www.freescale.com SIZ FUNC ...
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... RW, FUNC, and SIZ fields are restored and the released write cycle is rerun. To maintain long-word operand coherence, stack contents must be adjusted prior to the RTE execution. The fault address must be decremented the SZCx bits are set to long For More Information On This Product SZC0 MC68360 USER’S MANUAL Go to: www.freescale.com CPU32 SIZ FUNC ...
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... set in the stacked SSW, create a six-word stack frame and execute the trace handler. If either set in the SSW, create another six-word stack frame and execute the hardware breakpoint handler. 5-54 For More Information On This Product, MC68360 USER’S MANUAL Go to: www.freescale.com ...
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... Once the exception handler determines that the fault has been corrected, recovery can pro- ceed as described previously. If the fault cannot be corrected, move the supervisor stack to another area of memory, copy all valid stack frames to the new stack, create a faulted For More Information On This Product, $10). The return PC value is MC68360 USER’S MANUAL Go to: www.freescale.com CPU32+ ...
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... For More Information On This Product, STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW 0 VECTOR OFFSET STATUS REGISTER NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW 0 VECTOR OFFSET FAULTED INSTRUCTION PROGRAM COUNTER HIGH FAULTED INSTRUCTION PROGRAM COUNTER LOW MC68360 USER’S MANUAL Go to: www.freescale.com 0 0 ...
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... SSW is located at SP The fault address of a dynamically sized bus cycle is the address of the upper byte, regard- less of the byte that caused the error. For More Information On This Product SZC0 8 7 $12.) MC68360 USER’S MANUAL Go to: www.freescale.com CPU32 SIZ FUNC 0 TRANSFER COUNT ...
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... SPECIAL STATUS WORD STATUS REGISTER NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW 0 VECTOR OFFSET FAULTED ADDRESS HIGH FAULTED ADDRESS LOW PRE-EXCEPTION STATUS REGISTER FAULTED EXCEPTION FORMAT/VECTOR WORD INTERNAL TRANSFER COUNT REGISTER SPECIAL STATUS WORD MC68360 USER’S MANUAL Go to: www.freescale.com ...