MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 346

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Timers
ICLK—Input Clock Source for the Timer
GE—Gate Enable
7.5.2.4 TIMER REFERENCE REGISTERS (TRR1, TRR2, TRR3, TRR4). Each TRR is a
16-bit, memory-mapped, read-write register containing the reference value for the timeout.
TRR1–TRR4 are set to all ones by reset. The reference value is not reached until TCN incre-
ments to equal TRR.
7.5.2.5 TIMER CAPTURE REGISTERS (TCR1, TCR2, TCR3, TCR4). Each TCR is a 16-
bit register used to latch the value of the counter. TCR1–TCR4 appear as memory- mapped,
read-only registers to the user. TCR1–TCR4 are cleared by reset.
7.5.2.6 TIMER COUNTER (TCN1, TCN2, TCN3, TCN4). Each TCN is a 16-bit, memory-
mapped, read-write up-counter. A read cycle to TCN1–TCN4 yields the current value of the
timer, but does not affect the counting operation. A write cycle to TCN1–TCN4 sets the reg-
ister to the written value, causing its corresponding prescaler to be reset.
7.5.2.7 TIMER EVENT REGISTERS (TER1, TER2, TER3, TER4). Each TER is a 16-bit
register used to report events recognized by any of the timers. On recognition of an output
reference event, the timer sets the REF bit in the TER, regardless of the corresponding ORI
in the TMR. The capture event will be set only if enabled by the CE bits in the TMR. TER1–
TER4, which appear to the user as memory-mapped registers, may be read at any time.
A bit is reset by writing a one to that bit (writing a zero does not affect a bit’s value). More
than one bit may be reset at a time. Both bits must be reset before the timer will negate the
interrupt to the CPM interrupt controller. This register is cleared by reset.
Bits 15–2—Reserved
7-22
15
00 = Internally cascaded input.
01 = Internal general system clock.
10 = Internal general system clock divided by 16.
11 = Corresponding TIN pin: TIN1, TIN2, TIN3, or TIN4 (falling edge).
0 = The TGATE signal is ignored.
1 = The TGATE signal is used to control the timer.
14
For TMR1, the timer 1 input is the output of timer 2.
For TMR3, the timer 3 input is the output of timer 4.
For TMR2 and TMR4, this selection means no input clock is provided to the timer.
13
Write operation to this register while the timer is not running may
not update the register correctry. User should always use timer
refrence register to define desired count value.
12
11
Freescale Semiconductor, Inc.
For More Information On This Product,
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
9
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NOTE
8
7
6
5
4
3
2
REF
1
CAP
0