MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 731

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

BCLROID2–BCLROID0 to $3 and program the SDMA, IDMA1, and IDMA2 arbitration IDs
in the SDMA configuration register and IDMA channel configuration registers to 4, 2, and 0,
respectively, to allow the SDMA and DRAM refresh to preempt IDMA transfers. SHEN1–
SHEN0 should be left cleared. SUPV should be cleared. BCLRIID2–BCLRIID0 are not used
and can be programmed to $0. IARB3–IARB0 can be left programmed to $F to allow SIM
interrupts to have priority over CPM interrupts that occur at the same level.
The software watchdog interrupt vector register (SWIV) should be set as desired.
In the system protection control register (SYPCR), DBFE and BME should normally be set.
If the software watchdog is not used, the SWE bit should be cleared.
The periodic interrupt control register (PICR) may be set as desired.
The breakpoint address register (BKAR) and breakpoint control register (BKCR) should be
set as desired.
The port E pin assignment register (PEPAR) should be set to $0180. This configures the
RAS1DD pin, the WEx lines instead of A31–A28 lines, the four CASx lines, CS7, and AVEC.
9.1.3.2 CONFIGURING THE MEMORY CONTROLLER. The
describe configuring the memory controller registers.
The global memory register (GMR) should be configured as follows:
The RFCNT bits may be set as desired. At 25 MHz, an RFCNT value of 24 (decimal) gives
one refresh every 15.6 s.
RFEN should be set.
RCYC depends on the DRAM speed. At 25 MHz (an 80-ns DRAM SIMM), RCYC should
be 01.
PGS2–PGS0 should be set to 1M for the DRAM SIMM or to 256K for the 256K 16 DRAM
devices.
DPS should be set to 00.
WBT40 is not used and should be cleared.
WBTQ depends on timing; it should be set for 80-ns DRAM SIMMs.
DWQ depends on timing.
DW40 is not used and should be cleared.
EMWS is not used in this design since there is only one QUICC or MC68030-type bus
master. It should be cleared.
SYNC is not used in this design since there is only one QUICC or MC68030-type bus
master. It should be cleared.
OPAR may be chosen by the user.
PBEE should be set to cause parity errors to generate bus errors.
TSS40 is not used and should be cleared.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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