MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 118

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Bus Operation
EXAMPLE A: A system uses a bus monitor timer to terminate accesses to an unpopulated
address space. The timer asserts BERR after timeout (case 3).
EXAMPLE B: A system uses error detection and correction on RAM contents. The designer
may:
4.5.1 Bus Errors
BERR can be used to abort the bus cycle and the instruction being executed. BERR takes
precedence over DSACKx provided it meets the timing constraints described in Section 10
Electrical Characteristics. If BERR does not meet these constraints, it may cause unpredict-
4-42
1. Delay DSACKx until data is verified and assert BERR and HALT simultaneously to in-
2. Delay DSACKx until data is verified and assert BERR with or without DSACKx if data
3. Return DSACKx prior to data verification; if data is invalid, BERR is asserted on the
4. Return DSACKx prior to data verification; if data is invalid, assert BERR and HALT on
NOTES:
N —The number of current even bus state (e.g., S2, S4, etc.)
A —Signal is asserted in this bus state
NA —Signal is not asserted in this state
X —Don't care
S —Signal was asserted in previous state and remains asserted in this state
Case
Num
dicate to the QUICC to automatically retry the error cycle (case 5), or, if data is valid,
assert DSACKx (case 1).
is in error (case 3). This initiates exception processing for software handling of the con-
dition.
next clock cycle (case 4). This initiates exception processing for software handling of
the condition.
the next clock cycle (case 6). The memory controller can then correct the RAM prior
to or during the automatic retry.
2
3
4
5
6
1
DSACKx
DSACKx
DSACKx
DSACKx
DSACKx
DSACKx
Control
Signal
BERR
BERR
BERR
BERR
BERR
BERR
HALT
HALT
HALT
HALT
HALT
HALT
Table 4-8. DSACKx, BERR, and HALT Assertion Results
Asserted on Rising
NA/A
NA/A
A/S
A/S
NA
NA
NA
NA
NA
NA
NA
NA
Edge of State
N
A
A
A
A
A
A
Freescale Semiconductor, Inc.
For More Information On This Product,
N + 2
NA
NA
NA
NA
S
X
S
S
X
S
X
A
X
S
S
X
A
A
MC68360 USER’S MANUAL
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Normal cycle terminate and continue.
Normal cycle terminate and halt; continue when HALT negated.
Terminate and take bus error exception, possibly deferred.
Terminate and take bus error exception, possibly deferred.
Terminate and retry when HALT negated.
Terminate and retry when HALT negated.
Result