MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 425

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

choose its clock from a pre-defined pin or baud rate generator, which allows flexibility in the
pinout mapping strategy. Second, if a group of SCC receivers and transmitters need the
same clock rate, they can share the same pin. This configuration leaves additional pins for
other functions and minimizes potential skew between multiple clock sources.
The four baud rate generators also make their clocks available to external logic, regardless
of whether the baud rate generators are being used by an SCC or SMC. Note that the
BRGOx pins are multiplexed with other functions; therefore, all BRGOx pins may not always
be available. Note that BRGO3 has the flexibility to be output on both port A 12 and port B
16. See the pinout description in Section 11 Ordering Information and Mechanical Data for
more details.
There are a few restrictions in the bank-of-clocks mapping. First, only eight of the twelve
sources can be connected to any given SCC receiver or transmitter. Second the SMC trans-
mitter must have the same clock source as the receiver when connected to the NMSI pins.
Once the clock source is selected, the clock is given an internal name. For the SCCs, the
name is RCLKx and TCLKx. For the SMCs, the name is simply SMCLKx. These internal
names are used only in NMSI mode to specify the clock that is sent to the SCC or SMC.
These names do not correspond to any pins on the QUICC.
The exact pins available to each SCC and SMC in the NMSI mode are summarized in Figure
7-35.
The SCC1 in NMSI mode has its own set of modem control pins:
The SCC2 in NMSI mode has its own set of modem control pins:
TXD1
RXD1
TCLK1 <- BRG1–BRG4, CLK1–CLK4
RCLK1 <- BRG1–BRG4, CLK1–CLK4
RTS1
CTS1
CD1
TXD2
RXD2
TCLK2 <- BRG1–BRG4, CLK1–CLK4
RCLK2 <- BRG1–BRG4, CLK1–CLK4
RTS2
The internal RCLKx and TCLKx may be used as inputs to the
DPLL unit, which is inside the SCC. Thus, the RCLKx and
TCLKx signals are not required to always reflect the actual bit
rate on the line.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Serial Interface with Time Slot Assigner