MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 53

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

2.1.2 Function Codes (FC3–FC0)
These three-state bidirectional signals identify the processor state and the address space
of the current bus cycle as noted in Table 2-2. The function code pins provide the purpose
of each bus cycle to external logic.
Other bus masters besides the QUICC may also output function codes during their bus
cycles. On the QUICC, this capability is provided for each potential internal bus master (i.e.,
the IDMA, SDMA, and DRAM refresh units). Provision is also made for the decoding of func-
tion codes that are output from external bus masters (e.g., in the memory controller chip-
select generation logic).
In computer design, function code information can be used to protect certain portions of the
address map from unauthorized access or to extend the addressable range beyond the
address limit. However, in controller applications, function codes are most often used as a
debugging aid. Furthermore, in most controller applications, the QUICC stays continuously
in the supervisor state.
Refer to Section 4 Bus Operation for more information.
2.1.3 Data Bus
The data bus consists of the following two groups. Refer to Section 4 Bus Operation for infor-
mation on the data bus and its relationship to bus operation.
2.1.3.1 DATA BUS (D31–D16). These three-state bidirectional signals (along with D15–
D0) provide the general-purpose data path between the QUICC and all other devices.
Although the data path is a maximum of 32 bits wide, it can be dynamically sized to support
8-, 16-, or 32-bit transfers. D31 is the MSB of the data bus. Byte and word operations occur
on D31–D16. Additionally, if the QUICC is configured into 16-bit bus mode, the D31–D16
FC3-0 may not be set to 0xF
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 2-2. Address Space Encoding
Function Code Bits
3
0
0
0
0
0
0
0
0
1
2
0
0
0
0
1
1
1
1
x
MC68360 USER’S MANUAL
Go to: www.freescale.com
1
0
0
1
1
0
0
1
1
x
0
0
1
0
1
0
1
0
1
x
NOTE
Reserved (Motorola)
User Data Space
User Program Space
Reserved (User)
Reserved (Motorola)
Supervisor Data Space
Supervisor Program Space
Supervisor CPU Space
DMA Space
Address Space
Signal Descriptions