MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 723

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
Applications
9.1.1.2 CLOCKING STRATEGY. In this application, the system clock is generated from a
32.768-kHz crystal into the QUICC. The QUICC's internal phase-locked loop (PLL) then
multiplies the frequency up to 25 MHz, and outputs 25 MHz on CLKO1 and 50 MHz on
CLKO2. Neither CLKO pin is required for the application. It is recommended that the CLKO
outputs be disabled in software to save power.
The use of a 32.768-kHz crystal is not a requirement in the application. A 4-MHz crystal or
a 25-MHz external oscillator could have been used, if desired.
The QUICC clocking section allows for the clock oscillator to be kept running through the
VDDSYN pin in a power-down situation. This section does not address low-power issues,
however.
9.1.1.3 RESETTING THE QUICC. If a QUICC is configured to provide the global chip
select, it will also provide an internal power-on reset generation. Thus, the reset support
function is very simple. If a pushbutton switch is needed, it can be connected by an open-
drain buffer to the hard reset (RESETH) pin, once debounced. The soft reset (RESETS) pin
is not used in this design except to indicate that an internal QUICC soft reset is in progress.
9.1.1.4 INTERRUPTS. External interrupts may be brought into the QUICC through either
the IRQx pins or parallel I/O pins. This design shows no external interrupts (the IRQ7–IRQ1
pins are pulled high), but this could be easily changed if desired. Without any external inter-
rupts requiring autovector capability, the AVEC pin is also pulled high.
Internal interrupts from the QUICC may be generated in the SIM60 or the CPM. No addi-
tional hardware is required.
9.1.1.5 BUS ARBITRATION. This design assumes that no alternate bus masters exist in
the system. Thus, BR is pulled high, and BGACK is not connected, but pulled high since it
is an open-drain signal.
9.1.1.6 BREAKPOINT GENERATION. The QUICC can be used to generate a hardware
breakpoint signal. The result of a breakpoint (either internally generated using the break-
point address register or externally generated using the BKPT pin) is a CPU32+ breakpoint
cycle. In this application, the BKPT pin is tied high and is not used.
9.1.1.7 BUS MONITOR FUNCTION. The QUICC can be programmed to monitor the bus for
bus cycles that are not properly terminated. If AS is asserted but not negated, the cycle will
terminate with the BERR pin being asserted.
9.1.1.8 SPURIOUS INTERRUPT MONITOR. The QUICC will watch for spurious interrupt
cycles on the levels that it supports internally. If such a condition occurs, BERR will be
asserted by the QUICC.
9.1.1.9 SOFTWARE WATCHDOG. If desired, the QUICC software watchdog can be used
to generate a level 7 interrupt or a system reset. In this application, the software watchdog
is configured in software to generate a reset. No additional hardware is required.
MC68360 USER’S MANUAL
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