MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 622

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Serial Management Controllers (SMCs)
7.11.10.9 SMC TRANSPARENT ERROR-HANDLING PROCEDURE. The SMC reports
message reception and transmission error conditions using the channel BDs and the SMC
event register.
7.11.10.9.1 Transmission Error (Underrun). When this error occurs, the channel termi-
nates buffer transmission, closes the buffer, sets the UN bit in the BD, and generates the
TXE interrupt if it is enabled. The channel resumes transmission after the reception of the
RESTART TRANSMIT command. Underrun cannot occur between frames.
7.11.10.9.2 Reception Error (Overrun). The SMC maintains an internal FIFO for receiving
data (shift register plus data register). The CP begins programming the SDMA channel (if
the data buffer is in external memory) when the first character is received into the FIFO. If a
FIFO overrun occurs, the SMC writes the received data character to the internal FIFO over
the previously received character. The previous character and its status bits are lost. Fol-
lowing this, the channel closes the buffer, sets the OV bit in the BD, and generates the RX
interrupt if it is enabled. Reception then continues normally.
7.11.10.10 SMC TRANSPARENT MODE REGISTER (SMCMR). The operating mode of
an SMC is defined by the SMCMR. The SMCMR is a 16-bit, memory-mapped, read-write
register. The register is cleared at reset. The function of bits 7–0 is common to each SMC
protocol. The function of bits 15–8 varies according to the protocol selected by the SM bits.
Bits 15, 10, 9, 7, 6—Reserved
CLEN—Character Length
REVD—Reverse Data
7-298
15
—
CLEN is programmed with a value from 3 to 15 to obtain 4 to 16 bits per character. If the
character length is less than 8 bits, the MSBs of the byte in buffer memory are not used
on transmit and are written with zeros on receive. If the character length is more than 8
bits, but less than 16 bits, the MSBs of the word in buffer memory will not be used on trans-
mit and will be written with zeros on receive.
0 = Normal mode
1 = Reverse the character bit order; the MSB is transmitted first.
14
13
The values 0 to 2 should not be written to CLEN, or erratic be-
havior may result.
Larger character lengths increase the potential performance of
the SMC channel and lower the performance impact on other
channels. For instance, the use of 16-bit characters, rather than
8-bit characters, is encouraged if 16-bit characters are accept-
able in the end application.
CLEN
12
11
Freescale Semiconductor, Inc.
For More Information On This Product,
10
MC68360 USER’S MANUAL
—
Go to: www.freescale.com
9
REVD
NOTES
8
7
—
6
5
SM
4
3
DM
2
TEN
1
REN
0