MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 159

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

5.3.3.1 CONDITION CODE REGISTER. The CCR portion of the SR contains five bits that
indicate the result of a processor operation. Table 5-2 lists the effect of each instruction on
these bits. The carry bit and the multiprecision extend bit are separate in the M68000 Family
to simplify programming techniques that use them. Refer to Table 5-3 as an example.
NOTE 1: d is direction, L or R.
Opcode
TRAPcc
TRAPV
TBLSN
TBLUN
SWAP
SBCD
SUBQ
STOP
SUBA
SUBX
TRAP
UNLK
TBLS
TBLU
SUBI
RTS
SUB
TAS
TST
Scc
(SP)
Destination 10 – Source 10 – X
If Condition True
else 0s
If supervisor state
else TRAP
Destination – Source
Destination – Source
Destination – Immediate Data
Destination – Immediate Data
Destination – Source – X
Register [31:16]
Destination Tested
1
ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n))
256
ENTRY(n)
[7:0]}
ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n)) Dx[7:0]} /
256
ENTRY(n)
Dx[7:0]}
SSP – 2
SSP – 4
SR
If cc then TRAP
If V then TRAP
Destination Tested
An
then 1s
then Immediate Data
Table 5-2. Instruction Set Summary (Concluded)
bit 7 of Destination
SP; (SP)
(SSP); Vector Address
Dx
Dx
PC; SP + 4
Dx
Freescale Semiconductor, Inc.
Destination
SSP; Format/Offset
SSP; PC
Dx
For More Information On This Product,
Destination
256 + {(ENTRY(n + 1) – ENTRY(n)) Dx
256 + {(ENTRY(n + 1) – ENTRY(n))
An; SP + 4
Register [15:0]
Operation
MC68360 USER’S MANUAL
Condition Codes;
Go to: www.freescale.com
Condition Codes
SP
(SSP); SSP – 2
Destination
Destination
SR; STOP
Destination
PC
Destination
Destination
Destination
SP
(SSP);
SSP;
D
x[7:0]} /
RTS
SBCD Dx,Dy
SBCD –(Ax),–(Ay)
Scc ea
STOP # data
SUB ea ,Dn
SUB Dn, ea
SUBA ea ,An
SUBI # data , ea
SUBQ # data , ea
SUBX Dx,Dy
SUBX –(Ax),–(Ay)
SWAP Dn
TAS ea
TBLS. size ea , Dx
TBLS. size Dym:Dyn, Dx
TBLSN. size ea ,Dx
TBLSN. size Dym:Dyn, Dx
TBLU. size ea ,Dx
TBLU. size Dym:Dyn, Dx
TBLUN. size ea ,Dx
TBLUN. size Dym:Dyn,Dx
TRAP # vector
TRAPcc
TRAPcc.W # data
TRAPcc.L
TRAPV
TST ea
UNLK An
data
Syntax
CPU32+