MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 95

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

4.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment
The combination of operand size, operand alignment, and port size determines the number
of bus cycles required to perform a particular memory access. Table 4-7 lists the number of
bus cycles required for different operand sizes to different port sizes with all possible align-
ment conditions for write cycles and read cycles.
Figure 4-13. Misaligned Long-Word Transfer to Long-Word Port Timing
FC2–FC0
D23–D16
D31–D24
DSACK1
DSACK0
D15–D8
A31–A2
CLKO1
D7–D0
SIZ1
SIZ0
R/W
A0
AS
DS
A1
Freescale Semiconductor, Inc.
For More Information On This Product,
S0
MC68360 USER’S MANUAL
Go to: www.freescale.com
BYTE WRITE
S2
LONG-WORD OPERAND WRITE
S4
0P0
0P0
0P1
0P0
S0
3-BYTE WRITE
S2
0P1
0P2
0P3
0P1
S4
Bus Operation