MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 685

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

SCC1
PA4 can be configured as a general-purpose I/O pin, and as an open-drain pin. It may also
be the RXD3 pin for SCC3 in the NMSI mode if the PADIR bit is a zero. It may also be the
L1TXDB pin for TDMb if the PADIR bit is a one. If PA4 is configured as a general-purpose
I/O pin, then the RXD3 input is not defined. If SCC3 is connected to a TDM or is not used,
then PA4 may be used as general-purpose I/O.
PA8 can be configured as a general-purpose I/O pin, but not an open-drain pin. If the corre-
sponding PADIR bit is a zero, it may also be the CLK1 pin (part of the bank of clocks in the
SI), the TIN1 pin (input to timer 1), or the L1RCLKA pin (receive clock to TDMa) or all three
at once. There is no selection between these three inputs in port A, because the connections
are made separately in the SI and the timer mode registers. If the PADIR bit is a one, this
pin may also be the BRGO1 pin (output from BRG1). If the PA8 pin is a general-purpose I/
O pin, then the input to the on-chip peripheral (CLK1, TIN1, or L1RCLKa) is internally con-
nected to BRGO1. See 7.8 Serial Interface with Time Slot Assigner for more details on the
use of the CLK1 and L1RCLKA pins.
PA11 can be configured as a general-purpose I/O pin, but not an open-drain pin. If the
PADIR bit is a zero, PA11 may also be the CLK4 pin (part of the bank of clocks). If the PADIR
bit is a one, PA11 may also be the TOUT2 pin (output from timer 2). If the PA11 pin is a
general-purpose I/O pin, then the input to the on-chip CLK4 function is the value supplied
on the CLK8 pin. This interesting option is useful because not all CLK pins can be routed to
all serial channels in all situations. The ability to send a clock from CLK8 to CLK4 can
increase the flexibility of this assignment process. See 7.8 Serial Interface with Time Slot
Assigner for more details.
TO
PADAT
BIT 1
TO
TXD1
OUTPUT
LATCH
MUX
EN
0
1
Figure 7-98. Parallel Block Diagram for PA1
EN
Freescale Semiconductor, Inc.
For More Information On This Product,
16 BITS
PADIR
0
1
MC68360 USER’S MANUAL
Go to: www.freescale.com
MUX
EN
EN
16 BITS
PAPAR
1
0
MUX
EN
16 BITS
PAODR
OPEN
DRAIN
CNTL
EN
Parallel I/O Ports
TXD1/PA1
PIN