RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


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Processor Interface

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7.0

Processor Interface

7.1
Alphabetical Signals Reference
Table 33. Signal Description (Sheet 1 of 8)
Name
Type
A20M#
A[35:3]#
I/O
ADS#
I/O
AERR#
I/O
AP[1:0]#
I/O
BCLK/BCLK#
Datasheet
LV Intel
If the A20M# (Address-20 Mask) input signal is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any internal cache and
before driving a read/write transaction on the bus. Asserting A20M# emulates the
8086 processor's address wrap-around at the 1 MB boundary. Assertion of A20M#
I
is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
The A[35:3]# (Address) signals define a 2
When ADS# is active, these balls transmit the address of a transaction; when ADS#
is inactive, these balls transmit transaction type information. These signals must
connect the appropriate balls of all agents on the processor system bus. The
A[35:24]# signals are parity-protected by the AP1# parity signal, and the A[23:3]#
signals are parity-protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[35:3]#
balls to determine their power-on configuration. See the P6 Family of Processors
Hardware Developer’s Manual for details.
The ADS# (Address Strobe) signal is asserted to indicate the validity of the
transaction address on the A[35:3]# balls. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
This signal must connect the appropriate balls on all processor system bus agents.
The AERR# (Address Parity Error) signal is observed and driven by all processor
system bus agents, and if used, must connect the appropriate balls on all processor
system bus agents. AERR# observation is optionally enabled during power-on
configuration; if enabled, a valid assertion of AERR# aborts the current transaction.
If AERR# observation is disabled during power-on configuration, a central agent
may handle an assertion of AERR# as appropriate to the error handling architecture
of the system.
The AP[1:0]# (Address Parity) signals are driven by the request initiator along with
ADS#, A[35:3]#, REQ[4:0]#, and RP#. AP1# covers A[35:24]#, and AP0# covers
A[23:3]#. A correct parity signal is high if an even number of covered signals are
low and low if an odd number of covered signals are low. This allows parity to be
high when all the covered signals are high. AP[1:0]# should connect the appropriate
balls of all processor system bus agents.
The BCLK (Bus Clock) and BCLK# (for differential clock) signals determines the
bus frequency. All processor system bus agents must receive this signal to drive
their outputs and latch their inputs on the rising edge of BCLK. For differential
I
clocking, all processor system bus agents must receive this signal to drive their
outputs and latch their inputs on the BCLK and BCLK# crossing point.
All external timing parameters are specified with respect to the BCLK signal.
®
®
Pentium
III Processor 512K
Description
36
-byte physical memory address space.
59