RJ80530KZ933512

Manufacturer Part NumberRJ80530KZ933512
DescriptionLow Voltage Pentium III Processor with 512 kB L2 Cache
ManufacturerIntel Corporation
RJ80530KZ933512 datasheet
 


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®
®
LV Intel
Pentium
III Processor 512K
Table 33. Signal Description (Sheet 8 of 8)
Name
Type
THERMTRIP#
TMS
TRDY#
I/O
TRST#
V
CMOS_REF
VID [3:0,25mV]
V
REF
V
TT_PWRGD
66
The processor protects itself from catastrophic overheating through the use of an
internal thermal sensor. This sensor is set well above the normal operating
temperature to ensure that there are no false trips. The processor stops all
execution when the junction temperature exceeds approximately 135 °C. This is
signaled to the system by the THERMTRIP# (Thermal Trip) ball. Once activated,
the signal remains latched, and the processor remains stopped, until RESET# goes
active or core power is removed. There is no hysteresis built into the thermal sensor
itself; when the die temperature drops below the trip level, a RESET# pulse will
reset the processor and execution continues. If the temperature does not drop
O
below the trip level, the processor drives THERMTRIP# and remains stopped.
In the event the processor drives the THERMTRIP# signal active during valid
operation, both the V
and V
CC CORE
to prevent thermal runaway of the processor. Valid operation refers to the operating
conditions where the THERMTRIP# signal is guaranteed valid. The time required
from THERMTRIP# asserted to V
CC CORE
THERMTRIP# asserted to V
rail at 1/2 nominal is 5 seconds. Once V
TT
V
supplies are turned off the THERMTRIP# signal is deactivated. System logic
TT
should ensure that no “unsafe” power cycling occurs due to this deassertion.
The TMS (Test Mode Select) signal is a JTAG specification support signal used by
I
debug tools.
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate balls of all processor system bus agents.
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. TRST#
I
must be driven low during power on Reset.
The V
input ball supplies non-AGTL reference voltage; the voltage level
CMOS_REF
should be nominally 2/3 of V
CMOS
to determine if a signal is a logical 0 or a logical 1.
I
The Thevenin equivalent impedance of the VCMOS_REF generation circuits must
be less than 0.5 K /1 K
(i.e., top resistor 500 , bottom resistor 1 K ). Refer to
®
®
the LV Intel
Pentium
III Processor 512K Dual Processor Platform Design Guide
for implementation details.
The VID[3:0, 25 mV] (Voltage ID) balls can be used to support automatic selection
of power supply voltages. These balls are CMOS signals that must be pulled up to
3.3 V power rail with 1 K
resistors. The VID balls are needed to cleanly support
O
voltage specification variations on processors. See
balls. The power supply must supply the voltage that is requested by these balls, or
disable itself.
The V
input balls supply the AGTL reference voltage; the voltage level is
REF
I
typically 2/3 of V
. V
is used by the AGTL receivers to determine if a signal is a
TT
REF
logical 0 or a logical 1.
The VTT_PWRGD signal informs the system that the VID/BSEL signals are in their
correct logic state. During Power-up, the VID signals will be in a indeterminate state
for a small period of time. The voltage regulator or the VRM should not sample and/
I
or latch the VID signals until the VTT_PWRGD signal is asserted. The assertion of
the VTT_PWRGD signal indicates that the VID signals are stable and are driven to
the final state by the processor. Refer to
sequence for the VTT_PWRGD and the VID signals.
Description
supplies to the processor must be turned off
TT
rail at 1/2 nominal is 5 seconds and
CC CORE
. V
is used by the non-AGTL receivers
CMOS_REF
Table 5
for definitions of these
Figure 16
for the power-up timing
Datasheet
and