III Processor 512K
Table 33. Signal Description (Sheet 8 of 8)
The processor protects itself from catastrophic overheating through the use of an
internal thermal sensor. This sensor is set well above the normal operating
temperature to ensure that there are no false trips. The processor stops all
execution when the junction temperature exceeds approximately 135 °C. This is
signaled to the system by the THERMTRIP# (Thermal Trip) ball. Once activated,
the signal remains latched, and the processor remains stopped, until RESET# goes
active or core power is removed. There is no hysteresis built into the thermal sensor
itself; when the die temperature drops below the trip level, a RESET# pulse will
reset the processor and execution continues. If the temperature does not drop
below the trip level, the processor drives THERMTRIP# and remains stopped.
In the event the processor drives the THERMTRIP# signal active during valid
operation, both the V
to prevent thermal runaway of the processor. Valid operation refers to the operating
conditions where the THERMTRIP# signal is guaranteed valid. The time required
from THERMTRIP# asserted to V
THERMTRIP# asserted to V
rail at 1/2 nominal is 5 seconds. Once V
supplies are turned off the THERMTRIP# signal is deactivated. System logic
should ensure that no “unsafe” power cycling occurs due to this deassertion.
The TMS (Test Mode Select) signal is a JTAG specification support signal used by
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate balls of all processor system bus agents.
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
input ball supplies non-AGTL reference voltage; the voltage level
should be nominally 2/3 of V
to determine if a signal is a logical 0 or a logical 1.
The Thevenin equivalent impedance of the VCMOS_REF generation circuits must
be less than 0.5 K /1 K
(i.e., top resistor 500 , bottom resistor 1 K ). Refer to
the LV Intel
III Processor 512K Dual Processor Platform Design Guide
for implementation details.
The VID[3:0, 25 mV] (Voltage ID) balls can be used to support automatic selection
of power supply voltages. These balls are CMOS signals that must be pulled up to
3.3 V power rail with 1 K
resistors. The VID balls are needed to cleanly support
voltage specification variations on processors. See
balls. The power supply must supply the voltage that is requested by these balls, or
input balls supply the AGTL reference voltage; the voltage level is
typically 2/3 of V
is used by the AGTL receivers to determine if a signal is a
logical 0 or a logical 1.
The VTT_PWRGD signal informs the system that the VID/BSEL signals are in their
correct logic state. During Power-up, the VID signals will be in a indeterminate state
for a small period of time. The voltage regulator or the VRM should not sample and/
or latch the VID signals until the VTT_PWRGD signal is asserted. The assertion of
the VTT_PWRGD signal indicates that the VID signals are stable and are driven to
the final state by the processor. Refer to
sequence for the VTT_PWRGD and the VID signals.
supplies to the processor must be turned off
rail at 1/2 nominal is 5 seconds and
is used by the non-AGTL receivers
for definitions of these
for the power-up timing