AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 109

• Manufacturer Part Number: AT32UC3A464
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.2.14.11
9.3
9.3.1
9.3.2
32002F–03/2010
Debug Port
Overview
JTAG
Debug Program Counter (DPC)
This register contains the PC value of the last executed instruction in any non-debug mode. This
allows a debugger to sample program execution addresses for statistical purposes without inter-
rupting the CPU.
If this register is read in Debug Mode, it will reflect the last executed instruction before Debug
Mode was entered. Note that several types of breakpoints trigger before an instruction is exe-
cuted, so this value is not necessarily identical to RAR_DBG.
When replacing the return instruction from Debug Mode, the CPU will see the DPC value as the
PC value for the executed instruction. The user only needs to write this register when replacing
the return instruction from OCD Mode.
Table 9-15.
The OCD debug port consists of the JTAG port and the AUX port. The low bandwidth JTAG port
handles all register access, while the high bandwidth AUX port transfers all Nexus messages
from the OCD system.
The Nexus standard defines the maximum clock frequency for JTAG to be 33 MHz, and for AUX
200 MHz.
Access to OCD register is done through an IEEE1149.1 JTAG-port. The JTAG TAP controller is
shared with the rest of the system. In order to enable access to OCD register the emulator must
perform the following sequence.
R/W
R/W
1. Put the TAP controller in the state "test logic reset".
2. Insert the OCD Instruction to prepare the Debug Port to receive OCD register access.
3. Use the DR scan path to insert the OCD register address and operation (Read / Write).
4. Use the DR scan path to read / write the data to / from the register.
5. Repeat 3 through 4 for every register operation. The TAP controller will remain in OCD
The OCD instruction is inserted using the IR scan path.
mode until a test logic reset is detected.
Bit Number
31:0
Debug Program Counter
Field Name
DPC
Init. Val.
0
Description
DPC - Debug Program Counter
PC of the last executed instruction
AVR32
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