AT80C51RD2 Atmel Corporation, AT80C51RD2 Datasheet
AT80C51RD2
Specifications of AT80C51RD2
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AT80C51RD2 Summary of contents
Page 1
... High-speed Architecture – MHz in Standard Mode • 16K/32K Bytes On-Chip ROM Program • AT80C51RD2 ROMless Versions • On-Chip 1024 bytes Expanded RAM (XRAM) – Software Selectable Size (0, 256, 512, 768, 1024 bytes) – 256 Bytes Selected at Reset • Keyboard Interrupt Interface on Port P1 • ...
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... Description AT80C51RD2 microcontrollers are high performance versions of the 80C51 8-bit microcontrollers. The microcontrollers retain all features of the Atmel 80C52 with 256 bytes of internal RAM source 4-level interrupt controller and three timer/counters. In addition, the microcontrollers have a Programmable Counter Array, an XRAM of 1024 byte, a Hardware Watchdog Timer, a Keyboard Interface, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode) ...
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... P0.4/AD4 33 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 29 EA VQFP44 1.4 28 NIC* 27 ALE/PROG 26 PSEN 25 P2.7/A15 24 P2.6/A14 23 P2.5/A13 AT80C51RD2 P0.4/AD4 8 38 P0.5/AD5 9 37 P0.6/AD6 10 36 P0.7/AD7 PLCC44 34 NIC ALE/PROG 14 32 PSEN 15 31 P2.7/A15 ...
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... XTAL1 19 21 XTAL2 18 20 AT80C51RD2 4 VQFP44 1.4 Type Name and Function 16 I Ground: 0V reference Power Supply: This is the power supply voltage for normal, idle and power-down 38 I operation I/O Port 0: Port open-drain, bi-directional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs ...
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... PSEN is not activated during fetches from internal program memory. External Access Enable: EA must be externally held low to enable the device fetch code from external program memory locations. If security level 1 is programmed, EA will be internally latched on Reset. AT80C51RD2 permits a power-on reset SS . This pin is an output when the hardware CC 5 ...
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... Hardware Watchdog Timer registers: WDTRST, WDTPRG • Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1 • Keyboard Interface registers: KBE, KBF, KBLS • BRG (Baud Rate Generator) registers: BRL, BDRCON • Clock Prescaler register: CKRL • Others: AUXR, AUXR1, CKCON0, CKCON1 AT80C51RD2 6 4113D–8051–01/09 ...
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... XXX0 0000 0000 0000 TL0 TL1 TH0 0000 0000 0000 0000 0000 0000 DPL DPH 0000 0000 0000 0000 2/A 3/B 4/C AT80C51RD2 5/D 6/E 7/F CCAPL3H CCAPL4H XXXX XXXX XXXX XXXX CCAPL3L CCAPL4L XXXX XXXX XXXX XXXX CCAPM3 CCAPM4 X000 0000 X000 0000 TH2 ...
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... CKRL = FFh signal selects OSC: F • Any value between FFh down to 00h can be written by software into CKRL register in order to divide frequency of the selected oscillator: – CKRL = 00h: minimum frequency – CKRL = FFh: maximum frequency – F AT80C51RD2 8 Clock Reload Register ...
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... XTAL1 ÷ avoid glitches when switching from X2 to standard mode. switching mode waveforms. Figure 6-1. Clock Generation Diagram XTAL1 F XTAL 4113D–8051–01/09 shows the clock generation block diagram. X2 bit is validated on the rising edge of CKRL F XTAL1:2 OSC 2 0 8-bit Prescaler 1 X2 CKCON0 AT80C51RD2 Figure 6-2 shows the CLK Periph CLK CPU Idle 9 ...
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... These bits are active only in X2 mode. Table 6-1. CKCON0 - Clock Control Register (8Fh Bit Number 7 6 AT80C51RD2 10 F OSC X2 Mode CKCON0 Register WDX2 PCAX2 ...
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... Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. X2 Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2" bits. Programmed by hardware after Power-up regarding Hardware Config Byte (HCB). AT80C51RD2 11 ...
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... Table 7-1. AUXR1- Auxiliary Register 1(0A2h Bit Number Reset Value: XXXX XXXX0b Not bit addressable Note: AT80C51RD2 12 DPTR1 DPTR0 DPH(83H) DPL(82H) AUXR1 Register Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. ...
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... In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruc- tion (INC AUXR1), the routine will exit with DPS in the opposite state. 4113D–8051–01/09 AUXR1 EQU 0A2H AT80C51RD2 13 ...
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... Table 8-1. Table 8-1. T83C51RB2/RC2 T80C51RD2 The AT80C51RD2 has internal data memory that is mapped into four separate segments. The four segments are: 1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable. 2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only. ...
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... Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods M0 (default). Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods. Reserved - The value read from this bit is indeterminate. Do not set this bit AT80C51RD2 XRS1 XRS0 EXTRAM ...
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... Bit Number Reset Value = XX0X 00’HSB.XRAM’0b (see Not bit addressable AT80C51RD2 16 Bit Mnemonic Description XRS1 XRAM Size XRS1 XRS0 XRAM Size 0 0 256 bytes (default 512 bytes XRS0 1 0 768 bytes 1 1 1024 bytes EXTRAM bit Cleared to access internal XRAM using MOVX @ Ri/ @ DPTR. ...
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... Timer 2 The Timer 2 in the AT80C51RD2 is the standard C52 Timer 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded controlled by T2CON (Table 9-1) and T2MOD (Table 9-2) registers. Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F pin T2 (counter operation) as the timer clock input ...
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... Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. • Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different one depending on the application. • To start the timer, set TR2 run control bit in T2CON register. AT80C51RD2 ...
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... Figure 9-2. Table 9-1. T2CON - Timer 2 Control Register (C8h) 7 TF2 4113D–8051–01/09 Clock-Out Mode C/ CLK PERIPH T2 T2EX T2CON Register EXF2 RCLK TCLK AT80C51RD2 TR2 T2CON TH2 TL2 (8-bit) (8-bit) RCAP2H RCAP2L (8-bit) (8-bit) Toggle Q D T2OE T2MOD EXF2 T2CON EXEN2 ...
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... Reset Value = 0000 0000b Bit addressable AT80C51RD2 20 Bit Mnemonic Description Timer 2 overflow Flag TF2 Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2 = 1 ...
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... The value read from this bit is indeterminate. Do not set this bit. Timer 2 Output Enable bit T2OE Cleared to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. Down Counter Enable bit DCEN Cleared to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter. AT80C51RD2 T2OE 0 DCEN ...
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... The PCA timer is a common time base for all five modules (see Figure 10-1). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD register (Table 10-1) and can be programmed to run at: • 1/6 the • 1/2 the • The Timer 0 overflow • The input on the ECI pin (P1.2) AT80C51RD2 22 ÷ ) CLK PERIPH ÷ ) ...
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... Figure 10-1. PCA Timer/Counter F /6 CLK PERIPH F /2 CLK PERIPH T0 OVF P1.2 Idle 4113D–8051–01/09 CH 16-Bit Up/Down Counter CIDL CPS1 CPS0 WDTE CF CR CCF4 CCF3 CCF2 CCF1 CCF0 AT80C51RD2 To PCA Modules Overflow It CL CMOD ECF 0xD9 CCON 0xD8 23 ...
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... Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit. • Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. AT80C51RD2 24 CMOD Register 6 5 ...
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... Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 1 interrupt flag CCF1 Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 0 interrupt flag CCF0 Must be cleared by software. Set by hardware when a match or capture occurs. AT80C51RD2 CCF3 CCF2 CCF1 0 CCF0 25 ...
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... The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. • The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. AT80C51RD2 CCF4 CCF3 CCF2 CCF1 CCF0 ECCFn CCAPMn ...
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... Set to enable the CEXn pin to be used as a pulse width modulated output. Enable CCF interrupt Cleared to disable compare/capture flag CCFn in the CCON register to generate an CCF0 interrupt. Set to enable compare/capture flag CCFn in the CCON register to generate an interrupt. AT80C51RD2 MATn TOGn PWMn ...
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... CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh) CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh) CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh Bit Number 7-0 Reset Value = 0000 0000b Not bit addressable AT80C51RD2 28 PCA Module Modes (CCAPMn Registers) CAPPn CAPNn MATn TOGn ...
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... Not bit addressable 4113D–8051–01/09 CCAPnL Registers ( Bit Mnemonic Description PCA Module n Compare/Capture Control - CCAPnL Value CH Register Bit Mnemonic Description PCA counter - CH Value CL Register Bit Mnemonic Description PCA Counter - CL Value AT80C51RD2 ...
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... CCAPMn register. The PCA timer will be compared to the module's capture regis- ters and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 10-4). AT80C51RD2 30 CCF4 CCF3 CCF2 CCF1 CCF0 ...
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... A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit. 4113D–8051–01/09 CF CCF4 CCF3 CR CCAPnH CCAPnL Match 16 bit comparator CH CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CIDL WDTE AT80C51RD2 CCON 0xD8 CCF2 CCF1 CCF0 PCA IT RESET * CCAPMn 0xDA to 0xDE CMOD CPS1 CPS0 ECF 0xD9 31 ...
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... When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. AT80C51RD2 ...
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... Thus, in most applications the first solution is the best option. This watchdog timer won’t generate a reset out on the reset pin. 4113D–8051–01/09 CCAPnH Overflow CCAPnL Enable 8-Bit Comparator CL PCA Counter/Timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn AT80C51RD2 “0” CEXn “1” CCAPMn 0xDA to 0xDE 33 ...
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... Serial I/O Port The serial I/O port in the AT80C51RD2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Univer- sal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud ...
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... FE SMOD0 = 1 The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). SADDR0101 0110b SADEN1111 1100b Given0101 01XXb SADEN1111 1010b Given1111 0X0Xb SADEN1111 1001b AT80C51RD2 Data Byte Ninth Stop Bit ...
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... For slaves A and B, bit don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. AT80C51RD2 36 Given1111 0XX1b ...
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... Figure 11-4. Baud Rate selection 4113D–8051–01/09 SADEN Register SADEN - Slave Address Mask Register (B9h SADDR Register TIMER1 TI MER_BRG_RX 0 TIMER2 1 RCLK INT_BRG TIMER1 TIMER_BRG_TX 0 TI MER2 1 TCLK INT_BRG AT80C51RD2 Clock 1 RBCK Clock TBCK ...
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... BRL reload value, the value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1 bit in PCON register. Figure 11-5. Internal Baud Rate Peripheral clock BRR • The baud rate for UART is token by formula: BaudRate ( BRL AT80C51RD2 38 Baud Rate Selection Table UART RCLK TBCK (T2CON) (BDRCON ...
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... Set by hardware at the end of the 8th bit time in mode the beginning of the stop bit in the other modes. Receive Interrupt flag Clear to acknowledge interrupt. RI Set by hardware at the end of the 8th bit time in mode 0, see Figure 11-2. and Figure 11-3. in the other modes. AT80C51RD2 TB8 RB8 TI ...
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... UART Registers Table 11-7. SADEN - Slave Address Mask Register for UART (B9h) 7 Reset Value = 0000 0000b Table 11-8. SADDR - Slave Address Register for UART (A9h) 7 Reset Value = 0000 0000b AT80C51RD2 40 Example of Computed Value when SMOD1 = 1, SPD = 1 F =16.384 MHz OSC BRL 247 238 ...
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... SBUF - Serial Buffer Register for UART (99h) 7 Reset Value = XXXX XXXXb Table 11-10. BRL Register BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah) 7 Reset Value = 0000 0000b 4113D–8051–01/09 SBUF Register AT80C51RD2 ...
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... T2CON - Timer 2 Control Register (C8h) 7 TF2 Bit Number Reset Value = 0000 0000b Bit addressable AT80C51RD2 EXF2 RCLK TCLK Bit Mnemonic Description Timer 2 overflow Flag TF2 Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK=0 and TCLK=0. ...
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... Cleared by user for general purpose usage. Set by user for general purpose usage. Power-down mode bit PD Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit IDL Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. AT80C51RD2 GF1 GF0 PD 0 IDL 43 ...
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... Table 11-13. BDRCON Register BDRCON - Baud Rate Control Register (9Bh Bit Number Reset Value = XXX0 0000b Not bit addressable AT80C51RD2 BRR Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit Reserved - The value read from this bit is indeterminate ...
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... Interrupt System The AT80C51RD2 have a total of 8 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 12-1. Figure 12-1. Interrupt Control System ...
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... If interrupt requests of the same priority level are received simul- taneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. Table 12-2. IE0 - Interrupt Enable Register (A8h) AT80C51RD2 46 Priority Level Bit Values IPH.x 0 ...
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... Refer to PX1H for priority level. Timer 0 overflow interrupt priority bit 1 PT0L Refer to PT0H for priority level. External interrupt 0 priority bit 0 PX0L Refer to PX0H for priority level. IPH0 Register PPCH PT2H AT80C51RD2 PSL PT1L PX1L PT0L PSH PT1H PX1H PT0H 1 ...
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... Reset Value = X000 0000b Not bit addressable Table 12-5. IE1 - Interrupt Enable Register (B1h) AT80C51RD2 48 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt priority high bit. PPCHPPCLPriority Level 0 0Lowest 6 PPCH ...
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... The value read from this bit is indeterminate. Do not set this bit. Reserved 2 - The value read from this bit is indeterminate. Do not set this bit. Reserved 1 - The value read from this bit is indeterminate. Do not set this bit. Keyboard Interrupt Priority bit 0 KBDL Refer to KBDH for priority level. IPH1 Register AT80C51RD2 KBDL 49 ...
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... IPH1 - Interrupt Priority High Register (B3h) Reset Value = XXXX XXX0b Not bit addressable 12.2 Interrupt Sources and Vector Addresses Table 12-8. AT80C51RD2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. ...
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... AT80C51RD2 51 ...
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... Keyboard Interface The AT80C51RD2 implement a keyboard interface allowing the connection matrix key- board based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power- down modes ...
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... Keyboard interrupt request if the KBIE.1 bit in KBIE register is set. Must be cleared by software. Keyboard line 0 flag Set by hardware when the Port line 0 detects a programmed level. It generates a 0 KBF0 Keyboard interrupt request if the KBIE.0 bit in KBIE register is set. Must be cleared by software. AT80C51RD2 KBF4 KBF3 KBF2 KBF1 ...
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... Table 13-2. KBE - Keyboard Input Enable Register (9Dh) Reset Value = 0000 0000b AT80C51RD2 54 KBE Register KBE7 KBE6 KBE5 KBE4 Bit Bit Number Mnemonic Description Keyboard line 7 enable bit 7 KBE7 Cleared to enable standard I/O pin. Set to enable KBF.7 bit in KBF register to generate an interrupt request. ...
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... KBLS1 Cleared to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1. Keyboard line 0 level selection bit 0 KBLS0 Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0. AT80C51RD2 KBLS3 KBLS2 KBLS1 ...
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... In this case, the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put AT80C51RD2 into power-down mode. AT80C51RD2 56 can be lowered to save further power ...
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... ALE PSEN PORT0 1 1 Port Data 1 1 Floating 0 0 Port Dat 0 0 Floating AT80C51RD2 Active Phase PORT1 PORT2 (1) Port Data Port Data Port Data Address (1) Port Data Port Data Port Data Port Data PORT3 Port Data ...
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... F description, Table 15-1. WDTRST - Watchdog Reset Register (0A6h) Reset Value = XXXX XXXXb Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. AT80C51RD2 make the best use of the WDT, it should be serviced in those sec- CLK PERIPH 7 counter has been added to extend the Time-out capability MHz ...
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... WDT just before entering power-down. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT80C51RD2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. ...
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... Table 16-1. PCON - Power Control Register (87h) Reset Value = 00X1 0000b Not bit addressable AT80C51RD2 60 switch-on. A warm start reset occurs while V CC rises from 0 to its nominal voltage. The POF can be set or cleared by software allow- ...
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... Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting, XRAM selected. ALE Output bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1 mode is used) (default). Set, ALE is active only during a MOVX or MOVC instructione is used. AT80C51RD2 XRS1 XRS0 ...
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... AT80C51RD2 62 4113D–8051–01/09 ...
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... Input Leakage Current LI I Logical Transition Current, ports Capacitance of I/O Buffer IO I Power-down Current PD I Power Supply Current on normal mode CCOP I Power Supply Current on idle mode CCIDLE AT80C51RD2 60 Note: + 0.5V CC =4.5V to 5.5V MHz Min Typ -0.5 0 0 (6) ( ...
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... 200 120 . I would be slightly higher if a crystal oscillator used (see RST = V (see CC SS must be externally limited as follows: OL may exceed the related specification. Pins are not guaranteed to sink current greater OL AT80C51RD2 (5) Max Unit 0.45 V 0.45 V ...
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... Figure 17-1. I Figure 17-2. I Figure 17-3. I AT80C51RD2 62 Test Condition, Active Mode RST EA (NC) XTAL2 CLOCK XTAL1 SIGNAL V SS Test Condition, Idle Mode RST EA XTAL2 (NC) CLOCK XTAL1 SIGNAL V SS Test Condition, Power-down Mode ...
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... CCIV 4113D–8051–01/09 V -0.5V 0.7V CC 0.2V 0.45V T T CLCH CHCL 5ns. CLCH CHCL = Time for Address Valid to ALE Low. AVLL = Time for ALE Low to PSEN Low. LLPL for 20 MHz, Standard clock. LLIU AT80C51RD2 Tests in Active and Idle Modes ...
Page 67
... External Program Memory Characteristics Table 17-2. Table 17-3. AT80C51RD2 64 Symbol Description Symbol Parameter T Oscillator clock period T ALE pulse width LHLL T Address Valid to ALE AVLL T Address Hold After ALE LLAX T ALE to Valid Instruction In LLIV T ALE to PSEN LLPL T PSEN Pulse Width PLPH T PSEN to Valid Instruction In ...
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... CLCL T T LHLL LLIV T LLPL T PLPH T LLAX T PLIV T T TPLAZ AVLL PXIX A0-A7 INSTR IN T AVIV ADDRESS A8 - A15 AT80C51RD2 Standard X Parameter for - Clock X2 Clock M Range ...
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... Table 17-5. Table 17-6. AT80C51RD2 66 Symbol Description Symbol Parameter T RD Pulse Width RLRH T WR Pulse Width WLWH Valid Data In RLDV T Data Hold After RD RHDX T Data Float After RD RHDZ T ALE to Valid Data In LLDV T Address to Valid Data In AVDV T ALE LLWL T Address ...
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... Max x RLAZ T Min WHLH T Max WHLH T T LLWL WLWH T QVWX T T LLAX QVWH A0-A7 DATA OUT T AVWL ADDRESS A8 - A15 OR SFR P2 AT80C51RD2 X parameter for - X2 Clock M range Units 2 4 ...
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... External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 17.3.7 Serial Port Timing - Shift Register Mode Table 17-7. Table 17-8. AT80C51RD2 68 T LLDV T LLWL T AVDV T LLAX A0-A7 T RLAZ T AVWL ADDRESS A8-A15 OR SFR P2 Symbol Description Symbol Parameter T Serial port clock cycle time XLXL ...
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... T XHDV VALID VALID VALID VALID V -0.5V CC 0.7V CC 0.2V -0.1 0.45V CC T CHCL V -0.5V CC 0.45V CC min for a logic “1” and V IH AT80C51RD2 Standard X Parameter for - Clock X2 Clock M Range 133 ...
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... For timing purposes as port pin is no longer floating when a 100 mV changes from load voltage occurs and begins to float when a 100 mV change from the loaded V ≥ ± 20 mA. 17.3.12 Clock Waveforms Valid in normal clock mode mode XTAL2 must be changed to XTAL2/2. AT80C51RD2 70 FLOAT ...
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... INDICATES ADDRESS TRANSITIONS DPL OR Rt OUT FLOAT INDICATES DPH OR P2 SFR TO PCH TRANSITION DPL OR Rt OUT DATA OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION OLD DATA NEW DATA P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED RXD SAMPLED AT80C51RD2 STATE3 STATE4 STATE5 ...
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... Ordering Information Table 18-1. 4113D–8051–01/09 Ordering Information Part Number AT80C51RD2-3CSUM AT80C51RD2-SLSUM AT80C51RD2-RLTUM AT80C51RD2-SLRUM AT80C51RD2-RLRUM AT80C51RD2 Package Temperature Range PDIL40 Industrial & Green PLCC44 Industrial & Green VQFP44 Industrial & Green PLCC44 Industrial & Green VQFP44 Industrial & Green Packing Stick ...
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... Package Information 19.1 PDIL40 AT80C51RD2 64 4113D–8051–01/09 ...
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... PLCC44 4113D–8051–01/09 AT80C51RD2 65 ...
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... STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER SIDE. AT80C51RD2 66 4113D–8051–01/09 ...
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... VQFP44 4113D–8051–01/09 AT80C51RD2 67 ...
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... DATUM "A" AND "D" DETERMINED AT DATUM PLANE H. 6/ DIMENSION " f " DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08mm/.003" TOTAL IN EXCESS OF THE " f " DIMENSION AT MAXIMUM MATERIAL CONDITION . DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. AT80C51RD2 68 4113D–8051–01/09 ...
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... Datasheet Change Log 20.1 Changes from 4113A - 09/02 to 4113B -03/05 1. Added Green product ordering information. 20.2 Changes from 4113B -03/05 to 4113C -01/08 1. Removed AT80C51RD2 product offering 2. Updated Package Drawings. 20.3 Changes from 4113C -01/08 to 4113D -01/09 1. Removed AT83C51RD2 product offering 4113D–8051–01/09 AT80C51RD2 Table 18-1 on page 63. 69 ...